TW202133401A - 形成三維半導體結構的方法 - Google Patents

形成三維半導體結構的方法 Download PDF

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TW202133401A
TW202133401A TW109112841A TW109112841A TW202133401A TW 202133401 A TW202133401 A TW 202133401A TW 109112841 A TW109112841 A TW 109112841A TW 109112841 A TW109112841 A TW 109112841A TW 202133401 A TW202133401 A TW 202133401A
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Taiwan
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hole
dielectric layer
substrate
interlayer dielectric
circuit
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TW109112841A
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TWI732526B (zh
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施信益
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南亞科技股份有限公司
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Abstract

一種形成三維半導體結構的方法，包括：形成介電穿孔，從第一元件的第一層間介電層的第一表面延伸至第一層間介電層內；藉由第一層間介電層的第一表面和第二元件的第二表面黏合第一元件和第二元件，使得第二表面上的通矽接觸墊覆蓋介電穿孔；執行蝕刻製程在第一元件的背面上以同時形成第一通孔和第二通孔，並通過第二通孔露出通矽接觸墊，前述背面背向第一層間介電層；以及形成第一通孔插塞以填充第一通孔，以及第二通孔插塞以填充第二通孔和介電穿孔。

Description

形成三維半導體結構的方法
本揭示內容係關於一種形成三維半導體結構的方法。
此處的陳述僅提供與本揭示有關的背景信息，而不必然地構成現有技術。
隨著電子元件密度的增加，三維電路佈線方案的開發已啟動。近年來，連接上部電子元件和下部電子元件的矽穿孔（through silicon via，TSV）技術蓬勃發展。形成TSV的過程可從上部電子元件的表面開始。TSV結構的完成能夠電性連接至上部電子元件的電路互連部和下部電子元件的電路互連部，並且能夠接收外部信號。然而，在一般情況下，須完成多步蝕刻製程才能完成TSV結構。最近來亦有一種替代方法，在上部電子元件中的特定部分嵌入蝕刻延遲結構，從而可在同一蝕刻製程中產生不同深度的TSV。接著形成可從上部電子元件的一表面與上部電子元件和下部電子元件直接電性連接的三維電路結構。
本揭示的一些實施方式揭露了一種三維半導體結構的方法，包括：製備第一元件，第一元件具有第一電路和第一層間介電層設置在第一基板上，其中第一層間介電層圍繞第一電路並接觸第一基板；形成介電穿孔，從第一層間介電層的第一表面延伸至第一層間介電層內，其中第一表面背向第一基板；藉由第一層間介電層的第一表面和第二元件的第二表面黏合第一元件和第二元件，使得從第二元件的第二表面露出的通矽接觸墊覆蓋介電穿孔；以及執行蝕刻製程在第一元件的背面上以同時形成第一通孔和第二通孔，並通過第二通孔露出通矽接觸墊，前述背面背向第一層間介電層。
於本揭示的一或多個實施方式中，第二元件更由下述方法製備：形成第二電路和第二層間介電層於第二基板上，其中第二層間介電層圍繞第二電路，通矽接觸墊是在第二層間介電層的第二表面上，且第二表面背向第二基版。
於本揭示的一或多個實施方式中，黏合包括混成黏合第一元件和第二元件，使得第一電路的第一導電墊黏合至第二電路的第二導電墊，第一層間介電層黏合至第二層間介電層，其中第一導電墊從第一表面露出並與第一電路的多個第一互連部的一部分接觸，且第二導電墊從第二表面露出並與第二電路的多個第二互連部的一部分接觸。
於本揭示的一或多個實施方式中，更包括在執行蝕刻製程之前從第一基板的背面部分移除第一基板。
於本揭示的一或多個實施方式中，部分移除是通過矽研磨進行。
於本揭示的一或多個實施方式中，更包括在執行蝕刻製程之前形成鈍化層於第一基板的背面上。
於本揭示的一或多個實施方式中，執行蝕刻製程包括：蝕刻第一基板的背面以形成第一盲孔和第二盲孔，使得第一盲孔的第一暫時端緊鄰第一電路的多個第一互連部當中的一個，且第二盲孔的第二暫時端緊鄰介電穿孔；共形地形成隔離層於第一盲孔和第二盲孔中；以及蝕刻第一基板的背面以從第一盲孔形成第一通孔，以及從第二盲孔形成第二通孔。
於本揭示的一或多個實施方式中，蝕刻隔離層是通過乾蝕刻進行。
於本揭示的一或多個實施方式中，蝕刻第一基板的背面以從第一盲孔形成第一通孔，以及從第二盲孔形成第二通孔包括：蝕刻隔離層和第一層間介電層直到第一電路的多個第一互連部當中的一個從第一通孔露出，且通矽接觸墊從第二通孔露出。
於本揭示的一或多個實施方式中，第二通孔的直徑大於介電穿孔的直徑。
於本揭示的一或多個實施方式中，第一通孔和第二通孔的形成使得第一電路的多個第一互連部當中的一個從第一通孔露出，且通矽接觸墊從第二通孔露出。
於本揭示的一或多個實施方式中，更包括形成第一通孔插塞以填充第一通孔，以及第二通孔插塞以填充第二通孔和介電穿孔，其中第一通孔插塞接觸第一電路的多個第一互連部當中的一個，且第二通孔插塞接觸通矽接觸墊。
本揭示的上述實施方式能夠藉由實質上一個蝕刻和一個沉積製程，在三維半導體結構的一個表面上同時形成電性連接至第一元件和第二元件。其省去了用於在執行蝕刻製程時降低形成某些通孔之蝕刻速率的額外蝕刻延遲結構。
為了讓本揭示的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
為使本揭示之敘述更加詳盡與完備，下文針對了本揭示的實施態樣與具體實施例提出了說明性的描述；但這並非實施或運用本揭示具體實施例的唯一形式。以下所揭露的各實施例，在有益的情形下可相互組合或取代，也可在一實施例中附加其他的實施例，而無須進一步的記載或說明。
在以下的描述中，將詳細敘述許多特定細節以使讀者能夠充分理解以下的實施例。然而，可在無此等特定細節之情況下實踐本揭示之實施例。在其他情況下，為簡化圖式，熟知的結構與裝置僅示意性地繪示於圖中。
參考第1圖至第9圖。第1圖繪示本揭示一些實施例中形成三維半導體結構的方法S的流程圖。第2A圖至第9圖繪示本揭示一些實施例中第1圖所描述之方法S的中間階段的剖面示意圖。方法S從操作S1開始，製備第一元件110。第一元件110具有第一電路114和第一層間介電層116，其皆設置在第一基板112上。其中，第一層間介電層116圍繞第一電路114並接觸第一基板112（參考第2A圖）。在一些實施例中，第一電路114嵌入第一層間介電層116。詳細而言，第一層間介電層116包圍並接觸第一電路114的第一互連部1142。第一電路114的第一導電墊1144電性連接第一互連部1142並接觸第一層間介電層116。此外，第一導電墊1144從第一層間介電層116的第一表面1102露出，其中第一表面1102背向第一基板112。在一些實施例中，第一元件110是以在第一基板112上形成（例如，以沉積方式形成）第一電路114和第一層間介電層116的方式製備。
方法S接著進行操作S2，形成介電穿孔118，從第一層間介電層116的第一表面1102延伸至第一層間介電層116內（亦參考第2A圖）。介電穿孔118可用例如濕蝕刻或乾蝕刻的方式形成，但不以此為限。方法S接著進行操作S3，藉由第一層間介電層116的第一表面1102和第二元件120的第二表面1202黏合第一元件110和第二元件120，使得從第二元件120的第二表面1202露出的通矽接觸墊128覆蓋介電穿孔118（參考第2B圖和第3圖）。在一些實施例中，混成黏合（hybrid bonding）第一元件110和第二元件120，使得第一電路114的一些第一導電墊1144黏合並接觸第二電路124的一些第二導電墊1244，且第一層間介電層116黏合並接觸第二元件120的第二層間介電層126。在一些實施例中，第一導電墊1144從第一表面1102露出並與第一互連部1142的一部分接觸，且第二導電墊1244從第二表面1202露出並與第二互連部1242的一部分接觸。第一互連部1142和第二互連部1242可分別是分布並嵌入於第一層間介電層116和第二層間介電層126中以形成多層電路的電路。第一互連部1142和第二互連部1242亦可包括導電墊，其連接不同電路層。
第一互連部1142、第二互連部1242、第一導電墊1144和第二導電墊1244可包括金屬，例如鎢（tungsten，W）、鋁（aluminum，Al）、銅（copper，Cu），或是金屬矽化物（metal silicides），例如二矽化鎢（tungsten silicide，WSi2 ）、二矽化鈦（titanium silicide，TiSi2 ），或是金屬化合物，例如氮化鎢（tungsten nitride，W3 N2 ）、氮化鈦（titanium nitride，TiN），或多晶矽（polycrystalline silicon，poly-Si）或其組合，但不以此為限。
第一層間介電層116和第二層間介電層126可包括絕緣材料，例如二氧化矽（silicon dioxide，SiO2 ），但不以此為限。
在一些實施例中，第二元件120是以在第二基板122上形成（例如，以沉積方式形成）第二電路124和第二層間介電層126的方式製備。第二層間介電層126圍繞第二電路124。通矽接觸墊128從第二層間介電層126的第二表面1202露出，第二表面1202背向第二基板122。
第一基板112和第二基板122可包括塊材單晶矽晶圓、絕緣層上矽晶（silicon-on-insulator，SOI）、化合物半導體，例如矽鍺（silicon-germanium，SiGe），或矽磊晶層長於其上的晶圓，但不以此為限。
方法S接著進行操作S4，執行蝕刻製程於第一基板112背向第一層間介電層116的背面1104上以同時形成第一通孔V1和第二通孔V2，並通過第二通孔V2露出通矽接觸墊128（參考第3圖和第8圖）。在一些實施例中，第一通孔V1預對準其中一個上述的第一互連部1142。在第一通孔V1和第二通孔V2形成前，第二通孔V2的位置預對準通矽接觸墊128。在一些實施例中，於操作S3後，在執行蝕刻製程前從第一基板112的背面1104部分去除第一基板112（參考第4圖）。在一些實施例中，部分去除是藉由矽研磨方式，但不以此為限。藉由矽研磨，更容易讓接下來的蝕刻製程能蝕刻穿過第一基板112。在一些實施例中，在執行蝕刻製程前，鈍化層130形成於第一基板112的背面1104上（參考第5圖）。在那之後，可在背面1104上執行乾蝕刻製程以移除一部分的鈍化層130，接著可執行濕蝕刻製程以形成第一盲孔B1和第二盲孔B2（參考第6圖）。應注意，去除前述一部分的鈍化層130以及形成第一盲孔B1和第二盲孔B2的操作不限於上述的製程。在一些其它實施例中，去除前述一部分的鈍化層130以及形成第一盲孔B1和第二盲孔B2可於單一乾蝕刻製程中執行。在前面提到的實施例中，第一盲孔B1的第一暫時端T1緊鄰（例如，延伸進層間介電層116）其中一個第一互連部1142，且第二盲孔B2的第二暫時端T2緊鄰（例如，延伸進層間介電層116）介電穿孔118。鈍化層130可包括二氧化矽（silicon dioxide，SiO2 ）、氮化矽（silicon nitride，SiNx ）或有機材料，例如苯環丁烯（benzocyclobutene，BCB），但不以此為限。
在一些實施例中，隔離層140共形地形成於第一盲孔B1和第二盲孔B2內（參考第7圖）。隔離層140可包括絕緣材料，例如和用於鈍化層130之材料相同的材料，但不以此為限。隔離層140可形成於第一基板112的第一盲孔B1中的第一內壁I1、第一暫時端T1、第一基板112的第二盲孔B2中的第二內壁I2以及第二暫時端T2上，但不以此為限。在形成隔離層140後，接著蝕刻第一基板112的背面1104以從第一盲孔B1形成第一通孔V1，並從第二盲孔B2形成第二通孔V2（參考第8圖）。在一些實施例中，蝕刻隔離層140和第一層間介電層116直到其中一個上述的第一互連部1142自第一通孔V1露出，且通矽接觸墊128自第二通孔V2露出。
方法S接著進行操作S5，形成第一通孔插塞P1以填充第一通孔V1，以及第二通孔插塞P2以填充第二通孔V2和介電穿孔118。第一通孔插塞P1和第二通孔插塞P2可包括金屬，例如鎢、鋁、鈷、鎳和銅，和/或金屬矽化物，但不以此為限。第一通孔插塞P1接觸第一電路114之前述的其中一個第一互連部1142，且第二通孔插塞P2接觸通矽接觸墊128。在第一盲孔B1內之第一內壁I1上的隔離層140和在第二盲孔B2內之第二內壁I2上的隔離層140防止了第一通孔插塞P1和第一基板112之間，以及第二通孔插塞P2和第一基板112之間的接觸和直接電性連接。通過以上製程，形成了三維半導體結構1000（參考第9圖）。上述製程可同時形成從第一元件110的背面1104（經由第一通孔插塞P1）直接電性連接第一互連部1142以及從第一元件110的背面1104（經由第二通孔插塞P2）直接電性連接通矽接觸墊128，而不需使用任何額外的蝕刻延遲結構來控制第一通孔V1的蝕刻速率。在一些實施例中，第二通孔V2的直徑D1大於介電穿孔118的直徑D2，從而防止第二通孔插塞P2和第一基板112之間可能的漏電流。在一些實施例中，在第一通孔插塞P1、第二通孔插塞P2和鈍化層130上執行化學機械研磨（chemical mechanical planarization，CMP）製程。亦即，於形成第一通孔插塞P1和第二通孔插塞P2後在背面1104上執行化學機械研磨製程以平坦化背面1104。
綜上所述，本揭示的實施例提供形成三維半導體結構的方法，藉由實質上一個蝕刻和一個沉積製程，可在三維半導體結構的一個表面上同時形成電性連接至第一元件和第二元件，其省去了用於在執行蝕刻製程時降低形成某些通孔之蝕刻速率的額外蝕刻延遲結構。
雖然本揭示已以實施例揭露如上，然並非用以限定本揭示，人和熟習此技藝者，在不脫離本揭示之精神和範圍內，當可作各種之更動與潤飾，因此本揭示之保護範圍當視後附之申請專利範圍所界定者為準。
1000:三維半導體結構 110:第一元件 1102:第一表面 1104:背面 112:第一基板 114:第一電路 1142:第一互連部 1144:第一導電墊 116:第一層間介電層 118:介電穿孔 120:第二元件 1202:第二表面 122:第二基板 124:第二電路 1242:第二互連部 1244:第二導電墊 126:第二層間介電層 128:通矽接觸墊 130:鈍化層 140:隔離層 B1:第一盲孔 B2:第二盲孔 D1, D2:直徑 I1:第一內壁 I2:第二內壁 P1:第一通孔插塞 P2:第二通孔插塞 S:方法 S1, S2, S3, S4, S5:操作 T1:第一暫時端 T2:第二暫時端 V1:第一通孔 V2:第二通孔
第1圖繪示本揭示一些實施例中形成三維半導體結構的方法的流程圖。 第2A圖繪示本揭示一些實施例中第1圖所描述之方法的中間階段的剖面示意圖。 第2B圖繪示本揭示一些實施例中第1圖所描述之方法的中間階段的剖面示意圖。 第3圖繪示本揭示一些實施例中第1圖所描述之方法的中間階段的剖面示意圖。 第4圖繪示本揭示一些實施例中第1圖所描述之方法的中間階段的剖面示意圖。 第5圖繪示本揭示一些實施例中第1圖所描述之方法的中間階段的剖面示意圖。 第6圖繪示本揭示一些實施例中第1圖所描述之方法的中間階段的剖面示意圖。 第7圖繪示本揭示一些實施例中第1圖所描述之方法的中間階段的剖面示意圖。 第8圖繪示本揭示一些實施例中第1圖所描述之方法的中間階段的剖面示意圖。 第9圖繪示本揭示一些實施例中第1圖所描述之方法的中間階段的剖面示意圖。
1000:三維半導體結構
110:第一元件
1102:第一表面
1104:背面
112:第一基板
114:第一電路
1142:第一互連部
1144:第一導電墊
116:第一層間介電層
120:第二元件
1202:第二表面
122:第二基板
124:第二電路
1242:第二互連部
1244:第二導電墊
126:第二層間介電層
128:通矽接觸墊
130:鈍化層
140:隔離層
D1,D2:直徑
P1:第一通孔插塞
P2:第二通孔插塞

Claims (12)

  1. 一種形成三維半導體結構的方法，包括： 製備一第一元件，該第一元件具有一第一電路和一第一層間介電層設置在一第一基板上，其中該第一層間介電層圍繞該第一電路並接觸該第一基板； 形成一介電穿孔，從該第一層間介電層的一第一表面延伸至該第一層間介電層內，其中該第一表面背向該第一基板； 藉由該第一層間介電層的該第一表面和一第二元件的一第二表面黏合該第一元件和該第二元件，使得從該第二元件的該第二表面露出的一通矽接觸墊覆蓋該介電穿孔；以及 執行一蝕刻製程在該第一元件的一背面上以同時形成一第一通孔和一第二通孔，並通過該第二通孔露出該通矽接觸墊，其中該背面背向該第一層間介電層。
  2. 如請求項1所述之方法，其中該第二元件更由下述方法製備： 形成一第二電路和一第二層間介電層於一第二基板上，其中該第二層間介電層圍繞該第二電路，該通矽接觸墊是在該第二層間介電層的該第二表面上，且該第二表面背向該第二基版。
  3. 如請求項2所述之方法，其中該黏合包括： 混成黏合該第一元件和該第二元件，使得該第一電路的一第一導電墊黏合至該第二電路的一第二導電墊，該第一層間介電層黏合至該第二層間介電層，其中該第一導電墊從該第一表面露出並與該第一電路的多個第一互連部的一部分接觸，且該第二導電墊從該第二表面露出並與該第二電路的多個第二互連部的一部分接觸。
  4. 如請求項1所述之方法，更包括在執行該蝕刻製程之前從該第一基板的該背面部分移除該第一基板。
  5. 如請求項4所述之方法，其中該部分移除是通過矽研磨進行。
  6. 如請求項1所述之方法，更包括在執行該蝕刻製程之前形成一鈍化層於該第一基板的該背面上。
  7. 如請求項1所述之方法，其中執行該蝕刻製程包括： 蝕刻該第一基板的該背面以形成一第一盲孔和一第二盲孔，使得該第一盲孔的一第一暫時端緊鄰該第一電路的多個第一互連部當中的一個，且該第二盲孔的一第二暫時端緊鄰該介電穿孔； 共形地形成一隔離層於該第一盲孔和該第二盲孔中；以及 蝕刻該第一基板的該背面以從該第一盲孔形成該第一通孔，以及從該第二盲孔形成該第二通孔。
  8. 如請求項7所述之方法，其中蝕刻該隔離層是通過乾蝕刻進行。
  9. 如請求項7所述之方法，其中蝕刻該第一基板的該背面以從該第一盲孔形成該第一通孔，以及從該第二盲孔形成該第二通孔包括： 蝕刻該隔離層和該第一層間介電層直到該第一電路的該些第一互連部當中的一個從該第一通孔露出，且該通矽接觸墊從該第二通孔露出。
  10. 如請求項1所述之方法，其中該第二通孔的直徑大於該介電穿孔的直徑。
  11. 如請求項1所述之方法，其中該第一通孔和該第二通孔的形成使得該第一電路的多個第一互連部當中的一個從該第一通孔露出，且該通矽接觸墊從該第二通孔露出。
  12. 如請求項1所述之方法，更包括： 形成一第一通孔插塞以填充該第一通孔，以及一第二通孔插塞以填充該第二通孔和該介電穿孔，其中該第一通孔插塞接觸該第一電路的多個第一互連部當中的一個，且該第二通孔插塞接觸該通矽接觸墊。
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