JP5670306B2 - 浅いトレンチ分離および基板貫通ビアの集積回路設計への統合 - Google Patents
浅いトレンチ分離および基板貫通ビアの集積回路設計への統合 Download PDFInfo
- Publication number
- JP5670306B2 JP5670306B2 JP2011273948A JP2011273948A JP5670306B2 JP 5670306 B2 JP5670306 B2 JP 5670306B2 JP 2011273948 A JP2011273948 A JP 2011273948A JP 2011273948 A JP2011273948 A JP 2011273948A JP 5670306 B2 JP5670306 B2 JP 5670306B2
- Authority
- JP
- Japan
- Prior art keywords
- opening
- substrate
- trench isolation
- shallow trench
- tsv
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims description 149
- 238000002955 isolation Methods 0.000 title claims description 32
- 238000013461 design Methods 0.000 title description 6
- 230000010354 integration Effects 0.000 title 1
- 230000036961 partial effect Effects 0.000 claims description 71
- 238000000034 method Methods 0.000 claims description 59
- 238000011049 filling Methods 0.000 claims description 35
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 52
- 239000011343 solid material Substances 0.000 description 19
- 239000000463 material Substances 0.000 description 15
- 239000011810 insulating material Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000000470 constituent Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 241000724291 Tobacco streak virus Species 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本出願は、本出願の譲受人に譲渡され、参照によりその全体が本明細書に組み込まれている、M.A.Bachman、S.M.Merchant、およびJ.Osenbach(「Bachmanら」)への「METHOD OF FABRICATION OF THROUGH−SUBSTRATE VIAS」という名称の米国特許出願第12/969,836号(整理番号L09−0808)に関連する。
Claims (3)
- 集積回路を製造する方法であって、
第1の側、および第2の対向する側を有する基板を用意すること、
前記基板の前記第1の側に浅いトレンチ分離開口を形成すること、
前記基板の前記第1の側に部分的基板貫通ビア開口を形成すること、
前記部分的基板貫通ビア開口を延長することであって、前記延長された部分的基板貫通ビア開口は、前記浅いトレンチ分離開口より前記基板内への深さが深い、前記部分的基板貫通ビア開口を延長すること、および、
前記浅いトレンチ分離開口と前記延長された部分的基板貫通ビア開口とを同じ絶縁層で同時に充填することとを含み、前記同じ絶縁層は、浅いトレンチ分離構造を画定する前記開口の側壁上と基板貫通ビアを画定する前記開口の側壁上にパッシベーション層と拡散バリア層とを含み、
前記浅いトレンチ分離開口と前記延長された部分的基板貫通ビア開口とを前記拡散バリア層と接触する誘電体材料の絶縁プラグで同時に充填し、前記延長された部分的基板貫通ビア開口の深さの全体と前記浅いトレンチ分離開口の深さの全体とを充填することと、
第2の側の基板貫通ビア開口が前記基板の前記第2の対向する側から前記第1の側まで延びるように、前記基板の前記第2の対向する側から、前記延長された部分的基板貫通ビア開口の内部の前記絶縁プラグの少なくとも一部分を除去すること、
前記絶縁プラグの少なくとも一部分を取り除いた後、前記第2の側の基板貫通ビア開口を導電性材料で充填することをさらに含む、方法。 - 前記浅いトレンチ分離構造を画定する前記開口の側壁上と前記基板貫通ビアを画定する前記開口の側壁上に前記パッシベーション層を同時に形成し、そして、前記浅いトレンチ分離構造を画定する前記開口の側壁上と前記基板貫通ビアを画定する前記開口の側壁上に前記拡散バリア層を同時に形成することをさらに含む、請求項1に記載の方法。
- 前記浅いトレンチ分離開口と前記部分的基板貫通ビア開口とが同時に形成される、請求項1に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/969,852 US8742535B2 (en) | 2010-12-16 | 2010-12-16 | Integration of shallow trench isolation and through-substrate vias into integrated circuit designs |
US12/969,852 | 2010-12-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012129528A JP2012129528A (ja) | 2012-07-05 |
JP5670306B2 true JP5670306B2 (ja) | 2015-02-18 |
Family
ID=45375226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011273948A Active JP5670306B2 (ja) | 2010-12-16 | 2011-12-15 | 浅いトレンチ分離および基板貫通ビアの集積回路設計への統合 |
Country Status (6)
Country | Link |
---|---|
US (2) | US8742535B2 (ja) |
EP (1) | EP2466634B1 (ja) |
JP (1) | JP5670306B2 (ja) |
KR (1) | KR101475108B1 (ja) |
CN (1) | CN102543829B (ja) |
TW (1) | TWI463584B (ja) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1398204B1 (it) | 2010-02-16 | 2013-02-14 | St Microelectronics Srl | Sistema e metodo per eseguire il test elettrico di vie passanti nel silicio (tsv - through silicon vias). |
US8742535B2 (en) | 2010-12-16 | 2014-06-03 | Lsi Corporation | Integration of shallow trench isolation and through-substrate vias into integrated circuit designs |
US8987137B2 (en) | 2010-12-16 | 2015-03-24 | Lsi Corporation | Method of fabrication of through-substrate vias |
US20130119543A1 (en) * | 2011-11-16 | 2013-05-16 | Globalfoundries Singapore Pte. Ltd. | Through silicon via for stacked wafer connections |
JP6034095B2 (ja) * | 2012-08-21 | 2016-11-30 | 株式会社東芝 | 半導体装置およびその製造方法 |
US9577035B2 (en) * | 2012-08-24 | 2017-02-21 | Newport Fab, Llc | Isolated through silicon vias in RF technologies |
TWI492343B (zh) * | 2012-11-02 | 2015-07-11 | 矽品精密工業股份有限公司 | 半導體基板及其製法 |
US9123789B2 (en) * | 2013-01-23 | 2015-09-01 | United Microelectronics Corp. | Chip with through silicon via electrode and method of forming the same |
DE102013208816A1 (de) * | 2013-05-14 | 2014-11-20 | Robert Bosch Gmbh | Verfahren zum Erzeugen eines Durchkontakts in einem CMOS-Substrat |
JP2015153978A (ja) * | 2014-02-18 | 2015-08-24 | キヤノン株式会社 | 貫通配線の作製方法 |
US9419075B1 (en) * | 2015-01-28 | 2016-08-16 | Texas Instruments Incorporated | Wafer substrate removal |
WO2017111847A1 (en) * | 2015-12-24 | 2017-06-29 | Intel Corporation | Techniques for forming electrically conductive features with improved alignment and capacitance reduction |
US10043740B2 (en) * | 2016-07-12 | 2018-08-07 | Intel Coporation | Package with passivated interconnects |
US10290495B2 (en) * | 2016-07-29 | 2019-05-14 | Japan Display Inc. | Electronic apparatus and manufacturing method of the same |
WO2018026002A1 (ja) * | 2016-08-04 | 2018-02-08 | 大日本印刷株式会社 | 貫通電極基板及び実装基板 |
KR102652854B1 (ko) | 2016-08-17 | 2024-04-02 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
FR3059464B1 (fr) * | 2016-11-29 | 2019-03-15 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Circuit electronique comprenant des tranchees d'isolation electrique |
US9966318B1 (en) * | 2017-01-31 | 2018-05-08 | Stmicroelectronics S.R.L. | System for electrical testing of through silicon vias (TSVs) |
JP2018129412A (ja) * | 2017-02-09 | 2018-08-16 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、および半導体装置の製造方法 |
JP6640780B2 (ja) | 2017-03-22 | 2020-02-05 | キオクシア株式会社 | 半導体装置の製造方法および半導体装置 |
US10535585B2 (en) | 2017-08-23 | 2020-01-14 | Semiconductor Components Industries, Llc | Integrated passive device and fabrication method using a last through-substrate via |
US11296031B2 (en) | 2018-03-30 | 2022-04-05 | Intel Corporation | Dielectric-filled trench isolation of vias |
KR102643624B1 (ko) | 2018-06-07 | 2024-03-05 | 삼성전자주식회사 | 이미지 센서 |
WO2021061481A1 (en) * | 2019-09-27 | 2021-04-01 | Corning Incorporated | Vias including circumferential trenches, interposer including the vias, and method for fabricating the vias |
JP7391741B2 (ja) * | 2020-03-23 | 2023-12-05 | 株式会社東芝 | 構造体 |
CN111883541A (zh) * | 2020-06-30 | 2020-11-03 | 复旦大学 | 一种用于三维封装的soi有源转接板及其制备方法 |
KR20220010852A (ko) | 2020-07-20 | 2022-01-27 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 제조 방법 |
CN113421869B (zh) * | 2021-06-18 | 2022-08-02 | 武汉新芯集成电路制造有限公司 | 半导体器件及其制造方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7276787B2 (en) | 2003-12-05 | 2007-10-02 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
JP2006278646A (ja) * | 2005-03-29 | 2006-10-12 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP4869664B2 (ja) * | 2005-08-26 | 2012-02-08 | 本田技研工業株式会社 | 半導体装置の製造方法 |
JP4389227B2 (ja) | 2006-09-28 | 2009-12-24 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
US7879711B2 (en) | 2006-11-28 | 2011-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stacked structures and methods of fabricating stacked structures |
US7645678B2 (en) * | 2007-02-13 | 2010-01-12 | United Microelectronics Corp. | Process of manufacturing a shallow trench isolation and process of treating bottom surface of the shallow trench for avoiding bubble defects |
KR100895813B1 (ko) | 2007-06-20 | 2009-05-06 | 주식회사 하이닉스반도체 | 반도체 패키지의 제조 방법 |
US7615480B2 (en) * | 2007-06-20 | 2009-11-10 | Lam Research Corporation | Methods of post-contact back end of the line through-hole via integration |
KR100945504B1 (ko) | 2007-06-26 | 2010-03-09 | 주식회사 하이닉스반도체 | 스택 패키지 및 그의 제조 방법 |
US7939941B2 (en) | 2007-06-27 | 2011-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of through via before contact processing |
JP5361156B2 (ja) * | 2007-08-06 | 2013-12-04 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
US7859114B2 (en) * | 2008-07-29 | 2010-12-28 | International Business Machines Corporation | IC chip and design structure with through wafer vias dishing correction |
KR20100040455A (ko) | 2008-10-10 | 2010-04-20 | 주식회사 동부하이텍 | 반도체 소자의 제조 방법 |
US8097953B2 (en) * | 2008-10-28 | 2012-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional integrated circuit stacking-joint interface structure |
JP4945545B2 (ja) * | 2008-11-10 | 2012-06-06 | 株式会社日立製作所 | 半導体装置の製造方法 |
US20100224965A1 (en) | 2009-03-09 | 2010-09-09 | Chien-Li Kuo | Through-silicon via structure and method for making the same |
US8492241B2 (en) * | 2010-10-14 | 2013-07-23 | International Business Machines Corporation | Method for simultaneously forming a through silicon via and a deep trench structure |
US8742535B2 (en) | 2010-12-16 | 2014-06-03 | Lsi Corporation | Integration of shallow trench isolation and through-substrate vias into integrated circuit designs |
US8987137B2 (en) | 2010-12-16 | 2015-03-24 | Lsi Corporation | Method of fabrication of through-substrate vias |
US20130119543A1 (en) | 2011-11-16 | 2013-05-16 | Globalfoundries Singapore Pte. Ltd. | Through silicon via for stacked wafer connections |
US20130299950A1 (en) | 2012-05-11 | 2013-11-14 | Sematech, Inc. | Semiconductor structure with buried through substrate vias |
-
2010
- 2010-12-16 US US12/969,852 patent/US8742535B2/en active Active
-
2011
- 2011-11-23 TW TW100142971A patent/TWI463584B/zh active
- 2011-12-12 EP EP11193092.1A patent/EP2466634B1/en active Active
- 2011-12-14 KR KR1020110134104A patent/KR101475108B1/ko active IP Right Grant
- 2011-12-15 JP JP2011273948A patent/JP5670306B2/ja active Active
- 2011-12-16 CN CN201110421747.0A patent/CN102543829B/zh active Active
-
2014
- 2014-04-11 US US14/251,258 patent/US9613847B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
EP2466634B1 (en) | 2019-06-19 |
KR20120067941A (ko) | 2012-06-26 |
CN102543829A (zh) | 2012-07-04 |
US20120153430A1 (en) | 2012-06-21 |
KR101475108B1 (ko) | 2014-12-22 |
JP2012129528A (ja) | 2012-07-05 |
EP2466634A1 (en) | 2012-06-20 |
US8742535B2 (en) | 2014-06-03 |
US20140220760A1 (en) | 2014-08-07 |
US9613847B2 (en) | 2017-04-04 |
TW201230221A (en) | 2012-07-16 |
TWI463584B (zh) | 2014-12-01 |
CN102543829B (zh) | 2015-01-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5670306B2 (ja) | 浅いトレンチ分離および基板貫通ビアの集積回路設計への統合 | |
US8987137B2 (en) | Method of fabrication of through-substrate vias | |
US20220208749A1 (en) | Semiconductor devices and methods of manufacture thereof | |
JP5682897B2 (ja) | 基板を含む半導体ウェハの一部分内にビアを形成するための方法および基板を含む半導体ウェハの一部分内に形成されるビア構造体 | |
US9691840B2 (en) | Cylindrical embedded capacitors | |
TWI497660B (zh) | 具有穿透基板互連之半導體構造,以及形成穿透基板互連之方法 | |
US9472504B2 (en) | Semiconductor having a high aspect ratio via | |
US8309402B2 (en) | Method of fabricating oxide material layer with openings attached to device layers | |
TWI447850B (zh) | 直通基材穿孔結構及其製造方法 | |
CN102468284A (zh) | 堆叠的半导体器件及其制造方法 | |
US8679937B2 (en) | Method for fabricating a capacitor and capacitor structure thereof | |
KR101459597B1 (ko) | 관통 실리콘 비아 제조방법 | |
TWI546866B (zh) | 半導體元件與製作方法 | |
TW201401507A (zh) | 半導體元件與其製作方法 | |
CN107644836A (zh) | 用于三维存储器的晶圆三维集成引线工艺及其结构 | |
TWI518861B (zh) | 矽穿孔結構及其製法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20120713 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130612 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130620 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130920 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130926 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131218 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140617 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20140717 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20140718 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141010 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20141020 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141118 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141217 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5670306 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |