JP4389227B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4389227B2 JP4389227B2 JP2006265270A JP2006265270A JP4389227B2 JP 4389227 B2 JP4389227 B2 JP 4389227B2 JP 2006265270 A JP2006265270 A JP 2006265270A JP 2006265270 A JP2006265270 A JP 2006265270A JP 4389227 B2 JP4389227 B2 JP 4389227B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- conductor
- semiconductor device
- forming
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 131
- 238000004519 manufacturing process Methods 0.000 title claims description 58
- 239000000758 substrate Substances 0.000 claims description 67
- 239000004020 conductor Substances 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 40
- 150000004767 nitrides Chemical class 0.000 claims description 37
- 230000001681 protective effect Effects 0.000 claims description 27
- 238000002955 isolation Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 description 10
- 230000007261 regionalization Effects 0.000 description 6
- 230000035515 penetration Effects 0.000 description 5
- 239000000356 contaminant Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
11 半導体基板
12 外周貫通電極
13 内部貫通電極
14、16、21、23、27、41、43 酸化膜
15、22、28、42 窒化膜
17、24、44 導電体
29、45 トレンチ
30、46 絶縁酸化膜
31、47 ゲート絶縁膜
32、48 ゲート電極
33、49 拡散層
34、50 層間絶縁膜
25、45’ 凹部
26 保護酸化膜
Claims (9)
- 貫通電極を備えた半導体装置の製造方法において、
半導体基板に貫通電極形成用のトレンチを形成するトレンチ形成工程と、
前記貫通電極形成用のトレンチ内部に複数の絶縁膜を成膜する絶縁膜成膜工程と、
前記貫通電極形成用のトレンチ内部を導電体で充填する導電体成膜工程と、
前記導電体をエッチングし、前記導電体の表面を前記半導体基板の表面より低くし凹部を形成するエッチング工程と、
前記導電体の表面に保護用絶縁膜を形成する保護絶縁膜形成工程と、
前記半導体基板の半導体デバイスが形成されるべき領域の表面を露出させる工程と、
前記露出された表面に半導体デバイスを形成する工程と、
前記半導体デバイスが形成された半導体基板表面に層間絶縁膜を形成する工程と、
前記導電体が前記半導体基板を貫通するように前記半導体基板を裏面から研削する工程と、を備えたことを特徴とする半導体装置の製造方法。 - 前記絶縁膜成膜工程において成膜される複数の絶縁膜は、フィールドパターン形成用の酸化膜と窒化膜とを少なくとも含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記エッチング工程において、前記導電体をエッチングするとともに、前記半導体基板に絶縁分離用のトレンチを形成することを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記導電体をエッチングして形成した凹部の底面位置と、前記絶縁分離用のトレンチの底面位置とは、同じ高さであることを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記保護絶縁膜形成工程において、前記保護絶縁膜を前記導電体の表面に形成するとともに、前記絶縁分離用のトレンチ内部を前記保護絶縁膜で充填することを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記導電体は不純物を含む多結晶シリコンであることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記半導体基板の表面を露出する工程のあとで、前記半導体基板の表面にフィールドパターン形成用の酸化膜と窒化膜を成膜する工程と、絶縁分離用のトレンチを形成し、絶縁分離用絶縁膜を成膜する絶縁分離工程とをさらに備えたことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記導電体をエッチングして形成した凹部の底面位置は、前記絶縁分離用のトレンチの底面位置より低いことを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記保護絶縁膜形成工程において、前記導電体の表面に形成された保護絶縁膜の表面の位置は、前記半導体基板の表面の位置より低いことを特徴とする請求項7に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006265270A JP4389227B2 (ja) | 2006-09-28 | 2006-09-28 | 半導体装置の製造方法 |
US11/857,286 US7897459B2 (en) | 2006-09-28 | 2007-09-18 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006265270A JP4389227B2 (ja) | 2006-09-28 | 2006-09-28 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008085173A JP2008085173A (ja) | 2008-04-10 |
JP4389227B2 true JP4389227B2 (ja) | 2009-12-24 |
Family
ID=39260312
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006265270A Active JP4389227B2 (ja) | 2006-09-28 | 2006-09-28 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7897459B2 (ja) |
JP (1) | JP4389227B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8525343B2 (en) | 2010-09-28 | 2013-09-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device with through-silicon via (TSV) and method of forming the same |
US8987137B2 (en) | 2010-12-16 | 2015-03-24 | Lsi Corporation | Method of fabrication of through-substrate vias |
US8742535B2 (en) | 2010-12-16 | 2014-06-03 | Lsi Corporation | Integration of shallow trench isolation and through-substrate vias into integrated circuit designs |
JP2012256785A (ja) * | 2011-06-10 | 2012-12-27 | Elpida Memory Inc | 半導体装置及びその製造方法 |
KR101895528B1 (ko) * | 2012-01-05 | 2018-09-05 | 삼성전자주식회사 | 반도체 메모리 소자 및 이의 제조 방법 |
KR101867961B1 (ko) | 2012-02-13 | 2018-06-15 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
US9287197B2 (en) * | 2013-03-15 | 2016-03-15 | Globalfoundries Singapore Pte. Ltd. | Through silicon vias |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9723468D0 (en) * | 1997-11-07 | 1998-01-07 | Zetex Plc | Method of semiconductor device fabrication |
JP2003332417A (ja) | 2002-05-08 | 2003-11-21 | Toshiba Corp | 半導体チップの製造方法 |
JP2004221350A (ja) | 2003-01-15 | 2004-08-05 | Seiko Epson Corp | 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
JP4069028B2 (ja) | 2003-07-16 | 2008-03-26 | 株式会社フジクラ | 貫通電極付き基板、その製造方法及び電子デバイス |
JP2005236271A (ja) | 2004-01-22 | 2005-09-02 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
JP2005243689A (ja) | 2004-02-24 | 2005-09-08 | Canon Inc | 半導体チップの製造方法および半導体装置 |
JP4568039B2 (ja) | 2004-06-30 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそれを用いた半導体モジュール |
JP2006019455A (ja) | 2004-06-30 | 2006-01-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2006114686A (ja) | 2004-10-14 | 2006-04-27 | Sony Corp | 半導体装置およびその製造方法 |
US7868394B2 (en) * | 2005-08-09 | 2011-01-11 | United Microelectronics Corp. | Metal-oxide-semiconductor transistor and method of manufacturing the same |
JP4828537B2 (ja) * | 2005-08-26 | 2011-11-30 | 株式会社日立製作所 | 半導体装置 |
-
2006
- 2006-09-28 JP JP2006265270A patent/JP4389227B2/ja active Active
-
2007
- 2007-09-18 US US11/857,286 patent/US7897459B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2008085173A (ja) | 2008-04-10 |
US7897459B2 (en) | 2011-03-01 |
US20080079112A1 (en) | 2008-04-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5563186B2 (ja) | 半導体装置及びその製造方法 | |
KR102501967B1 (ko) | 반도체 디바이스들의 형성 및 이송을 위한 재사용가능 지지 기판 및 이를 사용하는 방법들 | |
US8809162B2 (en) | Method for manufacturing a semiconductor device comprising a guard ring between a cell region and a peripheral region | |
JP4389227B2 (ja) | 半導体装置の製造方法 | |
JP2007165461A (ja) | 半導体装置及びその製造方法 | |
US8975173B2 (en) | Semiconductor device with buried gate and method for fabricating the same | |
CN112567514B (zh) | 存储器结构及其形成方法 | |
KR102695369B1 (ko) | 반도체 소자 | |
JP2007096321A (ja) | 化学機械的研磨を利用した自己整列コンタクトパッドの形成方法 | |
JP2009253249A (ja) | 半導体装置、その製造方法、及び、データ処理システム | |
JP4945545B2 (ja) | 半導体装置の製造方法 | |
JP5697952B2 (ja) | 半導体装置、半導体装置の製造方法およびデータ処理システム | |
TW202243162A (zh) | 積體電路晶片、積體電路封裝以及形成接墊結構的方法 | |
US11239204B2 (en) | Bonded assembly containing laterally bonded bonding pads and methods of forming the same | |
TW201005826A (en) | Semiconductor device, semiconductor chip, manufacturing methods thereof, and stack package | |
US20230309299A1 (en) | Memory device and method of fabricating the same | |
US12027463B2 (en) | Memory device and fabrication method thereof | |
KR101087786B1 (ko) | 반도체 소자 및 그의 형성 방법 | |
US8685852B2 (en) | Method of forming metal line of semiconductor device | |
TWI834203B (zh) | 包括含碳接觸柵的半導體裝置 | |
JP5924198B2 (ja) | 半導体装置の製造方法 | |
KR101040533B1 (ko) | 반도체 소자 및 그 제조방법 | |
US20120220115A1 (en) | Method for fabricating semiconductor device | |
TWI431720B (zh) | 溝填方法及淺溝渠隔離結構的製造方法 | |
KR101076813B1 (ko) | 반도체 소자 및 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090213 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090218 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090417 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090902 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090924 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121016 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4389227 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131016 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |