JP2008085173A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2008085173A JP2008085173A JP2006265270A JP2006265270A JP2008085173A JP 2008085173 A JP2008085173 A JP 2008085173A JP 2006265270 A JP2006265270 A JP 2006265270A JP 2006265270 A JP2006265270 A JP 2006265270A JP 2008085173 A JP2008085173 A JP 2008085173A
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 141
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 239000004020 conductor Substances 0.000 claims description 59
- 238000000034 method Methods 0.000 claims description 40
- 150000004767 nitrides Chemical class 0.000 claims description 37
- 230000001681 protective effect Effects 0.000 claims description 35
- 238000002955 isolation Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 description 10
- 230000007261 regionalization Effects 0.000 description 6
- 230000035515 penetration Effects 0.000 description 5
- 239000000356 contaminant Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】 最初に貫通電極を形成し、その後標準の製造方法により半導体デバイスを形成する。貫通電極の側面は、絶縁膜により半導体基板と絶縁され、表面は保護用の絶縁膜により覆われる。これらの絶縁膜で覆われることで、貫通電極の導電体は保護され、導電体からの汚染物飛散が防止できる。標準の製造条件を変更することなく適用できる。
【選択図】 図9
Description
11 半導体基板
12 外周貫通電極
13 内部貫通電極
14、16、21、23、27、41、43 酸化膜
15、22、28、42 窒化膜
17、24、44 導電体
29、45 トレンチ
30、46 絶縁酸化膜
31、47 ゲート絶縁膜
32、48 ゲート電極
33、49 拡散層
34、50 層間絶縁膜
25、45’ 凹部
26 保護酸化膜
Claims (14)
- 貫通電極を備えた半導体装置の製造方法において、半導体基板に貫通電極形成用のトレンチを形成するトレンチ形成工程と、前記貫通電極形成用のトレンチ内部に複数の絶縁膜を成膜する絶縁膜成膜工程と、前記貫通電極形成用のトレンチ内部を導電体で充填する導電体成膜工程と、前記導電体をエッチングし、前記導電体の表面を前記半導体基板の表面より低くし凹部を形成するエッチング工程と、前記導電体の表面に保護用絶縁膜を形成する保護絶縁膜形成工程とを備えたことを特徴とする半導体装置の製造方法。
- 前記絶縁膜成膜工程において成膜される複数の絶縁膜は、フィールドパターン形成用の酸化膜と窒化膜とを少なくとも含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記エッチング工程において、前記導電体をエッチングするとともに、前記半導体基板に絶縁分離用のトレンチを形成することを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記導電体をエッチングして形成した凹部の底面位置と、前記絶縁分離用のトレンチの底面位置とは、同じ高さであることを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記保護絶縁膜形成工程において、前記保護絶縁膜を前記導電体の表面に形成するとともに、前記絶縁分離用のトレンチ内部を前記保護絶縁膜で充填することを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記導電体は不純物を含む多結晶シリコンであることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記保護絶縁膜形成工程のあとで、前記半導体基板の表面の基板面を露出させ、フィールドパターン形成用の酸化膜と窒化膜を成膜する工程と、絶縁分離用のトレンチを形成し、絶縁分離用絶縁膜を成膜する絶縁分離工程とをさらに備えたことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記導電体をエッチングして形成した凹部の底面位置は、前記絶縁分離用のトレンチの底面位置より低いことを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記保護絶縁膜形成工程において、前記導電体の表面に形成された保護絶縁膜の表面の位置は、前記半導体基板の表面の位置より低いことを特徴とする請求項7に記載の半導体装置の製造方法。
- 請求項1乃至9のいずれかに記載の半導体装置の製造方法により製造されたことを特徴とする半導体装置。
- 半導体基板と、前記半導体基板を貫通する導電体と、前記導電体の側面に設けられ、前記半導体基板との間を絶縁する絶縁膜と、前記導電体の表面に設けられた保護絶縁膜とを備えたことを特徴とする半導体装置。
- 前記保護絶縁膜は、絶縁分離絶縁膜の形成時に同時に形成され、前記絶縁分離絶縁膜と同じ材質からなる絶縁膜であることを特徴とする請求項11に記載の半導体装置。
- 前記半導体基板との間を絶縁する絶縁膜の表面には、層間絶縁膜が形成されていることを特徴とする請求項12に記載の半導体装置。
- 前記保護絶縁膜の表面には、フィールドパターン形成用の絶縁膜と層間絶縁膜とが積層されていることを特徴とする請求項11に記載の半導体装置。
Priority Applications (2)
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---|---|---|---|
JP2006265270A JP4389227B2 (ja) | 2006-09-28 | 2006-09-28 | 半導体装置の製造方法 |
US11/857,286 US7897459B2 (en) | 2006-09-28 | 2007-09-18 | Semiconductor device and manufacturing method thereof |
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JP2006265270A JP4389227B2 (ja) | 2006-09-28 | 2006-09-28 | 半導体装置の製造方法 |
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JP2008085173A true JP2008085173A (ja) | 2008-04-10 |
JP4389227B2 JP4389227B2 (ja) | 2009-12-24 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20130080690A (ko) * | 2012-01-05 | 2013-07-15 | 삼성전자주식회사 | 반도체 메모리 소자 및 이의 제조 방법 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8525343B2 (en) | 2010-09-28 | 2013-09-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device with through-silicon via (TSV) and method of forming the same |
US8987137B2 (en) | 2010-12-16 | 2015-03-24 | Lsi Corporation | Method of fabrication of through-substrate vias |
US8742535B2 (en) * | 2010-12-16 | 2014-06-03 | Lsi Corporation | Integration of shallow trench isolation and through-substrate vias into integrated circuit designs |
JP2012256785A (ja) * | 2011-06-10 | 2012-12-27 | Elpida Memory Inc | 半導体装置及びその製造方法 |
KR101867961B1 (ko) | 2012-02-13 | 2018-06-15 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
US9287197B2 (en) * | 2013-03-15 | 2016-03-15 | Globalfoundries Singapore Pte. Ltd. | Through silicon vias |
Family Cites Families (11)
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GB9723468D0 (en) * | 1997-11-07 | 1998-01-07 | Zetex Plc | Method of semiconductor device fabrication |
JP2003332417A (ja) | 2002-05-08 | 2003-11-21 | Toshiba Corp | 半導体チップの製造方法 |
JP2004221350A (ja) | 2003-01-15 | 2004-08-05 | Seiko Epson Corp | 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
JP4069028B2 (ja) | 2003-07-16 | 2008-03-26 | 株式会社フジクラ | 貫通電極付き基板、その製造方法及び電子デバイス |
JP2005236271A (ja) | 2004-01-22 | 2005-09-02 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
JP2005243689A (ja) | 2004-02-24 | 2005-09-08 | Canon Inc | 半導体チップの製造方法および半導体装置 |
JP2006019455A (ja) | 2004-06-30 | 2006-01-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP4568039B2 (ja) | 2004-06-30 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそれを用いた半導体モジュール |
JP2006114686A (ja) | 2004-10-14 | 2006-04-27 | Sony Corp | 半導体装置およびその製造方法 |
US7868394B2 (en) * | 2005-08-09 | 2011-01-11 | United Microelectronics Corp. | Metal-oxide-semiconductor transistor and method of manufacturing the same |
US7948088B2 (en) * | 2005-08-26 | 2011-05-24 | Hitachi, Ltd. | Semiconductor device |
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2006
- 2006-09-28 JP JP2006265270A patent/JP4389227B2/ja active Active
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2007
- 2007-09-18 US US11/857,286 patent/US7897459B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20130080690A (ko) * | 2012-01-05 | 2013-07-15 | 삼성전자주식회사 | 반도체 메모리 소자 및 이의 제조 방법 |
KR101895528B1 (ko) | 2012-01-05 | 2018-09-05 | 삼성전자주식회사 | 반도체 메모리 소자 및 이의 제조 방법 |
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Publication number | Publication date |
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JP4389227B2 (ja) | 2009-12-24 |
US20080079112A1 (en) | 2008-04-03 |
US7897459B2 (en) | 2011-03-01 |
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