WO2019042248A1 - 存储器结构及其形成方法 - Google Patents

存储器结构及其形成方法 Download PDF

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Publication number
WO2019042248A1
WO2019042248A1 PCT/CN2018/102496 CN2018102496W WO2019042248A1 WO 2019042248 A1 WO2019042248 A1 WO 2019042248A1 CN 2018102496 W CN2018102496 W CN 2018102496W WO 2019042248 A1 WO2019042248 A1 WO 2019042248A1
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Prior art keywords
layer
substrate layer
substrate
memory
isolation
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PCT/CN2018/102496
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English (en)
French (fr)
Inventor
陈赫
董金文
朱继锋
华子群
肖亮
王永庆
Original Assignee
长江存储科技有限责任公司
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Priority claimed from CN201710775893.0A external-priority patent/CN107644838B/zh
Priority claimed from CN201710774763.5A external-priority patent/CN107644837B/zh
Priority claimed from PCT/CN2018/098612 external-priority patent/WO2020024282A1/zh
Application filed by 长江存储科技有限责任公司 filed Critical 长江存储科技有限责任公司
Publication of WO2019042248A1 publication Critical patent/WO2019042248A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a memory structure and a method of forming the same.
  • flash memory In recent years, the development of flash memory has been particularly rapid.
  • the main feature of flash memory is that it can store stored information for a long time without power supply, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc., so it can be used in many fields such as microcomputer and automation control. Has been widely used.
  • the three-dimensional flash memory (3D NAND) technology In order to further increase the bit density of the flash memory and reduce the bit cost, the three-dimensional flash memory (3D NAND) technology has been rapidly developed.
  • a 3D NAND flash memory structure including a memory array structure and a CMOS circuit structure located above the memory array structure
  • the memory array structure and the CMOS circuit structure are usually formed on two different wafers respectively, and then by bonding,
  • the CMOS circuit wafer is bonded to the storage column structure to connect the CMOS circuit and the memory array circuit; then the back side of the wafer on which the memory array structure is located is thinned, and the entire circuit is connected through the contact portion and the pad through the back surface.
  • the parasitic capacitance is generally reduced by increasing the thickness of the insulating layer between the pad and the wafer.
  • the thickness of the insulating layer is required to be greater than 1.4 ⁇ m to effectively reduce the insulating layer between the pad and the wafer.
  • the thickness of the insulating layer increases, which leads to an increase in the aspect ratio of the through-wafer via hole, and also requires strict control of the feature size and shape of the through-wafer via hole. Appearance, process deviation may lead to circuit open circuit or leakage, which greatly increases the difficulty of the process, requires a more advanced semiconductor processing machine, and increases the process cost.
  • the technical problem to be solved by the present invention is to provide a memory structure and a method for forming the same, which effectively reduces the parasitic capacitance of the memory structure and improves the memory performance.
  • the technical solution of the present invention provides a memory structure, comprising: a first substrate comprising: a substrate layer and a memory layer, the substrate layer having opposite first and second surfaces, the memory layer being located at the substrate layer On the first surface, the first substrate includes a pad region, and the first surface of the substrate layer is provided with a connection portion at least in part; an insulating layer is formed in the connection portion, and the insulating layer has a relative a top surface and a bottom surface, wherein the top surface is a side facing a first surface of the substrate layer, the bottom surface being a side facing a second surface of the substrate layer, and the storage layer includes a connection portion One end of the connecting portion is in contact with the insulating layer; a dielectric layer is located on the second surface of the substrate layer; a solder pad is located on a surface of the dielectric layer above the pad region; and an isolation structure extends through the lining a bottom layer, located at an edge of the pad region, surrounding a substrate layer in the pad region for isolating
  • the method further includes: a first contact portion penetrating the substrate layer of the dielectric layer and the pad region; the pad is connected to the first contact portion, the first contact portion It is electrically connected to the connecting portion.
  • the first contact portion includes a metal connection structure and an insulating sidewall spacer on a sidewall surface of the metal connection structure.
  • an opening is formed on the second surface of the substrate layer, the opening exposing at least a portion of the surface of the insulating layer; the dielectric layer covering at least a sidewall of the opening and an opening of the opening The surface of the insulating layer.
  • the first contact portion includes a first metal connection structure and a second metal connection structure, the first metal connection structure is electrically connected to the connection portion, and the second metal connection structure is located at the opening The first metal connection structure is electrically connected to the second metal connection structure.
  • the feature size of the isolation structure is smaller than a feature size of the first contact portion.
  • the isolation structure includes an isolation trench penetrating the substrate layer and an isolation material filling the isolation trench.
  • a minimum distance between the projection of the bonding pad on the substrate layer and the isolation structure is 0.5 ⁇ m.
  • the isolation structure comprises two or more isolation rings disposed in a nested manner.
  • the distance between adjacent isolation rings is 0.8 ⁇ m to 1.2 ⁇ m.
  • a bottom surface of the insulating layer is located inside the substrate layer, a top surface of the insulating layer is flush with a first surface of the substrate layer, and a top surface of the insulating layer is higher than a bottom surface of the substrate layer
  • the first surface, the bottom surface of the insulating layer is in horizontal contact with the first surface of the substrate layer, and the top surface of the insulating layer is higher than the first surface of the substrate layer.
  • the storage layer comprises a three-dimensional memory, the three-dimensional memory comprising a three-dimensional memory device layer and a first metal layer sequentially away from the first surface of the substrate layer, the connection portion being located in the three-dimensional memory device layer, the connection One end of the portion is in contact with the insulating layer, and the other end of the connecting portion is in contact with the first metal layer.
  • one end of the connecting portion is located in an inner portion of the insulating layer, or one end of the connecting portion is in contact with a top surface of the insulating layer, or one end of the connecting portion passes through the insulating layer and It is in contact with the bottom surface of the insulating layer.
  • the method further includes: a second substrate, wherein the second substrate is formed with a peripheral circuit; the second substrate is bonded to the surface of the storage layer, a storage unit is formed in the storage layer, and the storage is connected
  • the memory circuit structure of the cell, the peripheral circuit within the second substrate and the memory circuit structure within the memory layer form an electrical connection.
  • the technical solution of the present invention further provides a method for forming a memory structure, comprising: providing a first substrate, including a substrate layer, the substrate layer having opposite first and second surfaces, the storage layer Located on a first surface of the substrate layer, the first substrate includes a pad region, the first surface of the substrate layer is provided with a connection portion at least part of the region; and an insulating layer is formed in the connection portion region
  • the insulating layer has oppositely disposed top and bottom surfaces, wherein the top surface is a side facing the first surface of the substrate layer, and the bottom surface is a side facing the second surface of the substrate layer; Forming a memory layer on a first surface of the substrate layer including at least the insulating layer, the memory layer including a connection portion, one end of the connection portion being in contact with the insulating layer; and a second layer in the substrate layer Forming a dielectric layer on the surface; forming an isolation structure penetrating the substrate layer, the isolation structure being located at an edge of the pad region
  • the method further includes: forming a first contact portion of the substrate layer penetrating the dielectric layer and the pad region; the pad is connected to the first contact portion, the first contact portion and the connecting portion Electrical connection.
  • the forming method of the first contact portion and the isolation structure includes: etching the dielectric layer to the substrate layer, forming a first opening and a second opening in the dielectric layer, the second opening Corresponding to the position of the connecting portion; simultaneously etching the substrate layer along the first opening and the second opening to form isolation trenches and contact holes respectively penetrating the substrate layer, the contact holes and corresponding Connecting the connection portion; forming an insulating material layer filling the isolation trench, the first opening, and covering the contact hole and the inner surface of the second opening; removing the insulating material layer at the bottom of the contact hole; forming the filling The metal material layer of the contact hole and the second opening is contacted, and the dielectric layer is planarized as a stop layer, and a metal connection structure is formed in the contact hole.
  • the method further includes: performing a hole opening treatment on the second surface of the substrate layer to expose at least a portion of the surface of the insulating layer; forming the dielectric layer on the second surface of the substrate layer, the dielectric layer covering at least a sidewall of the opening and a surface of the insulating layer exposed in the opening.
  • the method for forming the first contact portion includes: etching the dielectric layer and the insulating layer, and forming a contact hole at a position corresponding to the connecting portion at a second surface of the substrate layer, the contact hole Communicating with a corresponding connecting portion; forming a first metal connecting structure in the contact hole, forming a second metal connecting structure in the opening, the first metal connecting structure being electrically connected to the second metal connecting structure And the first metal connection structure is electrically connected to the connection portion.
  • the feature size of the isolation structure is smaller than a feature size of the first contact portion.
  • the step of forming an isolation structure penetrating the substrate layer further comprises: forming an isolation trench penetrating the substrate layer, the isolation trench being located at an edge of the pad region surrounding the pad region; forming An insulating material filling the isolation trenches.
  • a minimum distance between the projection of the bonding pad on the substrate layer and the isolation structure is 0.5 ⁇ m.
  • the isolation structure comprises two or more isolation rings disposed in a nested manner.
  • the distance between adjacent isolation rings is 0.8 ⁇ m to 1.2 ⁇ m.
  • a bottom surface of the insulating layer is located inside the substrate layer, a top surface of the insulating layer is flush with a first surface of the substrate layer, and a top surface of the insulating layer is higher than a bottom surface of the substrate layer
  • the first surface, the bottom surface of the insulating layer is in horizontal contact with the first surface of the substrate layer, and the top surface of the insulating layer is higher than the first surface of the substrate layer.
  • the storage layer comprises a three-dimensional memory, the three-dimensional memory comprising a three-dimensional memory device layer and a first metal layer sequentially away from the first surface of the substrate layer, the connection portion being located in the three-dimensional memory device layer, the connection One end of the portion is in contact with the insulating layer, and the other end of the connecting portion is in contact with the first metal layer.
  • one end of the connecting portion is located in an inner portion of the insulating layer, or one end of the connecting portion is in contact with a top surface of the insulating layer, or one end of the contact portion passes through the insulating layer and It is in contact with the bottom surface of the insulating layer.
  • a second substrate is bonded on the surface of the storage layer; a storage unit and a storage circuit structure connecting the storage unit are formed in the storage layer, and a peripheral circuit and the storage layer in the second substrate Electrical connections are made between the memory circuit structures within.
  • the substrate structure of the memory structure of the present invention is formed with an isolation structure as a physical isolation structure between the substrate layer under the solder pad and the substrate layer of other regions, and the substrate layer under the solder pad is isolated from the periphery, and no current is formed. . Therefore, the parasitic capacitance between the pad and the substrate layer can be reduced, thereby improving the performance of the memory structure. Further, since the parasitic capacitance between the pad and the substrate layer is small, a dielectric layer of a lower thickness can be used, which saves process cost and reduces process difficulty.
  • An insulating layer is disposed between the substrate layer and the storage layer, and a connection portion for metal interconnection is disposed in contact with the dielectric layer, and a back surface lead can be realized through a thick device layer in forming the lead connection structure. Reduced production costs and improved product yield.
  • an isolation structure is formed in the substrate layer as a physical isolation structure between a substrate layer under the pad and a substrate layer of the device region, and the parasitic formation between the pad and the substrate layer is reduced. Capacitance, which can improve the performance of the memory structure. Further, the isolation structure may be formed simultaneously in the process of forming the first contact portion through the substrate layer without adding process steps.
  • FIG. 7 are schematic structural diagrams showing a process of forming a memory structure according to an embodiment of the present invention.
  • FIGS. 8 to 10 are top plan views of an isolation ring and a bonding pad in a memory structure according to an embodiment of the present invention.
  • FIG. 11 to FIG. 13 are schematic top views of an isolation ring and a bonding pad in a memory structure according to an embodiment of the present invention.
  • FIG. 14 to FIG. 18 are schematic top views of an isolation ring and a bonding pad in a memory structure according to an embodiment of the present invention.
  • FIG. 1 to FIG. 7 are structural diagrams showing a process of forming a memory structure according to an embodiment of the present invention.
  • a first substrate 100 including: a substrate layer 101 having a first surface 11 and a second surface 12, and a memory layer 102, the memory layer 102 being located at the substrate layer 101.
  • the first substrate 100 includes a pad region I; a dielectric layer 103 is formed on the second surface 12 of the substrate layer 101.
  • the first substrate 100 is in an inverted state, at which time, the first surface 11 of the substrate layer 101 is the lower surface of the substrate layer 101, and the second surface 12 is the upper surface of the substrate layer 101.
  • the storage layer 102 covers the first surface 11 of the substrate layer 101, and in the inverted state, the corresponding storage layer 102 is also located below the substrate layer 101.
  • the substrate layer 101 is a semiconductor material layer, and may be a single crystal silicon wafer, a semiconductor epitaxial layer including a single crystal silicon wafer and a wafer surface, or a silicon-on-insulator substrate.
  • the substrate layer 101 includes a single crystal silicon wafer and a single crystal silicon epitaxial layer on the surface of the single crystal silicon substrate, and the surface of the single crystal silicon epitaxial layer is a first surface 11 The other side surface of the single crystal silicon wafer is the second surface 12.
  • the memory layer 102 includes an insulating layer and a memory cell formed in the insulating layer and a memory circuit connected to the memory cell.
  • a 3D NAND memory cell is formed in the memory layer 102.
  • a second contact portion 121 is also formed in the storage layer 102.
  • the second contact portion 121 may be an interconnect structure for connecting the memory cells, or may be an interconnect structure for connecting the circuit layers of the substrate layer 101 and the second substrate 200. In Fig. 1, a portion of the second contact portion 121 in the memory layer 102 is shown for illustrative purposes only.
  • the pad region I of the first substrate 100 is used to form a circuit connection structure connecting the circuits of the layers and subsequently forming a pad for connecting the external circuit and the internal circuit on the pad region I. Therefore, the pad region I A functional region such as a doped well is not formed in the inner substrate layer 101, and a second contact portion 121 is formed in the memory layer 102 in the pad region I for passing through the subsequently formed through pad region I.
  • the first contact portion of the substrate layer 101 connects the circuitry within the memory layer 102.
  • the first substrate 100 further includes a device region II other than the pad region I.
  • the device region II of the first substrate 100 is used to form a semiconductor device, and the pad region I is usually located at the periphery of the device region II.
  • a doped well is formed in the substrate layer 101 in the device region II, and a memory cell is formed in the memory layer 102 in the device region II.
  • the A current is required to pass through the substrate layer 101 of the device region II.
  • the dielectric layer 103 may be formed on the second surface 12 of the substrate layer 101 by a deposition process.
  • the dielectric layer 103 serves as a passivation layer covering the second surface 12 of the substrate layer 101 for protecting the second surface 12 of the substrate layer 101.
  • the material of the dielectric layer 103 may be an insulating dielectric material such as TEOS, silicon nitride, silicon oxynitride, or silicon oxide.
  • the dielectric layer 103 may be a single layer structure or a multi-layer stacked structure.
  • the dielectric layer 103 may be formed by various deposition processes such as a chemical vapor deposition process, a spin coating process, an atomic layer deposition process, and the like.
  • the other side surface of the storage layer 102 opposite to the substrate layer 101 is also bonded to a second substrate 200.
  • a peripheral circuit is formed in the second substrate 200, the second substrate 200 is located on a surface of the storage layer 102, and a peripheral circuit in the second substrate 200 forms a circuit with a storage circuit in the storage layer 102. connection.
  • the second substrate 200 exposes a surface of the connection portion of the peripheral circuit toward the surface of the storage layer 102, and the surface of the storage layer 102 exposes the surface of the connection portion of the storage circuit, and the two are bonded to form Electrical connection.
  • the dielectric layer 103 is etched to the second surface 12 of the substrate layer 101, and a first opening 131 and a second opening 132 are formed in the dielectric layer 103.
  • the method for forming the first opening 131 and the second opening 132 includes: forming a photoresist layer on the surface of the dielectric layer 103, and performing exposure and development on the photoresist layer by using a photomask to form a pattern a photoresist layer; the dielectric layer 103 is etched by using the patterned photoresist layer as a mask layer to form the first opening 131 and the second opening 132.
  • the first opening 131 is used to define the position and size of a subsequent isolation structure to be formed, and the second opening 132 is used to define the position and size of the first contact portion through the substrate layer 101 to be subsequently formed.
  • the first opening 131 is in the shape of an annular groove; the second opening 132 is in the shape of a hole, and the cross section may be circular, rectangular or polygonal.
  • the second opening 132 is formed not only in the dielectric layer above the pad region I, but also in the dielectric layer above the device region II for subsequent simultaneous
  • a first contact portion connecting the memory layer 102 is simultaneously formed in the pad region I and the device region II.
  • the substrate layer 101 is simultaneously etched along the first opening 131 and the second opening 132 to form isolation trenches 113 and contact holes 114 penetrating the substrate layer 101, respectively.
  • a second contact portion 121 in the storage layer 102 is exposed at the bottom of the contact hole 114, and a first contact portion penetrating through the substrate layer 101 and a second portion in the storage layer 102 are subsequently formed in the contact hole 114.
  • the contact portions 121 are connected.
  • the isolation trench 113 is located at the edge of the pad region I and is disposed around the pad region I.
  • the isolation trench 113 is located at the interface between the pad region I and the device region II, and one side sidewall of the isolation trench 113 exposes the substrate layer in the pad region I. 101, the other side sidewall exposes the substrate layer 101 within the device region II.
  • the isolation trench 113 is completely located in the pad region I; in another embodiment, the isolation trench 113 may also be completely located in the device region II, near The pad area I.
  • not only the isolation trenches 113 are formed at the edges of the pad region I, but also the isolation trenches may be formed between the contact holes 114 inside the pad region I.
  • the feature size of the isolation trench 113 is smaller than the feature size of the contact hole 114.
  • the feature size of the isolation trench 113 is the width of the isolation trench 113
  • the cross section of the contact hole 114 is circular
  • the feature size of the contact hole 114 is the cross section of the contact hole 114. diameter.
  • the width of the isolation trench 113 is less than half of the aperture width of the contact hole 114, greater than 20 nm, and the contact hole 114 has a maximum aperture width of 1500 nm.
  • an insulating material layer 400 is formed to fill the isolation trench 113 (please refer to FIG. 3), the first opening 131 (refer to FIG. 3), and the inner wall surface covering the contact hole 114 and the second opening 132. .
  • the material of the insulating material layer 400 may be an insulating dielectric material such as silicon oxide, silicon oxynitride or silicon nitride.
  • the insulating material layer 400 may be formed using a chemical vapor deposition process, an atomic layer deposition process, a plasma enhanced chemical vapor deposition process, or the like. Since the feature size of the isolation trench 113 is smaller than the feature size of the contact hole 114, when the insulating material layer 400 fills the isolation trench 113 and the first opening 131, the insulating material layer 400 covers only The inner wall surface of the contact hole 114 and the second opening 132.
  • the insulating material layer 400 also covers the surface of the dielectric layer 103.
  • the insulating material layer 400 at the bottom of the contact hole 114 is removed to form an insulating spacer 402 covering the sidewalls of the contact hole 114 and the second opening 132, and is filled in the isolation trench 113 and the first
  • the insulating material layer in the opening 131 serves as the isolation structure 401.
  • the insulating material layer 400 at the bottom of the contact hole 114 is removed by an anisotropic etching process.
  • the insulating material layer 400 on the surface of the dielectric layer 103 is also removed while removing the insulating material layer 400 at the bottom of the contact hole 114.
  • a portion of the thickness of the insulating material layer 400 remains on the surface of the dielectric layer 103.
  • the isolation structure 401 surrounds the substrate layer 101 of the pad region I, and physically separates between the substrate layer 101 in the pad region I and the substrate layer 101 on the periphery of the isolation structure 401.
  • the dielectric layer 103 can be kept at a lower thickness without increasing the thickness of the dielectric layer 103 to reduce the parasitic capacitance.
  • the dielectric layer 103 has a thickness greater than 100 nm, and may be, for example, 100 nm to 500 nm. In a specific embodiment, the dielectric layer 103 has a thickness of 400 nm.
  • the isolation structure 401 is formed synchronously without adding additional process steps.
  • a metal material layer filling the contact hole 114 and the second opening 132 is formed, and the dielectric layer 103 is planarized as a stop layer, and is formed in the contact hole 114 (please refer to FIG. 5 ).
  • a metal post 403 in the second opening 132 please refer to FIG. 5).
  • the insulating spacer 402 and the metal post 403 constitute a first contact portion.
  • the material of the metal material layer may be a metal material such as W, Cu, Al, or Au.
  • the metal material layer may be formed using a physical vapor deposition process, such as a sputtering process.
  • a pad 701 and a protective layer 703 covering the dielectric layer 103 and the pad 701 are formed on the surface of the dielectric layer 103 on the pad region I, and the protective layer 703 has an opening to expose the solder. Pad 701 surface.
  • an interconnect line 702 is also formed on the surface of the dielectric layer 103 on the device region II, the interconnect 702 connecting the metal pillars 403 in the device region II.
  • the minimum distance between the projection of the pad 701 on the substrate layer 101 and the isolation structure 401 is 0.5 ⁇ m, so that the pad 701 and the isolation structure 401 both have sufficient process windows to ensure that they are located on the pad 701.
  • the underlying substrate layer 101 is surrounded by the isolation structure 401.
  • the pad 701 is generally rectangular, and has a side length of 70 ⁇ m to 80 ⁇ m. The area is large and it is easy to cause a large parasitic capacitance.
  • the isolation of the isolation structure 401 causes no current to pass through the substrate layer 101 under the bonding pad 701, thereby reducing parasitic capacitance between the bonding pad 701 and the substrate layer 101.
  • the interconnection line 702 is formed simultaneously with the pad 701. Specifically, a metal layer covering the dielectric layer 103 and the first contact portion is formed, and the metal layer is patterned and etched to form a pad 701 and an interconnection. Line 702, and then forming a protective layer 703 covering the dielectric layer 103, the interconnect 702 and the pad 701, and etching the protective layer 703 to expose the surface of the pad 701 for subsequent solder pads The 701 is connected to an external circuit.
  • the material of the interconnect 702 and the pad 701 may be a metal such as Al, Cu, Au or Ag.
  • the size of the interconnect 702 is small.
  • the interconnect 702 has a width of 600 nm, does not generate a large parasitic capacitance, and has little influence on the performance of the memory.
  • the width of the interconnect 702 may also be from 500 nm to 700 nm.
  • the isolation structure 401 is formed in the substrate layer 101 as a physical isolation structure between the substrate layer 101 under the pad 701 and the substrate layer 102 of the device region II, and the lining under the pad 701 Current is formed inside the underlayer 101, and therefore, the parasitic capacitance between the pad 701 and the substrate layer 101 is lowered, thereby improving the performance of the memory structure. Therefore, the lower thickness of the dielectric layer 103 can also keep the parasitic capacitance between the pad 701 and the substrate layer 101 small.
  • the dielectric layer 103 may have a thickness of 400 nm. In other embodiments, the dielectric layer 103 may have a thickness of 300 nm to 500 nm. The thickness of the dielectric layer 103 is relatively low, so that the depths of the contact holes 114 and the isolation trenches 113 are relatively low, which can reduce the process difficulty.
  • the substrate layer 101 may be etched to form an isolation trench, and the isolation trench is filled with a spacer material as an isolation structure;
  • a dielectric layer 103 is formed on the second surface 12 of the substrate layer 101, and the dielectric layer 103 and the substrate layer 101 are etched to form a contact hole penetrating the dielectric layer 103 and the substrate layer 101, and formed on the inner wall surface of the contact hole.
  • An insulating sidewall 402 and a metal post 403 filled with the contact hole.
  • the isolation structure 401 is a single isolation ring.
  • FIG. 8 is a schematic top view of the isolation structure 401 and the bonding pad 701 .
  • the pad 701 is a rectangle, and the shape of the surrounding portion of the isolation structure 401 is the same as the shape of the pad 701. The distance between the isolation structure 401 and the pad 701 is equal. In other embodiments, the isolation structure 401 may also have other shapes such as a circular shape.
  • the isolation structure may include two or more isolation rings disposed in a nested manner.
  • the two isolation rings of the isolation structure are an isolation ring 401a and an isolation ring 401b, and the isolation ring 401a and the isolation ring 401b are nested.
  • the distance between the isolation ring 401a and the isolation ring 401b is equal everywhere, so that the isolation effect is uniform everywhere.
  • the spacer ring 401a may be located in the pad region I, the isolation ring 401b is located in the device region II; or the isolation ring 401a and the isolation ring 401b are located in the device region II or both Said in the pad area I.
  • the isolation effect can be improved by isolating the substrate layer 101 in the area surrounded by the two isolation rings.
  • the spacing between the spacer ring 401a and the spacer ring 401b may be 0.8 ⁇ m to 1.2 ⁇ m. In other embodiments, the spacing between the isolation ring 401a and the isolation ring 401b may also vary from position to location.
  • the isolation structure includes three isolation rings, which are an isolation ring 401a, an isolation ring 401b, and an isolation ring 401c.
  • the spacer ring 401a and the spacer ring 401b have a spacing d1
  • the spacer ring 401b and the spacer ring 401c have a spacing d2.
  • d1 d2; in other embodiments, d1 and d2 may also be used. not equal.
  • the isolation structure having a plurality of isolation rings can further improve the isolation effect and minimize the parasitic capacitance between the pad 701 and the substrate layer 101.
  • a specific embodiment of the present invention also provides a memory structure formed by the above method.
  • FIG. 7 is a schematic structural diagram of a storage structure according to an embodiment of the present invention.
  • the memory structure includes a first substrate 100 including a substrate layer 101 and a memory layer 102 having opposing first and second surfaces 11 and 12, the memory layer 102 Located on the first surface 11 of the substrate layer 101, the first substrate 100 includes a pad region I; a dielectric layer 103 on the second surface 12 of the substrate layer 101; and a pad 701 located at the soldering a surface of the dielectric layer 103 on the pad region I; an isolation structure 401 penetrating the substrate layer 101 and located at an edge of the pad region I, surrounding the substrate layer 101 in the pad region I for isolating the solder The substrate layer 101 in the pad region I and the substrate layer 101 on the periphery of the isolation structure 401.
  • the substrate layer 101 is a semiconductor material layer, and may be a single crystal silicon wafer, a semiconductor epitaxial layer including a single crystal silicon wafer and a wafer surface, or a silicon-on-insulator substrate.
  • the substrate layer 101 includes a single crystal silicon wafer and a single crystal silicon epitaxial layer on the surface of the single crystal silicon substrate, and the surface of the single crystal silicon epitaxial layer is a first surface 11 The other side surface of the single crystal silicon wafer is the second surface 12.
  • the first substrate 100 is in an inverted state, at which time, the first surface 11 of the substrate layer 101 is the lower surface of the substrate layer 101, and the second surface 12 is the upper surface of the substrate layer 101.
  • the storage layer 102 covers the first surface 11 of the substrate layer 101, and in the inverted state, the corresponding storage layer 102 is also located below the substrate layer 101.
  • the memory layer 102 includes an insulating layer and a memory cell formed in the insulating layer and a memory circuit connected to the memory cell.
  • a 3D NAND memory cell is formed in the memory layer 102.
  • a second contact portion 121 is also formed in the storage layer 102.
  • the second contact portion 121 may be an interconnect structure for connecting the memory cells, or may be an interconnect structure for connecting the circuit layers of the substrate layer 101 and the second substrate 200.
  • the other side surface of the storage layer 102 opposite to the substrate layer 101 is further connected to a second substrate 200, and a peripheral circuit is formed in the second substrate 200;
  • the substrate 200 is located on the surface of the memory layer 102, and a peripheral circuit within the second substrate 200 forms an electrical connection with a memory circuit within the memory layer 102.
  • the second substrate 200 exposes a surface of the connection portion of the peripheral circuit toward the surface of the storage layer 102, and the surface of the storage layer 102 exposes the surface of the connection portion of the storage circuit, and the two are bonded to form Electrical connection.
  • the first substrate 100 further includes a device region II for forming a semiconductor device, and the pad region I is generally located at the periphery of the device region II.
  • a doped well is formed in the substrate layer 101 in the device region II, and a memory cell is formed in the memory layer 102 in the device region II.
  • the A current is required to pass through the substrate layer 101 of the device region II.
  • the pad region I of the first substrate 100 is used to form a circuit connection structure connecting the circuits of the layers and subsequently forming a pad for connecting the external circuit and the internal circuit on the pad region I.
  • the pad region I A functional region such as a doped well is not formed in the inner substrate layer 101, and a second contact portion 121 is formed in the memory layer 102 in the pad region I for passing through the subsequently formed through pad region I.
  • the first contact portion of the substrate layer 101 connects the circuitry within the memory layer 102.
  • a portion of the second contact portion 121 in the memory layer 102 is shown for illustrative purposes only.
  • the dielectric layer 103 acts as a passivation layer on the second surface 12 of the substrate layer 101 for protecting the second surface 12 of the substrate layer 101.
  • the material of the dielectric layer 103 may be an insulating dielectric material such as TEOS, silicon nitride, silicon oxynitride, or silicon oxide.
  • the dielectric layer 103 may be a single layer structure or a multi-layer stacked structure.
  • the dielectric layer 103 may be formed by various deposition processes such as a chemical vapor deposition process, a spin coating process, an atomic layer deposition process, and the like.
  • the dielectric layer 103 has a thickness greater than 100 nm, and may be, for example, 100 nm to 500 nm. In a specific embodiment, the dielectric layer 103 has a thickness of 400 nm.
  • the isolation structure 401 includes an isolation trench penetrating the substrate layer 101 and an isolation material filling the isolation trench.
  • the insulating material may be an insulating dielectric material such as silicon oxide, silicon oxynitride or silicon nitride.
  • the isolation structure 401 also penetrates the dielectric layer 103.
  • the isolation structure 401 may also be located only within the substrate layer 101.
  • the isolation structure 401 is located at the edge of the pad region I and is disposed around the pad region I. In this embodiment, the isolation structure 401 is located at the interface between the pad region I and the device region II, and one side wall of the isolation structure 401 is in contact with the substrate layer 101 in the pad region I. The other side wall is in contact with the substrate layer 101 in the device region II. In another embodiment, the isolation structure 401 is completely located in the pad region I; in another specific embodiment, the isolation structure 401 may also be completely located in the device region II, adjacent to the Pad area I. In another embodiment, the isolation structure 401 is formed not only at the edge of the pad region I, but also between the metal posts 403 of the first contact portion inside the pad region I.
  • the isolation structure 401 surrounds the substrate layer 101 of the pad region I, and physically separates between the substrate layer 101 in the pad region I and the substrate layer 101 on the periphery of the isolation structure 401.
  • the substrate layer 101 of the device region II has a current, and due to the isolation of the isolation structure 401, no current flows through the substrate layer 101 of the pad region I, thereby reducing the substrate layer.
  • the parasitic capacitance formed between the 101 and the pad 701 above the pad region I does not need to reduce the parasitic capacitance by increasing the thickness of the dielectric layer 103.
  • the minimum distance between the projection of the pad 701 on the substrate layer 101 and the isolation structure 401 is 0.5 ⁇ m, so that the pad 701 and the isolation structure 401 both have sufficient process windows to ensure that they are located on the pad 701.
  • the underlying substrate layer 101 is surrounded by the isolation structure 401.
  • the pad 701 is generally rectangular, and has a side length of between 70 ⁇ m and 80 ⁇ m. The area is large and is likely to cause a large parasitic capacitance. In the specific embodiment of the present invention, the pad 701 is insulated by the isolation structure 401.
  • the underlying substrate layer 101 has no current flowing, thereby reducing the parasitic capacitance formed between the pad 701 and the substrate layer 101.
  • the memory structure further includes a first contact portion penetrating the dielectric layer 103 and the substrate layer 101, the first contact portion including a metal pillar 403 and an insulating sidewall spacer 402 on a sidewall surface of the metal pillar 403.
  • the material of the metal pillar 403 may be a metal material such as W, Cu, Al, or Au.
  • the metal post 403 is connected to the second contact portion 121 to achieve connection with a memory circuit in the storage layer 102.
  • the first contact portion is formed in both the device region II and the pad region I.
  • the feature size of the isolation structure 401 is smaller than the feature size of the first contact portion.
  • the feature size of the isolation structure 401 is the width of the isolation structure 401
  • the cross section of the first contact portion is circular
  • the feature size of the first contact portion is the horizontal of the first contact portion. Section diameter.
  • the width of the isolation structure 401 is less than half of the cross-sectional diameter of the first contact portion, greater than 20 nm, and the maximum diameter of the cross section of the first contact portion is 1500 nm.
  • the isolation structure 401 and the first contact portion both penetrate the dielectric layer 103 and the substrate layer 101, the isolation trench and the contact hole are simultaneously formed by etching the dielectric layer 103 and the substrate layer 101, and then forming the Simultaneously with insulating the spacers 402, an isolation structure 401 filling the isolation trenches is formed without adding additional process steps.
  • the surface of the dielectric layer 103 on the device region II is also formed with interconnect lines 702 that are connected to the first contacts within the device region II.
  • the material of the interconnect 702 and the pad 701 may be a metal such as Al, Cu, Au or Ag.
  • the feature size of the interconnect 702 is small.
  • the interconnect 702 has a width of 600 nm, which does not cause a large parasitic capacitance, and has little influence on the performance of the memory. In other embodiments, the width of the interconnect 702 may also be from 500 nm to 700 nm.
  • the surface of the dielectric layer 103 further has a protective layer 703 covering the dielectric layer 103, the interconnect 702, and the pad 701.
  • the protective layer 703 has an opening to expose the surface of the pad 701 for subsequent solder pads.
  • the 701 is connected to an external circuit.
  • the isolation structure 401 is formed in the substrate layer 101 as a physical isolation structure between the substrate layer 101 under the pad 701 and the substrate layer 101 of the device region II, and the substrate layer under the pad 701 101 is isolated from the surroundings and no current is formed. Therefore, the parasitic capacitance between the pad 701 and the substrate layer 101 is reduced, thereby improving the performance of the memory structure. Further, since the parasitic capacitance between the pad 701 and the substrate layer 101 is reduced by the isolation structure 401, a dielectric layer 103 of a lower thickness and thus a first contact through the dielectric layer 103 and the substrate layer 101 may be employed. The depth and width of the portion and the isolation structure 401 are relatively low, which can reduce the process difficulty.
  • the isolation structure 401 is a single isolation ring.
  • FIG. 8 is a schematic top view of the isolation structure 401 and the bonding pad 701 .
  • the pad 701 is a rectangle, and the shape of the surrounding portion of the isolation structure 401 is the same as the shape of the pad 701. The distance between the isolation structure 401 and the pad 701 is equal. In other embodiments, the isolation structure 401 may also have other shapes such as a circular shape.
  • the isolation structure may include two or more isolation rings disposed in a nested manner.
  • the two isolation rings of the isolation structure are an isolation ring 401a and an isolation ring 401b, and the isolation ring 401a and the isolation ring 401b are nested.
  • the distance between the isolation ring 401a and the isolation ring 401b is equal everywhere, so that the isolation effect is uniform everywhere.
  • the spacer ring 401a may be located in the pad region I, the isolation ring 401b is located in the device region II; or the isolation ring 401a and the isolation ring 401b are located in the device region II or both Said in the pad area I.
  • the isolation effect can be improved by isolating the substrate layer 101 in the area surrounded by the two isolation rings.
  • the spacing between the spacer ring 401a and the spacer ring 401b may be 0.8 ⁇ m to 1.2 ⁇ m. In other embodiments, the spacing between the isolation ring 401a and the isolation ring 401b may also vary from position to position.
  • the substrate layer 101 may be etched while forming two nested annular isolation trenches, and the annular isolation trench is filled with an insulating material to form the isolation. Ring 401a and isolation ring 401b.
  • the isolation structure includes three isolation rings, which are an isolation ring 401a, an isolation ring 401b, and an isolation ring 401c.
  • the spacer ring 401a and the spacer ring 401b have a spacing d1
  • the spacer ring 401b and the spacer ring 401c have a spacing d2.
  • d1 d2; in other embodiments, d1 and d2 may also be used. not equal.
  • the isolation structure having a plurality of isolation rings can further improve the isolation effect and minimize the parasitic capacitance between the pad 701 and the substrate layer 101.
  • FIG. 11 to FIG. 13 are structural diagrams showing a process of forming a memory structure according to an embodiment of the present invention.
  • a first substrate including a substrate layer 11, the substrate layer 11 having opposite first and second surfaces; the first surface of the substrate layer 11 is provided with a connection region at least in part 12; forming an insulating layer 13 in the connecting portion region 12, the insulating layer 13 is an oxide insulating layer 13 or a nitride insulating layer 13, and the process of forming the insulating layer 13 in the connecting portion region 12 includes lithography and engraving One or a combination of etching, deposition, filling and grinding, the insulating layer 13 having oppositely disposed top and bottom surfaces, wherein the top surface is a side facing the first surface of the substrate layer, the bottom surface being facing the substrate layer One side of the second surface.
  • Fig. 8 only the pad region of the substrate layer 11 is shown.
  • the step of forming the insulating layer 13 first, a shallow trench is formed in the connection portion region 12 of the first surface of the substrate layer 11 by a lithography and etching process, and then deposition and The filling process forms the insulating layer 13 in the shallow trench, and the insulating layer 13 may be subsequently polished by a polishing process to planarize it.
  • the bottom surface of the insulating layer 13 is formed inside the substrate layer 11, and the top surface of the insulating layer 13 is flush with the first surface of the substrate layer 11.
  • the insulating layer 13 has a thickness of about 1 micron.
  • the specific process step of forming the insulating layer is: first, forming a hard mask layer on the first surface of the substrate layer, sequentially etching the hard mask layer and the substrate layer to form a trench, and the hard mask layer is, for example, A silicon nitride layer formed by a chemical vapor deposition process or a silicon oxide layer formed by a High Density Plasma Chemical Vapor Deposition (HDPCVD) process.
  • the hard mask layer and the substrate layer are etched to form trenches using any of the prior art techniques well known to those skilled in the art.
  • an insulating layer is deposited in the trench and on the hard mask layer, the insulating layer filling the trench; the insulating layer material such as silicon oxide, silicon nitride, silicon oxynitride, etc., is filled with the dielectric material
  • the process is, for example, a High Density Plasma Chemical Vapor Deposition (HDPCVD) method.
  • the insulating layer on the hard mask layer is removed; the process of removing the insulating layer on the hard mask layer is performed, for example, by a chemical mechanical polishing (CMP) method, after the CMP, the surface of the hard mask layer is deposited. The insulating layer is completely removed, so that the upper surface of the hard mask layer is completely exposed.
  • CMP chemical mechanical polishing
  • the rapid thermal oxidation treatment is performed, and the ambient temperature of rapid thermal oxidation is 400-800 degrees Celsius.
  • This step can eliminate the damage of the atomic structure caused by the corners of the groove in the foregoing process, and avoid the ditch in the subsequent process. Slot corner damage.
  • the trench is at an ambient temperature of 500-700 degrees Celsius.
  • the ambient temperature at which the trench is placed is linearly heated to between 400 and 800 degrees Celsius in 60 seconds to 140 seconds.
  • the ambient temperature of the trench can be, for example, 450 degrees Celsius, 480 degrees Celsius, 550 degrees Celsius, 600 degrees Celsius, 660 degrees Celsius, 640 degrees Celsius, 750 degrees Celsius, and the like.
  • the time for linear heating of the ambient temperature is, for example, 70 seconds, 75 seconds, 80 seconds, 95 seconds, 103 seconds, 115 seconds, 125 seconds, 130 seconds.
  • the method further includes the step of introducing an oxygen-containing gas into the environment in which the trench is located, wherein the oxygen-containing gas, such as oxygen (O 2 ), ozone (O 3 ), etc., has an oxidizing ability. gas.
  • oxygen-containing gas such as oxygen (O 2 ), ozone (O 3 ), etc.
  • the insulating layer in the trench is in a high temperature oxygen environment, the oxygen molecule concentration in the high temperature environment is large and the molecular activity is high, and the edge of the insulating layer in the trench is The original molecular structure is relatively loose, so the free silicon ions generated in the CMP process will be fully oxidized in this process, and the oxides formed after oxidation and the original oxide molecules in the insulating layer in the trench are at a high temperature.
  • the hard mask layer is removed.
  • the process of removing the hard mask layer is, for example, wet etching (Wet Etch), and the chemical etching reagent used varies depending on the material of the hard mask layer, and is a technique known to those skilled in the art.
  • the insulating layer 13 has oppositely disposed bottom surfaces and a top surface that is away from the first metal layer 18 with respect to the top surface.
  • a shallow trench is formed in the contact hole region 12 of the first surface of the substrate layer 11 by a lithography and etching process, and a shallow trench is formed by a deposition and filling process.
  • the insulating layer 13 is formed in the middle, and the insulating layer 13 may be subsequently polished by a polishing process to be planarized.
  • the bottom surface of the insulating layer 13 is formed inside the substrate layer 11, and the top surface of the insulating layer 13 is higher than the first surface of the substrate layer 11.
  • the insulating layer 13 has a thickness of about 1 micron.
  • the insulating layer 13 has oppositely disposed bottom surfaces and a top surface that is away from the first metal layer 18 with respect to the top surface.
  • the insulating layer 13 is formed on the surface of the contact hole region 12 of the first surface of the substrate layer 11 by a deposition process, and the insulating layer 13 may be further polished by a grinding process. Flatten it.
  • the bottom surface of the insulating layer 13 is formed in horizontal contact with the first surface of the substrate layer 11, and the top surface of the insulating layer 13 is higher than the first surface of the substrate layer 11.
  • the insulating layer 13 has a thickness of about 1 micron.
  • a storage layer 14 is formed on a region of the first surface of the substrate layer 11 including at least the insulating layer 13.
  • the storage layer 14 includes a connecting portion 15 having one end in contact with the insulating layer 13, and the connecting portion 15 is connected.
  • a metal material filled in the hole the metal material being one of copper, aluminum, tin or tungsten or any combination thereof;
  • the memory layer 14 comprising a three-dimensional memory comprising a three-dimensional memory device sequentially spaced away from the first surface of the substrate layer 11 a layer 141 and a first metal layer 18, the connecting portion 15 is located in the three-dimensional memory device layer 141, one end of the connecting portion 15 is in contact with the insulating layer 13, and the other end of the connecting portion 15 is in contact with the first metal layer 18. .
  • One end of the connecting portion 15 is located in the interior of the insulating layer 13. Alternatively, one end of the connecting portion 15 is in contact with the top surface of the insulating layer 13, or one end of the connecting portion 15 is passed through the insulating layer 13 and is in contact with the bottom surface of the insulating layer 13.
  • the side of the memory layer 14 of the substrate layer 11 including the memory layer 14 is bonded to the second substrate 16, and the second surface of the substrate layer 11 is thinned; the second surface of the substrate layer after thinning
  • An upper dielectric layer 19 is deposited, which is made of an oxide or a nitride or an oxynitride.
  • the dielectric layer 19 and the substrate layer 11 are etched, a contact hole 21 is formed at a position corresponding to the connection portion 15 at a first surface of the substrate layer 11, and a periphery is formed at an edge of the pad region of the substrate layer 11.
  • the pad region is provided with an isolation trench; and the isolation trench is filled with an insulating material to form the isolation structure 191, and an insulating spacer 23 is formed on the sidewall surface of the contact hole 21.
  • the contact hole 21 is in communication with the corresponding connecting portion 15.
  • the isolation structure 191 is disposed around the contact hole 21 in the pad region.
  • the method for forming the contact hole 21 and the isolation structure 191 includes: etching the dielectric layer 19 to the substrate layer 11, and forming a first opening and a second opening in the dielectric layer 19, Two openings corresponding to the position of the connecting portion 15; the substrate layer 11 is simultaneously etched along the first opening and the second opening, respectively forming isolation trenches and contact holes 21 penetrating the substrate layer, a contact hole 21 communicating with the corresponding connecting portion 15; forming a layer of insulating material filling the isolation trench, the first opening, and covering the contact hole 21 and the inner surface of the second opening; removing the bottom of the contact hole
  • the layer of insulating material forms an insulating spacer 23 .
  • a metal material layer filling the contact hole 21 and the second opening is formed, and the metal material layer is planarized with the dielectric layer 19 as a stop layer, and formed in the contact hole 21 a metal connection structure 22; a lead metal layer is deposited on the second surface of the substrate layer 11, and the lead structure 17 is defined by photolithography of the lead metal layer, the lead structure 17 and the metal connection structure 22 in the contact hole 21 Electrically connected, the material of the lead metal layer is one of copper, silver, aluminum, tin or tungsten or any combination thereof.
  • a second protective layer is deposited on the second surface of the substrate layer 11, and the second protective layer is formed into the second protective layer structure 20 by a lithography and etching process.
  • the material of the second protective layer is an oxide or a nitride or an oxynitride.
  • the lead structure 17 is a pad that is used as a subsequent connection to an external circuit.
  • FIG. 14 to FIG. 18 are structural diagrams showing a process of forming a memory structure according to another embodiment of the present invention.
  • FIG. 14 to FIG. 18 are structural diagrams showing a process of forming a memory structure according to another embodiment of the present invention.
  • portions that are different from the above embodiments will be described, and the same portions will not be described again.
  • FIG. 14 shows only the pad region of the substrate layer 11.
  • a dielectric layer 19 is formed on the second surface of the substrate layer 11, covering at least a sidewall of the opening and a surface of the insulating layer 13 exposed in the opening.
  • the dielectric layer 19 is made of oxide or nitrogen.
  • the etched dielectric layer 19 and the insulating layer 13 form a contact hole 21 at a position corresponding to the connecting portion 15 at a second surface of the substrate layer 11.
  • the process of forming the contact hole 21 includes lithography and etching.
  • the contact hole 21 is in communication with the corresponding connection portion 15. While the contact hole 21 is formed, the dielectric layer 19 and the substrate layer 11 are etched, an isolation trench is formed around the pad region, and an insulating material is filled in the isolation trench to form an isolation structure 191.
  • the isolation structure is disposed around the contact hole 21 in the pad region.
  • a first metal connection structure 2101 is formed in the through hole 21 , and a second metal connection structure 2102 is formed in the opening, and the first metal connection structure 2101 is electrically connected to the second metal connection structure 2102.
  • the first metal connection structure 2101 is electrically connected to the connection portion 15, the first metal connection structure is formed in the through hole, and the process of forming the second metal connection structure in the opening includes metal filling and chemical mechanical polishing;
  • the material of the first metal connection structure 2101 and the second metal connection structure 2102 is one of copper, aluminum, tin or tungsten or any combination thereof.
  • a lead metal layer is deposited on the second surface of the substrate layer 11, and the lead structure 24 is defined by the lithography and etching process for the lead metal layer.
  • the lead structure 24 and the second metal connection structure 2102 Electrically connecting, the material of the lead metal layer is one of copper, silver, aluminum, tin or tungsten or any combination thereof; after forming the lead structure 24, a protective layer 20 is deposited on the second surface of the substrate layer 11 and passed The lithography and etching processes form the structure of the protective layer 20.
  • the material of the protective layer 20 is an oxide or a nitride or an oxynitride.
  • the lead structure 24 acts as a solder pad for connecting external circuits.

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Abstract

一种存储器结构及其形成方法，存储器结构包括：第一基底（100），包括：衬底层（101）和存储层（102），存储层位于衬底层的第一表面上（11），第一基底包括焊垫区域，衬底层的第一表面至少部分区域上设置有连接部区域；连接部区域中形成有绝缘层，绝缘层具有相对设置的顶面和底面，其中顶面为朝向衬底层的第一表面的一侧，底面为朝向衬底层的第二表面（12）的一侧，存储层包括连接部，连接部的一端与绝缘层接触；介质层（103），位于衬底层的第二表面上；焊垫（701），位于焊垫区域上方的介质层表面；隔离结构（401），贯穿衬底层，用于隔离焊垫区域内的衬底层与隔离结构外围的衬底层。该存储器结构中焊垫与衬底层之间的寄生电容被减小，有利于提高存储器性能。

Description

存储器结构及其形成方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种存储器结构及其形成方法。
背景技术
近年来，闪存(Flash Memory)存储器的发展尤为迅速。闪存存储器的主要特点是在不加电的情况下能长期保持存储的信息，且具有集成度高、存取速度快、易于擦除和重写等优点，因而在微机、自动化控制等多项领域得到了广泛的应用。为了进一步提高闪存存储器的位密度(Bit Density)，同时减少位成本(Bit Cost)，三维的闪存存储器(3D NAND)技术得到了迅速发展。
在3D NAND闪存结构中，包括存储阵列结构以及位于存储阵列结构上方的CMOS电路结构，所述存储阵列结构和CMOS电路结构通常分别形成于两个不同的晶圆上，然后通过键合方式，将CMOS电路晶圆键合到存储整列结构上方，将CMOS电路和存储阵列电路连接在一起；然后再将存储阵列结构所在晶圆的背面减薄，通过贯穿背面的接触部和焊垫将整个电路接出。焊垫与晶圆背面之间具有绝缘层，当焊垫和晶圆同时有电流通过时，焊垫与晶圆之间会产生强烈的寄生电容，减慢运算存储的速度。
现有技术中，一般通过提高焊垫与晶圆之间的绝缘层厚度来减少寄生电容，通常要求绝缘层的厚度大于1.4μm，才能有效降低焊垫与晶圆之间的绝缘层。但是由于电路接出需要同时打通绝缘层和晶圆形成贯穿晶圆通孔，绝缘层厚度增加，会导致贯穿晶圆通孔的深宽比增加，并且还需要严格控制贯穿晶圆通孔的特征尺寸和形貌，工艺的偏差可能导致电路断路或者漏电，这样就大大增加工艺的难度，需要更先进的半导体处理机台，工艺成本增加。
如何有效降低存储器结构的寄生电容，是目前亟待解决的问题。
发明内容
本发明所要解决的技术问题是，提供一种存储器结构及其形成方法，有效降低存储器结构的寄生电容，提高存储器性能。
本发明的技术方案提供一种存储器结构，包括：第一基底，包括：衬底层和存储层，所述衬底层具有相对的第一表面和第二表面，所述存储层位于所述衬底层的第一表面上，所述第一基底包括焊垫区域，所述衬底层的第一表面至少部分区域上设置有连接部区域；所述连接部区域中形成有绝缘层，所述绝缘层具有相对设置的顶面和底面，其中所述顶面为朝向所述衬底层的第一表面的一侧，所述底面为朝向所述衬底层的第二表面的一侧，所述存储层包括连接部，所述连接部的一端与所述绝缘层接触；介质层，位于所述衬底层的第二表面上；焊垫，位于所述焊垫区域上方的介质层表面；隔离结构，贯穿所述衬底层，位于所述焊垫区域边缘，包围所述焊垫区域内的衬底层，用于隔离所述焊垫区域内的衬底层与所述隔离结构外围的衬底层。
可选的，还包括：第一接触部，所述第一接触部贯穿所述介质层和焊垫区域的衬底层；所述焊垫连接至所述第一接触部，所述第一接触部与所述连接部电连接。
可选的，所述第一接触部包括金属连接结构以及位于所述金属连接结构侧壁表面的绝缘侧墙。
可选的，所述衬底层的第二表面上形成有开孔，所述开孔露出所述绝缘层的至少一部分表面；所述介质层至少覆盖所述开孔的侧壁和开孔中露出的绝缘层的表面。
可选的，所述第一接触部包括第一金属连接结构和第二金属连接结构，所述第一金属连接结构与所述连接部电连接，所述第二金属连接结构位于所述开孔内，所述第一金属连接结构与该第二金属连接结构电连接。
可选的，所述隔离结构的特征尺寸小于所述第一接触部的特征尺寸。
可选的，所述隔离结构包括贯穿所述衬底层的隔离沟槽和填充满所述隔离沟槽的隔离材料。
可选的，所述焊垫在衬底层上的投影与所述隔离结构之间的最小距离为0.5μm
可选的，所述隔离结构包括两个以上套嵌设置的隔离环。
可选的，相邻隔离环之间的距离为0.8μm～1.2μm。
可选的，所述绝缘层的底面位于所述衬底层内部，所述绝缘层的顶面与所述衬底层的第一表面齐平、所述绝缘层的顶面高于所述衬底层的第一表面、所述绝缘层的底面与所述衬底层的第一表面水平接触，所述绝缘层的顶面高于所述衬底层的第一表面。
可选的，所述存储层包括三维存储器，所述三维存储器包括顺序远离衬底层第一表面的三维存储器件层和第一金属层，所述连接部位于该三维存储器件层内，所述连接部的一端与所述绝缘层接触，所述连接部的另一端与所述第一金属层接触。
可选的，所述连接部的一端位于所述绝缘层的内部中，或者所述连接部的一端与所述绝缘层的顶面接触，或者所述连接部的一端穿过所述绝缘层并与所述绝缘层的底面接触。
可选的，还包括：第二基底，所述第二基底内形成有外围电路；所述第二基底键合于所述存储层表面，所述存储层内形成有存储单元和连接所述存储单元的存储电路结构，所述第二基底内的外围电路与所述存储层内的存储电路结构之间形成电连接。
为解决上述问题，本发明的技术方案还提供一种存储器结构的形成方法，包括：提供第一基底，包括衬底层，所述衬底层具有相对的第一表面和第二表面，所述存储层位于所述衬底层的第一表面上，所述第一基底包括焊垫区域，，所述衬底层的第一表面至少部分区域上设置有连接部区域；在所述连接部区域中形成绝缘层，所述绝缘层具有相对设置的顶面和底面，其中所述顶面为朝向所述衬底层的第一表面的一侧，所述底面为朝向所述衬底层的第二表面的一侧；在所述衬底层的至少包含所述绝缘层的第一表面上形成存储层，所述存储层包括连接部，所述连接部的一端与所述绝缘层接触；在所述衬底层的第二表面形成介质层；形成贯穿所述衬底层的隔离结构，所述隔离结构位于所述焊垫区域边缘，包围焊垫区域的衬底层，用于隔离所述焊垫区域内的衬底层与所述隔离结构外围的衬底层；在所述焊垫区域上方的介质层表面形成焊垫。
可选的，还包括：形成贯穿所述介质层和焊垫区域的衬底层的第一接触部；所述焊垫连接至所述第一接触部，所述第一接触部与所述连接部电连接。
可选的，所述第一接触部和隔离结构的形成方法包括：刻蚀所述介质层至所述衬底层，在所述介质层内形成第一开口和第二开口，所述第二开口与所述连接部位置对应；沿所述第一开口和所述第二开口同时刻蚀所述衬底层，分别形成贯穿所述衬底层的隔离沟槽和接触孔，所述接触孔与对应的连接部连通；形成填充满所述隔离沟槽、第一开口以及覆盖所述接触孔和第二开口内壁表面的绝缘材料层；去除位于所述接触孔底部的绝缘材料层；形成填充满所述接触孔和第二开口的金属材料层，并以所述介质层为停止层进行平坦化处理，在所述接触孔内形成金属连接结构。
可选的，还包括：对衬底层的第二表面进行开孔处理，露出所述绝缘层的至少一部分表面；在所述衬底层的第二表面形成所述介质层，所述介质层至少覆盖所述开孔的侧壁和开孔中露出的绝缘层的表面。
可选的，所述第一接触部的形成方法包括：刻蚀所述介质层和绝缘层，在所述衬底层的第二表面与所述连接部对应的位置形成接触孔，所述接触孔与对应的连接部连通；在所述接触孔内形成第一金属连接结构，在所述开孔内形成第二金属连接结构，所述第一金属连接结构与所述第二金属连接结构电连接，并且所述第一金属连接结构与所述连接部电连接。
可选的，所述隔离结构的特征尺寸小于所述第一接触部的特征尺寸。
可选的，形成贯穿所述衬底层的隔离结构的步骤进一步包括：形成贯穿所述衬底层的隔离沟槽，所述隔离沟槽位于所述焊垫区域边缘，围绕所述焊垫区域；形成填充满所述隔离沟槽的隔离材料。
可选的，所述焊垫在衬底层上的投影与所述隔离结构之间的最小距离为0.5μm。
可选的，所述隔离结构包括两个以上套嵌设置的隔离环。
可选的，相邻隔离环之间的距离为0.8μm～1.2μm。
可选的，所述绝缘层的底面位于所述衬底层内部，所述绝缘层的顶面与所述衬底层的第一表面齐平、所述绝缘层的顶面高于所述衬底层的第一表面、所述绝缘层的底面与所述衬底层的第一表面水平接触，所述绝缘层的顶面高于所述衬底层的第一表面。
可选的，所述存储层包括三维存储器，所述三维存储器包括顺序远离衬底层第一表面的三维存储器件层和第一金属层，所述连接部位于该三维存储器件层内，所述连接部的一端与所述绝缘层接触，所述连接部的另一端与所述第一金属层接触。
可选的，所述连接部的一端位于所述绝缘层的内部中，或者所述连接部的一端与所述绝缘层的顶面接触，或者所述接触部的一端穿过所述绝缘层并与所述绝缘层的底面接触。
可选的，在所述存储层表面键合第二基底；所述存储层内形成有存储单元和连接所述存储单元的存储电路结构，所述第二基底内的外围电路与所述存储层内的存储电路结构之间形成电连接。
本发明的存储器结构的衬底层内形成有隔离结构，作为焊垫下方的衬底层与其他区域衬底层之间的物理隔离结构，所述焊垫下方的衬底层与周围隔离，不会有电流形成。因此，所述焊垫与所述衬底层之间的寄生电容会被减小，从而提高存储器结构的性能。进一步的，由于焊垫与衬底层之间的寄生电容较小，因此可以采用较低厚度的介质层，节约工艺成本，降低工艺难度。在衬底层和存储层之间设置绝缘层，并将用于金属互联的连接部设置为与该介质层接触，在形成引线连接结构的过程中，可以穿过较厚的器件层实现背面引线，降低了制作成本，提高了产品良率。
本发明的存储器结构的形成方法，在所述衬底层内形成有隔离结构作为焊垫下方的衬底层与器件区域的衬底层之间的物理隔离结构，降低焊垫与衬底层之间形成的寄生电容，从而能够提高存储器结构的性能。进一步的，所述隔离结构可以在形成贯穿衬底层的第一接触部的过程中同时形成，无需增加工艺步骤。
附图说明
图1至图7为本发明一具体实施方式的存储器结构的形成过程的结构示意图；
图8～图10为本发明一具体实施方式的存储结构中隔离环与焊垫的俯视示 意图；
图11至图13为本发明一具体实施方式的存储结构中隔离环与焊垫的俯视示意图；
图14至图18为本发明一具体实施方式的存储结构中隔离环与焊垫的俯视示意图。
具体实施方式
下面结合附图对本发明提供的存储器结构及其形成方法的具体实施方式做详细说明。
请参考图1至图7，为本发明一具体实施方式的存储器结构的形成过程的结构示意图。
请参考图1，提供第一基底100，包括：衬底层101和存储层102，所述衬底层101具有相对的第一表面11和第二表面12，所述存储层102位于所述衬底层101的第一表面11上，所述第一基底100包括焊垫区域I；在所述衬底层101的第二表面12上形成介质层103。
图1中，所述第一基底100处于倒置状态，此时，所述衬底层101的第一表面11为衬底层101的下表面，而第二表面12为衬底层101的上表面。所述存储层102覆盖所述衬底层101的第一表面11，在倒置状态下，相应的所述存储层102也位于所述衬底层101的下方。在本发明的具体实施方式的描述过程中，各材料层之间的实际相对位置，请结合具体实施方式中的文字描述以及附图中的实际相对位置进行理解。
所述衬底层101为半导体材料层，可以为单晶硅晶圆、包括单晶硅晶圆以及晶圆表面的半导体外延层、或者绝缘体上硅衬底等。本具体实施方式中，所述衬底层101包括单晶硅晶圆以及位于所述单晶硅衬底表面的单晶硅外延层，所述单晶硅外延层表面为第一表面11，所述单晶硅晶圆另一侧表面为第二表面12。
所述存储层102包括绝缘层以及形成于所述绝缘层内的存储单元以及连接 所述存储单元的存储电路。在一个具体实施方式中，所述存储层102内形成有3D NAND存储单元。所述存储层102内还形成有第二接触部121。所述第二接触部121可以为用于连接存储单元的互连结构，也可以为用于连接衬底层101和第二基底200内电路的互连结构。图1中，示出存储层102内的部分第二接触部121，仅作为示意。
所述第一基底100的焊垫区域I内用于形成连接各层电路的电路连接结构以及后续在焊垫区域I上形成用于连接外部电路与内部电路的焊垫，因此，焊垫区域I内的衬底层101内通常不会形成掺杂阱等功能区域，且所述焊垫区域I内的存储层102内形成有第二接触部121，用于通过后续形成的贯穿焊垫区域I内的衬底层101的第一接触部将存储层102内的电路连出。
所述第一基底100还包括焊垫区域I以外的器件区域II。所述第一基底100的器件区域II内用于形成半导体器件，所述焊垫区域I通常位于所述器件区域II的外围。在一个具体实施方式中，所述器件区域II内的衬底层101内形成有掺杂阱，所述器件区域II内的存储层102内形成有存储单元，在存储器结构工作的过程中，所述器件区域II的衬底层101内需要通过电流。
可以采用沉积工艺在所述衬底层101的第二表面12上形成所述介质层103。所述介质层103作为覆盖所述衬底层101第二表面12的钝化层，用于保护所述衬底层101的第二表面12。所述介质层103的材料可以为TEOS、氮化硅、氮氧化硅、氧化硅等绝缘介质材料。所述介质层103可以为单层结构可以为多层堆叠结构。可以通过化学气相沉积工艺、旋涂工艺、原子层沉积工艺等各种沉积工艺形成所述介质层103。
该具体实施方式中，所述存储层102与所述衬底层101相对的另一侧表面还与一第二基底200键合连接。所述第二基底200内形成有外围电路，所述第二基底200位于所述存储层102表面，所述第二基底200内的外围电路与所述存储层102内的存储电路之间形成电连接。具体的，所述第二基底200朝向所述存储层102的表面暴露出外围电路的连接部的表面，而所述存储层102的表面暴露出存储电路的连接部表面，两者键合，形成电连接。
请参考图2，刻蚀所述介质层103至所述衬底层101的第二表面12，在所 述介质层103内形成第一开口131和第二开口132。
具体的，所述第一开口131和第二开口132的形成方法包括：在所述介质层103表面形成光刻胶层，采用一光罩对所述光刻胶层进行曝光显影，形成图形化的光刻胶层；以所述图形化光刻胶层为掩膜层，刻蚀所述介质层103，形成所述第一开口131和第二开口132。所述第一开口131用来定义后续待形成的隔离结构的位置和尺寸，所述第二开口132用于定义后续待形成的贯穿所述衬底层101的第一接触部的位置和尺寸。采用同一光罩进行光刻工艺在介质层103上形成图形化光刻胶层，再刻蚀介质层103，同时形成所述第二开口132和第一开口131，无需针对隔离结构额外增加工艺步骤。
所述第一开口131为环形沟槽状；所述第二开口132为孔状，横截面可以为圆形、矩形或多边形等。
该具体实施方式中，不仅在焊垫区域I上方的介质层内形成所述第二开口132，还在所述器件区域II上方的介质层内也形成所述第二开口132，以便后续同时在所述焊垫区域I和器件区域II内同时形成连接存储层102的第一接触部。
请参考图3，沿所述第一开口131和所述第二开口132同时刻蚀所述衬底层101，分别形成贯穿所述衬底层101的隔离沟槽113和接触孔114。
所述接触孔114底部暴露出所述存储层102内的第二接触部121，后续在所述接触孔114内形成贯穿衬底层101的第一接触部，与所述存储层102内的第二接触部121连接。
所述隔离沟槽113位于所述焊垫区域I边缘，围绕所述焊垫区域I设置。该具体实施方式中，所述隔离沟槽113位于所述焊垫区域I与器件区域II的界面处，所述隔离沟槽113的一侧侧壁暴露出所述焊垫区域I内的衬底层101，另一侧侧壁暴露出器件区域II内的衬底层101。在另一具体实施方式中，所述隔离沟槽113完全位于所述焊垫区域I内；在另一具体实施方式中，所述隔离沟槽113还可以完全位于所述器件区域II内，靠近所述焊垫区域I。在另一具体实施方式中，不仅在所述焊垫区域I边缘形成隔离沟槽113，还可以同时在所述焊垫区域I内部的接触孔114之间形成所述隔离沟槽。
所述隔离沟槽113的特征尺寸小于所述接触孔114的特征尺寸。该具体实施方式中，所述隔离沟槽113的特征尺寸为隔离沟槽113的宽度，所述接触孔114的横截面为圆形，所述接触孔114的特征尺寸为接触孔114的横截面直径。在本发明的具体实施方式中，所述隔离沟槽113的宽度为小于接触孔114的孔径宽度的一半，大于20nm，所述接触孔114的孔径最大宽度为1500nm。
请参考图4，形成填充满所述隔离沟槽113(请参考图3)、第一开口131(请参考图3)以及覆盖所述接触孔114和第二开口132内壁表面的绝缘材料层400。
所述绝缘材料层400的材料可以为氧化硅、氮氧化硅或氮化硅等绝缘介质材料。可以采用化学气相沉积工艺、原子层沉积工艺、等离子体增强化学气相沉积工艺等形成所述绝缘材料层400。由于所述隔离沟槽113的特征尺寸小于所述接触孔114的特征尺寸，所述绝缘材料层400填充满所述隔离沟槽113和第一开口131时，所述绝缘材料层400仅覆盖所述接触孔114和第二开口132的内壁表面。
所述绝缘材料层400还覆盖所述介质层103的表面。
请参考图5，去除位于所述接触孔114底部的绝缘材料层400，形成覆盖所述接触孔114和第二开口132侧壁的绝缘侧墙402，填充于所述隔离沟槽113和第一开口131内的绝缘材料层作为隔离结构401。
采用各向异性刻蚀工艺去除位于所述接触孔114底部的绝缘材料层400。在去除所述接触孔114底部的绝缘材料层400的同时，还将位于所述介质层103表面的绝缘材料层400去除。在其他具体实施方式中，去除位于所述接触孔114底部的绝缘材料层400之后，所述介质层103表面还剩余部分厚度的绝缘材料层400。
所述隔离结构401包围所述焊垫区域I的衬底层101，在所述焊垫区域I内的衬底层101与所述隔离结构401外围的衬底层101之间构成物理隔离。当存储器结构在工作过程过程中，器件区域II的衬底层101有电流通过时，由于隔离结构401的隔离作用，所述焊垫区域I的衬底层101内不会有电流通过，因此可以降低后续在焊垫区域I上方形成的焊垫之间形成寄生电容。因此，无 需通过提高介质层103的厚度来降低寄生电容，可以使所述介质层103保持较低的厚度。在一个具体实施方式中，所述介质层103的厚度大于100nm，例如可以为100nm～500nm。在一个具体实施方式中，所述介质层103的厚度为400nm。
该具体实施方式中，在形成所述绝缘侧墙402的过程中，同步形成所述隔离结构401，无需增加额外的工艺步骤。
请参考图6，形成填充满所述接触孔114和第二开口132的金属材料层，并以所述介质层103为停止层进行平坦化，形成位于所述接触孔114(请参考图5)和第二开口132(请参考图5)内的金属柱403。所述绝缘侧墙402和金属柱403构成第一接触部。
所述金属材料层的材料可以为W、Cu、Al、Au等金属材料。可以采用物理气相沉积工艺，例如溅射工艺，形成所述金属材料层。
对所述金属材料层进行平坦化，去除位于介质层103表面的金属材料层，形成金属柱403，所述金属柱403连接至所述存储层102内的第二接触部121，实现与所述存储层102内的存储电路的连接。
请参考图7，在所述焊垫区域I上的介质层103表面形成焊垫701以及覆盖所述介质层103和焊垫701的保护层703，所述保护层703具有开口暴露出所述焊垫701表面。
在形成所述焊垫701的同时，还包括在所述器件区域II上的介质层103表面形成互连线702，所述互连线702连接所述器件区域II内的金属柱403。
所述焊垫701在衬底层101上的投影与所述隔离结构401之间的最小距离为0.5μm，以使得所述焊垫701与隔离结构401均具有足够的工艺窗口，确保位于焊垫701下方的衬底层101均被所述隔离结构401包围。所述焊垫701通常为一矩形，边长为70μm～80μm，面积较大，容易引起较大的寄生电容。而本发明的具体实施方式，通过隔离结构401的隔离，使得焊垫701下方的衬底层101没有电流通过，从而降低所述焊垫701与衬底层101之间形成寄生电容。
所述互连线702与所述焊垫701同时形成，具体的，形成覆盖介质层103和第一接触部的金属层，对所述金属层进行图形化刻蚀，形成焊垫701和互连 线702，然后再形成覆盖所述介质层103、互连线702以及焊垫701的保护层703，并刻蚀所述保护层703，暴露出所述焊垫701的表面，以便后续将焊垫701连接至外部电路。所述互连线702和焊垫701的材料可以为Al、Cu、Au或Ag等金属。
所述互连线702的尺寸较小，该具体实施方式中，互连线702的宽度为600nm，不会产生较大的寄生电容，对存储器的性能影响较小。在其他具体实施方式中，互连线702的宽度也可以为500nm～700nm。
由于该具体实施方式中，所述衬底层101内形成有隔离结构401作为焊垫701下方的衬底层101与器件区域II的衬底层102之间的物理隔离结构，所述焊垫701下方的衬底层101内部会有电流形成，因此，所述焊垫701与衬底层101之间的寄生电容被降低，从而提高存储器结构的性能。因此，所述介质层103的厚度较低也能够保持焊垫701与衬底层101之间的寄生电容较小。该具体实施方式中，所述介质层103的厚度可以为400nm。在其他具体实施方式中，所述介质层103的厚度可以为300nm～500nm。所述介质层103的厚度较低，使得接触孔114和隔离沟槽113的深宽比较低，可以降低工艺难度。
在另一具体实施方式中，还可以在形成所述介质层103之前，先刻蚀所述衬底层101形成隔离沟槽，在所述隔离沟槽内填充满隔离材料，作为隔离结构；然后再在所述衬底层101第二表面12上形成介质层103，刻蚀所述介质层103和衬底层101，形成贯穿所述介质层103和衬底层101的接触孔，在所述接触孔内壁表面形成绝缘侧墙402以及填充满所述接触孔的金属柱403。
上述具体实施方式中，所述隔离结构401为单个隔离环。
请参考图8，为所述隔离结构401与焊垫701的俯视示意图。所述焊垫701为一矩形，所述隔离结构401包围区域的形状与所述焊垫701的形状一致，所述隔离结构401与所述焊垫701各位置处之间的距离相等。在其他具体实施方式中，所述隔离结构401还可以为圆环形等其他形状。
在其他具体实施方式中，所述隔离结构可以包括两个以上套嵌设置的隔离环。
请参考图9，在另一具体实施方式中，所述隔离结构两个隔离环，分别为 隔离环401a和隔离环401b，所述隔离环401a和隔离环401b套嵌设置。该具体实施方式中，所述隔离环401a和隔离环401b之间的距离各处相等，使得各处的隔离效果一致。所述隔离环401a可以位于所述焊垫区域I内，所述隔离环401b位于所述器件区域II内；或者所述隔离环401a和隔离环401b均位于所述器件区域II内或均位于所述焊垫区域I内。通过两个隔离环包围区域内的衬底层101进行隔离，可以提高隔离效果。所述隔离环401a和隔离环401b之间的间距可以为0.8μm～1.2μm。在其他具体实施方式中，所述隔离环401a和隔离环401b各位置处的间距也可以随位置不同而不同。
请参考图10，在另一具体实施方式中，所述隔离结构包括三个隔离环，分别为隔离环401a、隔离环401b和隔离环401c。所述隔离环401a与隔离环401b之间具有间距d1，隔离环401b与隔离环401c之间具有间距d2，该具体实施方式中，d1＝d2；在其他具体实施方式中，d1和d2也可以不相等。
具有多个隔离环的隔离结构能够进一步的提高隔离效果，最大程度降低焊垫701与衬底层101之间的寄生电容。
本发明的具体实施方式还提供一种上述方法形成的存储结构。
请参考图7，为本发明一具体实施方式的存储结构的结构示意图。
所述存储结构包括：第一基底100，所述第一基底100包括：衬底层101和存储层102，所述衬底层101具有相对的第一表面11和第二表面12，所述存储层102位于所述衬底层101的第一表面11上，所述第一基底100包括焊垫区域I；介质层103，位于所述衬底层101的第二表面12上；焊垫701，位于所述焊垫区域I上的介质层103表面；隔离结构401，贯穿所述衬底层101，且位于所述焊垫区域I边缘，包围所述焊垫区域I内的衬底层101，用于隔离所述焊垫区域I内的衬底层101与所述隔离结构401外围的衬底层101。
所述衬底层101为半导体材料层，可以为单晶硅晶圆、包括单晶硅晶圆以及晶圆表面的半导体外延层、或者绝缘体上硅衬底等。本具体实施方式中，所述衬底层101包括单晶硅晶圆以及位于所述单晶硅衬底表面的单晶硅外延层，所述单晶硅外延层表面为第一表面11，所述单晶硅晶圆另一侧表面为第二表面12。
图7中，所述第一基底100处于倒置状态，此时，所述衬底层101的第一表面11为衬底层101的下表面，而第二表面12为衬底层101的上表面。所述存储层102覆盖所述衬底层101的第一表面11，在倒置状态下，相应的所述存储层102也位于所述衬底层101的下方。
所述存储层102包括绝缘层以及形成于所述绝缘层内的存储单元以及连接所述存储单元的存储电路。在一个具体实施方式中，所述存储层102内形成有3D NAND存储单元。所述存储层102内还形成有第二接触部121。所述第二接触部121可以为用于连接存储单元的互连结构，也可以为用于连接衬底层101和第二基底200内电路的互连结构。
该具体实施方式中，所述存储层102与所述衬底层101相对的另一侧表面还与一第二基底200键合连接，所述第二基底200内形成有外围电路；所述第二基底200位于所述存储层102表面，所述第二基底200内的外围电路与所述存储层102内的存储电路之间形成电连接。具体的，所述第二基底200朝向所述存储层102的表面暴露出外围电路的连接部的表面，而所述存储层102的表面暴露出存储电路的连接部表面，两者键合，形成电连接。
所述第一基底100还包括器件区域II，所述器件区域II用于形成半导体器件，所述焊垫区域I通常位于所述器件区域II的外围。在一个具体实施方式中，所述器件区域II内的衬底层101内形成有掺杂阱，所述器件区域II内的存储层102内形成有存储单元，在存储器结构工作的过程中，所述器件区域II的衬底层101内需要通过电流。所述第一基底100的焊垫区域I内用于形成连接各层电路的电路连接结构以及后续在焊垫区域I上形成用于连接外部电路与内部电路的焊垫，因此，焊垫区域I内的衬底层101内通常不会形成掺杂阱等功能区域，且所述焊垫区域I内的存储层102内形成有第二接触部121，用于通过后续形成的贯穿焊垫区域I内的衬底层101的第一接触部将存储层102内的电路连出。图1中，示出存储层102内的部分第二接触部121，仅作为示意。
所述介质层103作为所述衬底层101第二表面12上的钝化层，用于保护所述衬底层101的第二表面12。所述介质层103的材料可以为TEOS、氮化硅、氮氧化硅、氧化硅等绝缘介质材料。所述介质层103可以为单层结构可以为多 层堆叠结构。可以通过化学气相沉积工艺、旋涂工艺、原子层沉积工艺等各种沉积工艺形成所述介质层103。该具体实施方式中，所述介质层103的厚度大于100nm，例如可以为100nm～500nm。在一个具体实施方式中，所述介质层103的厚度为400nm。
所述隔离结构401包括贯穿所述衬底层101的隔离沟槽和填充满所述隔离沟槽的隔离材料。所述隔离材料可以为氧化硅、氮氧化硅或氮化硅等绝缘介质材料。该具体实施方式中，所述隔离结构401还贯穿所述介质层103。在另一具体实施方式中，所述隔离结构401还可以仅位于所述衬底层101内。
所述隔离结构401位于所述焊垫区域I边缘，围绕所述焊垫区域I设置。该具体实施方式中，所述隔离结构401位于所述焊垫区域I与器件区域II的界面处，所述隔离结构401的一侧侧壁与所述焊垫区域I内的衬底层101接触，另一侧侧壁与器件区域II内的衬底层101接触。在另一具体实施方式中，所述隔离结构401完全位于所述焊垫区域I内；在另一具体实施方式中，所述隔离结构401还可以完全位于所述器件区域II内，靠近所述焊垫区域I。在另一具体实施方式中，不仅在所述焊垫区域I边缘形成隔离结构401，还可以同时在所述焊垫区域I内部的第一接触部的金属柱403之间形成所述隔离结构。
所述隔离结构401包围所述焊垫区域I的衬底层101，在所述焊垫区域I内的衬底层101与所述隔离结构401外围的衬底层101之间构成物理隔离。当存储器结构在工作过程过程中，器件区域II的衬底层101有电流通过，由于隔离结构401的隔离作用，所述焊垫区域I的衬底层101内不会有电流通过，因此能够降低衬底层101与焊垫区域I上方的焊垫701之间形成的寄生电容，也无需通过提高介质层103的厚度来降低寄生电容。
所述焊垫701在衬底层101上的投影与所述隔离结构401之间的最小距离为0.5μm，以使得所述焊垫701与隔离结构401均具有足够的工艺窗口，确保位于焊垫701下方的衬底层101均被所述隔离结构401包围。所述焊垫701通常为一矩形，边长在70μm～80μm之间，面积较大，容易引起较大的寄生电容，而本发明的具体实施方式，通过隔离结构401的隔离，使得焊垫701下方的衬底层101没有电流通过，从而降低所述焊垫701与衬底层101之间形成的寄生 电容。
所述存储结构还包括：贯穿所述介质层103和衬底层101的第一接触部，所述第一接触部包括金属柱403以及位于所述金属柱403侧壁表面的绝缘侧墙402。所述金属柱403的材料可以为W、Cu、Al、Au等金属材料。所述金属柱403连接至所述第二接触部121，实现与所述存储层102内的存储电路的连接。所述器件区域II和焊垫区域I内均形成有所述第一接触部。
所述隔离结构401的特征尺寸小于所述第一接触部的特征尺寸。该具体实施方式中，所述隔离结构401的特征尺寸为隔离结构401的宽度，所述第一接触部的横截面为圆形，所述第一接触部的特征尺寸为第一接触部的横截面直径。在一个具体实施方式中，所述隔离结构401的宽度为小于第一接触部的横截面直径的一半，大于20nm，所述第一接触部的横截面的最大直径为1500nm。
由于所述隔离结构401和第一接触部均贯穿所述介质层103和衬底层101，因此，通过刻蚀介质层103和衬底层101，同时形成隔离沟槽和接触孔，然后在形成所述绝缘侧墙402的同时，形成填充所述隔离沟槽的隔离结构401，无需增加额外工艺步骤。
所述器件区域II上的介质层103表面还形成有互连线702，连接至器件区域II内的第一接触部。所述互连线702和焊垫701的材料可以为Al、Cu、Au或Ag等金属。所述互连线702的特征尺寸较小，本发明的具体实施方式中，互连线702的宽度为600nm，不会引起较大的寄生电容，对存储器的性能影响较小。在其他具体实施方式中，互连线702的宽度也可以为500nm～700nm。
所述介质层103表面还具有覆盖所述介质层103、互连线702以及焊垫701的保护层703，所述保护层703具有开口暴露出所述焊垫701的表面，以便后续将焊垫701连接至外部电路。
上述具体实施方式中，所述衬底层101内形成有隔离结构401作为焊垫701下方的衬底层101与器件区域II的衬底层101之间的物理隔离结构，所述焊垫701下方的衬底层101与周围隔离，不会有电流形成。因此，所述焊垫701与所述衬底层101之间的寄生电容被减小，从而提高存储器结构的性能。进一步的，由于焊垫701与衬底层101之间的寄生电容通过隔离结构401被减小，因 此可以采用较低厚度的介质层103进而使得贯穿所述介质层103和衬底层101的第一接触部和隔离结构401的深宽比较低，可以降低工艺难度。
上述具体实施方式中，所述隔离结构401为单个隔离环。
请参考图8，为所述隔离结构401与焊垫701的俯视示意图。所述焊垫701为一矩形，所述隔离结构401包围区域的形状与所述焊垫701的形状一致，所述隔离结构401与所述焊垫701各位置处之间的距离相等。在其他具体实施方式中，所述隔离结构401还可以为圆环形等其他形状。
在其他具体实施方式中，所述隔离结构可以包括两个以上套嵌设置的隔离环。
请参考图9，在另一具体实施方式中，所述隔离结构两个隔离环，分别为隔离环401a和隔离环401b，所述隔离环401a和隔离环401b套嵌设置。该具体实施方式中，所述隔离环401a和隔离环401b之间的距离各处相等，使得各处的隔离效果一致。所述隔离环401a可以位于所述焊垫区域I内，所述隔离环401b位于所述器件区域II内；或者所述隔离环401a和隔离环401b均位于所述器件区域II内或均位于所述焊垫区域I内。通过两个隔离环包围区域内的衬底层101进行隔离，可以提高隔离效果。所述隔离环401a和隔离环401b之间的间距可以为0.8μm～1.2μm。在其他具体实施方式中，所述隔离环401a和隔离环401b各位置处的间距也可以随位置不同而相应改变。
该具体实施方式在形成所述隔离结构的过程中，可以刻蚀衬底层101同时形成两个套嵌的环状隔离沟槽，在所述环状隔离沟槽内填充绝缘材料，形成所述隔离环401a和隔离环401b。
请参考图10，在另一具体实施方式中，所述隔离结构包括三个隔离环，分别为隔离环401a、隔离环401b和隔离环401c。所述隔离环401a与隔离环401b之间具有间距d1，隔离环401b与隔离环401c之间具有间距d2，该具体实施方式中，d1＝d2；在其他具体实施方式中，d1和d2也可以不相等。
具有多个隔离环的隔离结构能够进一步的提高隔离效果，最大程度降低焊垫701与衬底层101之间的寄生电容。
请参考11至图13，为本发明一具体实施方式的存储器结构的形成过程的 结构示意图。
请参考图11，提供一第一基底，包括衬底层11，所述衬底层11具有相对设置的第一表面和第二表面；该衬底层11的第一表面至少部分区域上设置有连接部区域12；在所述连接部区域12中形成绝缘层13，该绝缘层13为氧化物绝缘层13或氮化物绝缘层13，在该连接部区域12中形成绝缘层13的工艺包括微影、刻蚀、沉积、填充和研磨之一或其任意组合，该绝缘层13具有相对设置的顶面和底面，其中该顶面为朝向该衬底层第一表面的一侧，该底面为朝向该衬底层第二表面的一侧。图8中，仅示出了衬底层11的焊垫区域。
在该具体实施方式中，在形成该绝缘层13的步骤中，首先，通过微影和刻蚀工艺在该衬底层11的第一表面的连接部区域12形成一浅沟槽，再利用沉积和填充工艺在该浅沟槽中形成该绝缘层13，后续还可以通过研磨工艺对该绝缘层13进行研磨使其平坦化。经过上述工艺步骤后，形成的该绝缘层13的底面位于该衬底层11内部，该绝缘层13的顶面与该衬底层11的第一表面齐平。优选地，该绝缘层13的厚度约为1微米。
上述形成绝缘层的具体工艺步骤为，首先，在衬底层的第一表面上形成硬掩膜层，依次刻蚀所述硬掩膜层和衬底层，形成沟槽，硬掩膜层例如是采用化学气相沉积工艺形成的氮化硅层，或者采用高密度等离子体化学气相沉积(High Density Plasma Chemical Vapor Deposition，HDPCVD)工艺形成的氧化硅层。刻蚀所述硬掩膜层和衬底层，形成沟槽可以采用本领域技术人员熟知的任何现有技术。
然后，在所述沟槽内以及硬掩膜层上沉积绝缘层，所述绝缘层填满沟槽；所述的绝缘层材料例如氧化硅、氮化硅、氮氧化硅等，填入介质材料的工艺例如采用高密度等离子体化学气相沉积(High Density Plasma Chemical Vapor Deposition，HDPCVD)法。
然后，去除位于硬掩膜层上的绝缘层；去除硬掩膜层上的绝缘层的工艺例如通过化学机械抛光(Chemical Mechanical Polishing，CMP)的方法，CMP之后，硬掩膜层表面以上沉积的绝缘层被完全去除，从而硬掩膜层的上表面全部暴露出来。
然后，进行快速热氧化处理，进行快速热氧化的环境温度为400～800摄氏度，采用本步骤可以消除沟槽的边角在前述工艺中对原子结构造成的损伤，避免在后续的工艺中造成沟槽边角损伤。优选的，沟槽所处的环境温度为500-700摄氏度。在本发明的一个具体实施方式中，在60秒～140秒内将沟槽所处的环境温度线性加热至400～800摄氏度。
具体实施中，沟槽所处的环境温度例如可以选用450摄氏度，480摄氏度，550摄氏度，600摄氏度，660摄氏度，640摄氏度，750摄氏度等。线形加热环境温度的时间例如70秒，75秒，80秒，95秒，103秒，115秒，125秒，130秒。
在所述的快速热氧化工艺中，还包括向沟槽所在的环境通入含氧气体的工艺步骤，所述的含氧气体例如氧气(O 2)，臭氧(O 3)等具有氧化能力的气体。
在所述的快速热氧化工艺中，所述沟槽中的绝缘层处于高温氧气环境当中，高温环境下的氧气分子浓度较大且分子活性较高，又由于所述沟槽中绝缘层边角处原先的分子结构较为疏松，因此所述CMP过程中产生的游离态硅离子在这一过程中将被充分氧化，氧化后生成的氧化物与沟槽中的绝缘层中原有的氧化物分子在高温下重新结合形成稳定的分子键，使得所述沟槽中的绝缘层的边角处的氧化物结构由原先的疏松变得稳固、致密，从而所述沟槽中的绝缘层的边角损伤能够得到有效修复，所述高温氧化的过程通常也被俗称为高温淬火。
最后，去除硬掩膜层。去除所述硬掩膜层的工艺例如采用湿法刻蚀(Wet Etch)，所使用的化学刻蚀试剂根据硬掩膜层材料的不同而不同，为本领域技术人员习知的技术。
在另一具体实施方式中，所述绝缘层13具有相对设置的底面和顶面，该底面为相对于顶面更远离该第一金属层18的一侧。在形成该绝缘层13的步骤中，首先，通过微影和刻蚀工艺在该衬底层11的第一表面的接触孔区域12形成一浅沟槽，再利用沉积和填充工艺在该浅沟槽中形成该绝缘层13，后续还可以通过研磨工艺对该绝缘层13进行研磨使其平坦化。经过上述工艺步骤后，形成的该绝缘层13的底面位于该衬底层11内部，该绝缘层13的顶面高于该 衬底层11的第一表面。优选地，该绝缘层13的厚度约为1微米。
在另一具体实施方式中，该绝缘层13具有相对设置的底面和顶面，该底面为相对于顶面更远离该第一金属层18的一侧。在形成该绝缘层13的步骤中，首先，通过沉积工艺在该衬底层11的第一表面的接触孔区域12表面上形成该绝缘层13，后续还可以通过研磨工艺对该绝缘层13进行研磨使其平坦化。经过上述工艺步骤后，形成的该绝缘层13的底面与该衬底层11的第一表面水平接触，该绝缘层13的顶面高于该衬底层11的第一表面。优选地，该绝缘层13的厚度约为1微米。
在该衬底层11的第一表面至少包含绝缘层13的区域上形成存储层14，该存储层14包括连接部15，该连接部15的一端与该绝缘层13接触，该连接部15为连接孔中填充的金属材料，该金属材料为铜、铝、锡或钨之一或其任意组合；该存储层14包括三维存储器，该三维存储器包括顺序远离该衬底层11第一表面的三维存储器件层141和第一金属层18，该连接部15位于该三维存储器件层141内，该连接部15的一端与该绝缘层13接触，该连接部15的另一端与该第一金属层18接触。所述连接部15的一端位于该绝缘层13的内部中。或者，该连接部15的一端与该绝缘层13的顶面接触，或者连接部15的一端穿过该绝缘层13并与绝缘层13的底面接触。
将包括该存储层14的衬底层11的存储层14一侧与第二基底16键合，并将该衬底层11的第二表面进行减薄；在减薄后的该衬底层的第二表面上沉积介质层19，该介质层的材质为氧化物或氮化物或氮氧化物。
请参考图12，刻蚀所述介质层19和衬底层11，在该衬底层11的第一表面与该连接部15对应的位置形成接触孔21，在衬底层11的焊垫区域边缘形成围绕所述焊垫区域设置隔离沟槽；并在所述隔离沟槽内填充绝缘材料，形成隔离结构191，同时在接触孔21侧壁表面形成绝缘侧墙23。所述接触孔21与对应的所述连接部15连通。所述隔离结构191围绕所述焊垫区域内的接触孔21设置。具体的，所述接触孔21和隔离结构191的形成方法包括：刻蚀所述介质层19至所述衬底层11，在所述介质层19内形成第一开口和第二开口，所述第二开口与所述连接部15位置对应；沿所述第一开口和所述第二开口同时刻 蚀所述衬底层11，分别形成贯穿所述衬底层的隔离沟槽和接触孔21，所述接触孔21与对应的所述连接部15连通；形成填充满所述隔离沟槽、第一开口以及覆盖所述接触孔21和第二开口内壁表面的绝缘材料层；去除位于所述接触孔底部的绝缘材料层，形成绝缘侧墙23。
请参考图13，形成填充满所述接触孔21和第二开口的金属材料层，并以所述介质层19为停止层对所述金属材料层进行平坦化，在所述接触孔21内形成金属连接结构22；在衬底层11的第二表面沉积引线金属层，并对该引线金属层利用微影刻蚀定义引线结构17，该引线结构17与该接触孔21内的该金属连接结构22电连接，该引线金属层的材料为铜、银、铝、锡或钨之一或其任意组合。在形成引线结构17之后，在该衬底层11的第二表面沉积第二保护层，并通过微影和刻蚀工艺将该第二保护层形成第二保护层结构20。该第二保护层的材质为氧化物或氮化物或氮氧化物。所述引线结构17为作为后续连接外部电路的焊垫。
请参考图14至图18，为本发明另一具体实施方式的存储器结构的形成过程的结构示意图。在该实施例中，将描述与以上实施例不同的部分，相同部分将不再赘述。
请参考图14，在减薄后的该衬底层11的第二表面进行开孔处理，露出该绝缘层13的至少一部分表面。图14仅示出了衬底层11的焊垫区域。
请参考图15，在该衬底层11的第二表面制作介质层19，至少覆盖该开孔的侧壁和开孔中露出的绝缘层13的表面，该介质层19的材质为氧化物、氮化物或氮氧化物之一或其任意组合。
请参考图16，刻蚀介质层19和绝缘层13在该衬底层11的第二表面与该连接部15对应的位置形成接触孔21，形成该接触孔21的工艺包括微影和刻蚀，该接触孔21与对应的连接部15连通。在形成所述接触孔21的同时，刻蚀介质层19和衬底层11，在所述焊垫区域外围形成隔离沟槽，并在所述隔离沟槽内填充绝缘材料，形成隔离结构191。所述隔离结构包围焊垫区域内的所述接触孔21设置。
请参考图17，在该通孔21内形成第一金属连接结构2101，在该开孔内形 成第二金属连接结构2102，该第一金属连接结构2101与该第二金属连接结构2102电连接，并且该第一金属连接结构2101与该连接部15电连接，在该通孔内形成第一金属连接结构以及在该开孔内形成第二金属连接结构的工艺包括金属填充和化学机械研磨；该第一金属连接结构2101和第二金属连接结构2102的材料为铜、铝、锡或钨之一或其任意组合。
请参考图18，在所述衬底层11的第二表面沉积引线金属层，并对该引线金属层利用微影和刻蚀工艺定义引线结构24，该引线结构24与该第二金属连接结构2102电连接，该引线金属层的材料为铜、银、铝、锡或钨之一或其任意组合；在形成引线结构24之后，在所述衬底层11的第二表面沉积保护层20，并通过微影和刻蚀工艺形成保护层20结构。该保护层20的材质为氧化物或氮化物或氮氧化物。所述引线结构24作为连接外部电路的焊垫。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (20)

  1. 一种存储器结构，其特征在于，包括：
    第一基底，包括：衬底层和存储层，所述衬底层具有相对的第一表面和第二表面，所述存储层位于所述衬底层的第一表面上，所述第一基底包括焊垫区域，所述衬底层的第一表面至少部分区域上设置有连接部区域；
    所述连接部区域中形成有绝缘层，所述绝缘层具有相对设置的顶面和底面，其中所述顶面为朝向所述衬底层的第一表面的一侧，所述底面为朝向所述衬底层的第二表面的一侧，所述存储层包括连接部，所述连接部的一端与所述绝缘层接触；
    介质层，位于所述衬底层的第二表面上；
    焊垫，位于所述焊垫区域上方的介质层表面；
    隔离结构，贯穿所述衬底层，位于所述焊垫区域边缘，包围所述焊垫区域内的衬底层，用于隔离所述焊垫区域内的衬底层与所述隔离结构外围的衬底层。
  2. 根据权利要求1所述的存储器结构，其特征在于，还包括：第一接触部，所述第一接触部贯穿所述介质层和焊垫区域的衬底层；所述焊垫连接至所述第一接触部，所述第一接触部与所述连接部电连接。
  3. 根据权利要求2所述的存储器结构，其特征在于，所述第一接触部包括金属连接结构以及位于所述金属连接结构侧壁表面的绝缘侧墙。
  4. 根据权利要求2所述的存储器结构，其特征在于，所述衬底层的第二表面上形成有开孔，所述开孔露出所述绝缘层的至少一部分表面；所述介质层至少覆盖所述开孔的侧壁和开孔中露出的绝缘层的表面。
  5. 根据权利要求4所述的存储器结构，其特征在于，所述第一接触部包括第一金属连接结构和第二金属连接结构，所述第一金属连接结构与所述连接部电连接，所述第二金属连接结构位于所述开孔内，所述第一金属连接结构与该第二金属连接结构电连接。
  6. 根据权利要求2所述的存储器结构，其特征在于，所述隔离结构的特征尺寸小于所述第一接触部的特征尺寸。
  7. 根据权利要求1所述的存储器结构，其特征在于，所述隔离结构包括贯穿所述衬底层的隔离沟槽和填充满所述隔离沟槽的隔离材料。
  8. 根据权利要求1所述的存储器结构，其特征在于，所述焊垫在衬底层上的投影与所述隔离结构之间的最小距离为0.5μm
  9. 根据权利要求1所述的存储器结构，其特征在于，所述隔离结构包括两个以上套嵌设置的隔离环。
  10. 根据权利要求9所述的存储器结构，其特征在于，相邻隔离环之间的距离为0.8μm～1.2μm。
  11. 根据权利要求1所述的存储器结构，其特征在于，所述绝缘层的底面位于所述衬底层内部，所述绝缘层的顶面与所述衬底层的第一表面齐平、所述绝缘层的顶面高于所述衬底层的第一表面、所述绝缘层的底面与所述衬底层的第一表面水平接触，所述绝缘层的顶面高于所述衬底层的第一表面。
  12. 根据权利要求1所述的存储器结构，其特征在于，所述存储层包括三维存储器，所述三维存储器包括顺序远离衬底层第一表面的三维存储器件层和第一金属层，所述连接部位于该三维存储器件层内，所述连接部的一端与所述绝缘层接触，所述连接部的另一端与所述第一金属层接触。
  13. 根据权利要求1所述的存储器结构，其特征在于，所述连接部的一端位于所述绝缘层的内部中，或者所述连接部的一端与所述绝缘层的顶面接触，或者所述连接部的一端穿过所述绝缘层并与所述绝缘层的底面接触。
  14. 根据权利要求1所述的存储器结构，其特征在于，还包括：第二基底，所述第二基底内形成有外围电路；所述第二基底键合于所述存储层表面，所述存储层内形成有存储单元和连接所述存储单元的存储电路结构，所述第二基底内的外围电路与所述存储层内的存储电路结构之间形成电连接。
  15. 一种存储器结构的形成方法，其特征在于，包括：
    提供第一基底，包括衬底层，所述衬底层具有相对的第一表面和第二表面，所述存储层位于所述衬底层的第一表面上，所述第一基底包括焊垫区域，，所述衬底层的第一表面至少部分区域上设置有连接部区域；
    在所述连接部区域中形成绝缘层，所述绝缘层具有相对设置的顶面和底面，其中所述顶面为朝向所述衬底层的第一表面的一侧，所述底面为朝向所述衬底层的第二表面的一侧；
    在所述衬底层的至少包含所述绝缘层的第一表面上形成存储层，所述存储层包括连接部，所述连接部的一端与所述绝缘层接触；
    在所述衬底层的第二表面形成介质层；
    形成贯穿所述衬底层的隔离结构，所述隔离结构位于所述焊垫区域边缘，包围焊垫区域的衬底层，用于隔离所述焊垫区域内的衬底层与所述隔离结构外围的衬底层；
    在所述焊垫区域上方的介质层表面形成焊垫。
  16. 根据权利要求15所述的存储器结构的形成方法，其特征在于，还包括：形成贯穿所述介质层和焊垫区域的衬底层的第一接触部；所述焊垫连接至所述第一接触部，所述第一接触部与所述连接部电连接。
  17. 根据权利要求16所述的存储器结构的形成方法，其特征在于，包括：还包括：对衬底层的第二表面进行开孔处理，露出所述绝缘层的至少一部分表面；在所述衬底层的第二表面形成所述介质层，所述介质层至少覆盖所述开孔的侧壁和开孔中露出的绝缘层的表面。
  18. 根据权利要求15所述的存储器结构的形成方法，其特征在于，形成贯穿所述衬底层的隔离结构的步骤进一步包括：形成贯穿所述衬底层的隔离沟槽，所述隔离沟槽位于所述焊垫区域边缘，围绕所述焊垫区域；形成填充满所述隔离沟槽的隔离材料。
  19. 根据权利要求15所述的存储器结构的形成方法，其特征在于，所述焊垫在衬底层上的投影与所述隔离结构之间的最小距离为0.5μm。
  20. 根据权利要求15所述的存储器结构的形成方法，其特征在于，所述隔离结构包括两个以上套嵌设置的隔离环。
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US20090008747A1 (en) * 2007-07-02 2009-01-08 Masataka Hoshino Semiconductor device and method for manufacturing thereof
CN104810396A (zh) * 2014-01-23 2015-07-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法

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* Cited by examiner, † Cited by third party
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US20090008747A1 (en) * 2007-07-02 2009-01-08 Masataka Hoshino Semiconductor device and method for manufacturing thereof
CN104810396A (zh) * 2014-01-23 2015-07-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法

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