WO2020024282A1 - 存储器结构及其形成方法 - Google Patents
存储器结构及其形成方法 Download PDFInfo
- Publication number
- WO2020024282A1 WO2020024282A1 PCT/CN2018/098612 CN2018098612W WO2020024282A1 WO 2020024282 A1 WO2020024282 A1 WO 2020024282A1 CN 2018098612 W CN2018098612 W CN 2018098612W WO 2020024282 A1 WO2020024282 A1 WO 2020024282A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- isolation
- substrate
- substrate layer
- memory
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000002955 isolation Methods 0.000 claims abstract description 220
- 239000000758 substrate Substances 0.000 claims abstract description 217
- 230000000149 penetrating effect Effects 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 17
- 239000011810 insulating material Substances 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 230000002093 peripheral effect Effects 0.000 claims description 12
- 239000007769 metal material Substances 0.000 claims description 9
- 238000011049 filling Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 23
- 230000007334 memory performance Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 304
- 235000012431 wafers Nutrition 0.000 description 19
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
Definitions
- the present invention relates to the field of semiconductor technology, and in particular, to a memory structure and a method for forming the same.
- flash memory has been particularly rapid.
- the main feature of flash memory is that it can keep stored information for a long time without powering on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used.
- the technology of three-dimensional flash memory (3D NAND) has been rapidly developed.
- the 3D NAND flash memory structure includes a memory array structure and a CMOS circuit structure located above the memory array structure.
- the memory array structure and the CMOS circuit structure are usually formed on two different wafers respectively, and then by bonding, the The CMOS circuit wafer is bonded to the entire memory array structure to connect the CMOS circuit and the memory array circuit together; then, the back of the wafer on which the memory array structure is located is thinned, and the entire circuit is connected through the contact portion and the solder pad which penetrate the back surface. Out. There is an insulating layer between the pad and the back of the wafer. When a current is passed through the pad and the wafer at the same time, a strong parasitic capacitance will be generated between the pad and the wafer, which slows down the speed of computing storage.
- parasitic capacitance is generally reduced by increasing the thickness of the insulating layer between the bonding pad and the wafer.
- the thickness of the insulating layer is required to be greater than 1.4 ⁇ m to effectively reduce the insulating layer between the bonding pad and the wafer.
- the technical problem to be solved by the present invention is to provide a memory structure and a method for forming the same, which can effectively reduce the parasitic capacitance of the memory structure and improve the performance of the memory.
- the technical solution of the present invention provides a memory structure, including: a memory structure including: a first substrate including: a substrate layer and a storage layer; the substrate layer has a first surface and a second surface opposite to each other; A layer is located on the first surface of the substrate layer, the first substrate includes a pad region; a dielectric layer is located on the second surface of the substrate layer; a pad is located on the surface of the dielectric layer above the pad region; An isolation structure that penetrates the substrate layer and is located at the edge of the pad region and surrounds the substrate layer in the pad region, and is used to isolate the substrate layer in the pad region and the substrate layer around the isolation structure; .
- the method further includes: a first contact portion that penetrates the dielectric layer and a substrate layer in a pad region; the pad is connected to the first contact portion.
- the first contact portion includes a metal pillar and an insulating side wall located on a side wall surface of the metal pillar.
- a characteristic size of the isolation structure is smaller than a characteristic size of the first contact portion.
- the isolation structure includes an isolation trench penetrating the substrate layer and an isolation material filling the isolation trench.
- the minimum distance between the projection of the pad on the substrate layer and the isolation structure is 0.5 ⁇ m.
- the isolation structure includes more than two isolation rings nested in a set.
- the distance between adjacent isolation rings is 0.8 ⁇ m to 1.2 ⁇ m.
- a second contact portion is formed in the storage layer, and the first contact portion is connected to the second contact portion.
- it further includes: a second substrate having peripheral circuits formed therein; the second substrate is bonded to the surface of the storage layer, and a storage unit is formed in the storage layer and connected to the storage A memory circuit structure of the cell, an electrical connection is formed between a peripheral circuit in the second substrate and a memory circuit structure in the memory layer.
- a specific embodiment of the present invention further provides a method for forming a memory structure, including: providing a first substrate including a substrate layer and a storage layer, the substrate layer having a first surface and a second surface opposite to each other, The storage layer is located on a first surface of the substrate layer, the first substrate includes a pad region; a dielectric layer is formed on a second surface of the substrate layer; an isolation structure is formed through the substrate layer, and An isolation structure is located at the edge of the pad region and surrounds the substrate layer in the pad region, and is used to isolate the substrate layer in the pad region from the substrate layer in the periphery of the isolation structure; a dielectric layer above the pad region Pads are formed on the surface.
- the method further includes: forming a first contact portion of the substrate layer penetrating the dielectric layer and the pad region; and the pad is connected to the first contact portion.
- the method for forming the first contact portion and the isolation structure includes: etching the dielectric layer to the substrate layer, and forming a first opening and a second opening in the dielectric layer; along the first The opening and the second opening simultaneously etch the substrate layer to form isolation trenches and contact holes penetrating through the substrate layer, respectively; and form the first trenches and fill the isolation trenches and cover the contact holes and the first holes.
- a characteristic size of the isolation structure is smaller than a characteristic size of the first contact portion.
- the step of forming an isolation structure penetrating the substrate layer further includes: forming an isolation trench penetrating the substrate layer, the isolation trench being located at an edge of the pad region and surrounding the pad region; forming An isolation material filling the isolation trench.
- the minimum distance between the projection of the pad on the substrate layer and the isolation structure is 0.5 ⁇ m.
- the isolation structure includes more than two isolation rings nested in a set.
- the distance between adjacent isolation rings is 0.8 ⁇ m to 1.2 ⁇ m.
- a second contact portion penetrating the storage layer is formed in the storage layer, and the first contact portion is connected to the second contact portion.
- a second substrate is further bonded to the surface of the memory layer of the first substrate; a memory cell and a memory circuit structure connected to the memory unit are formed in the memory layer; and a peripheral circuit in the second substrate is formed.
- An electrical connection is formed with a memory circuit structure in the memory layer.
- An isolation structure is formed in the substrate layer of the memory structure of the present invention.
- the substrate layer under the pad is isolated from the surroundings and no current is formed. . Therefore, the parasitic capacitance between the bonding pad and the substrate layer is reduced, thereby improving the performance of the memory structure. Further, since the parasitic capacitance between the pad and the substrate layer is small, a dielectric layer with a lower thickness can be used, saving process costs and reducing process difficulty.
- an isolation structure is formed in the substrate layer as a physical isolation structure between a substrate layer under a pad and a substrate layer in a device region, so as to reduce parasitics formed between the pad and the substrate layer. Capacitor, which can improve the performance of the memory structure. Further, the isolation structure may be formed at the same time in the process of forming the first contact portion penetrating the substrate layer, without adding a process step.
- FIG. 1 to 7 are schematic structural diagrams of a memory structure formation process according to a specific embodiment of the present invention.
- FIGS. 8 to 10 are schematic top views of a spacer ring and a bonding pad in a storage structure according to a specific embodiment of the present invention.
- FIG. 1 to FIG. 7 are schematic structural diagrams of a memory structure formation process according to a specific embodiment of the present invention.
- a first substrate 100 which includes a substrate layer 101 and a storage layer 102.
- the substrate layer 101 has a first surface 11 and a second surface 12 opposite to each other.
- the storage layer 102 is located on the substrate layer 101.
- the first substrate 100 includes a pad region I; a dielectric layer 103 is formed on the second surface 12 of the substrate layer 101.
- the first substrate 100 is in an inverted state.
- the first surface 11 of the substrate layer 101 is a lower surface of the substrate layer 101
- the second surface 12 is an upper surface of the substrate layer 101.
- the storage layer 102 covers the first surface 11 of the substrate layer 101.
- the corresponding storage layer 102 is also located below the substrate layer 101.
- the substrate layer 101 is a semiconductor material layer, and may be a single crystal silicon wafer, a semiconductor epitaxial layer including a single crystal silicon wafer and a wafer surface, or a silicon-on-insulator substrate.
- the substrate layer 101 includes a single crystal silicon wafer and a single crystal silicon epitaxial layer on the surface of the single crystal silicon substrate.
- the surface of the single crystal silicon epitaxial layer is a first surface 11.
- the other surface of the single crystal silicon wafer is the second surface 12.
- the memory layer 102 includes an insulating layer, a memory cell formed in the insulating layer, and a memory circuit connected to the memory cell.
- a 3D NAND memory cell is formed in the storage layer 102.
- a second contact portion 121 is also formed in the storage layer 102.
- the second contact portion 121 may be an interconnection structure for connecting a memory cell, or may be an interconnection structure for connecting a circuit in the substrate layer 101 and the second substrate 200.
- FIG. 1 a portion of the second contact portion 121 in the memory layer 102 is shown as a schematic illustration.
- the pad area I of the first substrate 100 is used to form a circuit connection structure for connecting layers of circuits, and subsequently, pads used to connect external circuits and internal circuits are formed on the pad area I. Therefore, the pad area I A functional region such as a doped well is generally not formed in the inner substrate layer 101, and a second contact portion 121 is formed in the storage layer 102 in the pad region I for passing through the pad region I formed later The first contact portion of the substrate layer 101 connects the circuits in the memory layer 102.
- the first substrate 100 further includes a device region II other than the pad region I.
- the device region II of the first substrate 100 is used to form a semiconductor device, and the pad region I is generally located at the periphery of the device region II.
- a doped well is formed in the substrate layer 101 in the device region II, and a memory cell is formed in the memory layer 102 in the device region II.
- the A current needs to pass through the substrate layer 101 of the device region II.
- the dielectric layer 103 may be formed on the second surface 12 of the substrate layer 101 by a deposition process.
- the dielectric layer 103 serves as a passivation layer covering the second surface 12 of the substrate layer 101 and is used to protect the second surface 12 of the substrate layer 101.
- the material of the dielectric layer 103 may be an insulating dielectric material such as TEOS, silicon nitride, silicon oxynitride, or silicon oxide.
- the dielectric layer 103 may be a single-layer structure or a multilayer stack structure.
- the dielectric layer 103 may be formed by various deposition processes such as a chemical vapor deposition process, a spin coating process, and an atomic layer deposition process.
- the other surface of the storage layer 102 opposite to the substrate layer 101 is also bonded to a second substrate 200.
- Peripheral circuits are formed in the second substrate 200.
- the second substrate 200 is located on the surface of the memory layer 102.
- Electrical circuits are formed between the peripheral circuits in the second substrate 200 and the memory circuits in the memory layer 102. connection.
- the surface of the second substrate 200 facing the storage layer 102 exposes the surface of the connection portion of the peripheral circuit
- the surface of the storage layer 102 exposes the surface of the connection portion of the storage circuit. The two are bonded to form Electrical connection.
- the dielectric layer 103 is etched to the second surface 12 of the substrate layer 101, and a first opening 131 and a second opening 132 are formed in the dielectric layer 103.
- the method for forming the first opening 131 and the second opening 132 includes forming a photoresist layer on the surface of the dielectric layer 103, and exposing and developing the photoresist layer with a photomask to form a pattern.
- the first opening 131 is used to define a position and size of an isolation structure to be formed later, and the second opening 132 is used to define a position and size of a first contact portion to be formed through the substrate layer 101.
- the same photomask is used for the photolithography process to form a patterned photoresist layer on the dielectric layer 103, and then the dielectric layer 103 is etched to form the second opening 132 and the first opening 131 at the same time. No additional process steps are required for the isolation structure. .
- the first opening 131 is in the shape of an annular groove; the second opening 132 is in the shape of a hole, and the cross section may be circular, rectangular, or polygonal.
- the second opening 132 is not only formed in the dielectric layer above the pad region I, but also the second opening 132 is formed in the dielectric layer above the device region II.
- a first contact portion connecting the memory layer 102 is simultaneously formed in the pad region I and the device region II.
- the substrate layer 101 is simultaneously etched along the first opening 131 and the second opening 132 to form isolation trenches 113 and contact holes 114 penetrating through the substrate layer 101, respectively.
- a second contact portion 121 in the storage layer 102 is exposed at the bottom of the contact hole 114, and a first contact portion penetrating the substrate layer 101 and a second contact portion in the storage layer 102 are subsequently formed in the contact hole 114.
- the contact portion 121 is connected.
- the isolation trench 113 is located at an edge of the pad region I and is disposed around the pad region I.
- the isolation trench 113 is located at an interface between the pad region I and the device region II, and a side wall of the isolation trench 113 exposes a substrate layer in the pad region I 101. The other side wall exposes the substrate layer 101 in the device region II.
- the isolation trench 113 is completely located in the pad region I; in another specific implementation manner, the isolation trench 113 may also be completely located in the device region II, close to The pad area I.
- not only the isolation trench 113 is formed at the edge of the pad region I, but also the isolation trench may be formed between the contact holes 114 inside the pad region I at the same time.
- a characteristic size of the isolation trench 113 is smaller than a characteristic size of the contact hole 114.
- a characteristic dimension of the isolation trench 113 is a width of the isolation trench 113
- a cross section of the contact hole 114 is circular
- a characteristic dimension of the contact hole 114 is a cross section of the contact hole 114. diameter.
- the width of the isolation trench 113 is less than half of the aperture width of the contact hole 114 and greater than 20 nm, and the maximum width of the aperture of the contact hole 114 is 1500 nm.
- an insulating material layer 400 is formed to fill the isolation trench 113 (refer to FIG. 3), the first opening 131 (refer to FIG. 3), and an inner wall surface of the contact hole 114 and the second opening 132. .
- the material of the insulating material layer 400 may be an insulating dielectric material such as silicon oxide, silicon oxynitride, or silicon nitride.
- the insulating material layer 400 may be formed using a chemical vapor deposition process, an atomic layer deposition process, a plasma enhanced chemical vapor deposition process, and the like. Because the feature size of the isolation trench 113 is smaller than the feature size of the contact hole 114, when the insulation material layer 400 fills the isolation trench 113 and the first opening 131, the insulation material layer 400 only covers The inner wall surfaces of the contact hole 114 and the second opening 132 are described.
- the insulating material layer 400 also covers the surface of the dielectric layer 103.
- the insulating material layer 400 at the bottom of the contact hole 114 is removed to form an insulating sidewall 402 covering the sidewall of the contact hole 114 and the second opening 132, and filled in the isolation trench 113 and the first
- the insulating material layer in the opening 131 serves as the isolation structure 401.
- An anisotropic etching process is used to remove the insulating material layer 400 located at the bottom of the contact hole 114.
- the insulating material layer 400 at the bottom of the contact hole 114 is removed, the insulating material layer 400 on the surface of the dielectric layer 103 is also removed.
- a portion of the thickness of the insulating material layer 400 remains on the surface of the dielectric layer 103.
- the isolation structure 401 surrounds the substrate layer 101 in the pad region I, and a physical isolation is formed between the substrate layer 101 in the pad region I and the substrate layer 101 around the isolation structure 401.
- a current flows through the substrate layer 101 of the device region II during the working process of the memory structure, no current will pass through the substrate layer 101 of the pad region I due to the isolation of the isolation structure 401, which can reduce subsequent
- a parasitic capacitance is formed between the pads formed above the pad region I. Therefore, there is no need to reduce the parasitic capacitance by increasing the thickness of the dielectric layer 103, and the dielectric layer 103 can be kept at a lower thickness.
- the thickness of the dielectric layer 103 is greater than 100 nm, for example, it may be 100 nm to 500 nm. In a specific embodiment, the thickness of the dielectric layer 103 is 400 nm.
- the isolation structure 401 is simultaneously formed without adding additional process steps.
- a metal material layer filled with the contact hole 114 and the second opening 132 is formed, and the dielectric layer 103 is used as a stop layer for planarization to form the contact hole 114 (refer to FIG. 5).
- a metal post 403 in the second opening 132 (refer to FIG. 5).
- the insulating side wall 402 and the metal pillar 403 constitute a first contact portion.
- the material of the metal material layer may be a metal material such as W, Cu, Al, or Au.
- the metal material layer may be formed by a physical vapor deposition process, such as a sputtering process.
- a pad 701 is formed on a surface of the dielectric layer 103 on the pad region I, and a protective layer 703 covering the dielectric layer 103 and the pad 701 is formed.
- the protective layer 703 has an opening to expose the solder. Surface of pad 701.
- the bonding pad 701 When the bonding pad 701 is formed, it also includes forming an interconnection line 702 on the surface of the dielectric layer 103 on the device region II, and the interconnection line 702 is connected to the metal pillar 403 in the device region II.
- the minimum distance between the projection of the bonding pad 701 on the substrate layer 101 and the isolation structure 401 is 0.5 ⁇ m, so that both the bonding pad 701 and the isolation structure 401 have sufficient process windows to ensure that they are located on the bonding pad 701.
- the underlying substrate layers 101 are all surrounded by the isolation structure 401.
- the pad 701 is generally a rectangle with a side length of 70 ⁇ m to 80 ⁇ m, and has a large area, which is likely to cause a large parasitic capacitance.
- the interconnection line 702 is formed at the same time as the bonding pad 701. Specifically, a metal layer covering the dielectric layer 103 and the first contact portion is formed, and the metal layer is patterned and etched to form the bonding pad 701 and the interconnection. Line 702, and then forming a protective layer 703 covering the dielectric layer 103, the interconnect line 702, and the solder pad 701, and etching the protective layer 703 to expose the surface of the solder pad 701, so that the solder pad can be subsequently The 701 is connected to an external circuit.
- the materials of the interconnection lines 702 and the bonding pads 701 may be metals such as Al, Cu, Au, or Ag.
- the size of the interconnection line 702 is small.
- the width of the interconnection line 702 is 600 nm, which does not generate a large parasitic capacitance and has a small impact on the performance of the memory.
- the width of the interconnection line 702 may also be 500 nm to 700 nm.
- an isolation structure 401 is formed in the substrate layer 101 as a physical isolation structure between the substrate layer 101 under the bonding pad 701 and the substrate layer 102 in the device region II.
- a current is formed inside the bottom layer 101, so the parasitic capacitance between the bonding pad 701 and the substrate layer 101 is reduced, thereby improving the performance of the memory structure. Therefore, the low thickness of the dielectric layer 103 can also keep the parasitic capacitance between the pad 701 and the substrate layer 101 small.
- the thickness of the dielectric layer 103 may be 400 nm. In other specific implementations, the thickness of the dielectric layer 103 may be 300 nm to 500 nm.
- the thickness of the dielectric layer 103 is relatively low, so that the depth and width of the contact hole 114 and the isolation trench 113 are relatively low, which can reduce the process difficulty.
- the substrate layer 101 is etched to form an isolation trench, and the isolation trench is filled with an isolation material as an isolation structure.
- a dielectric layer 103 is formed on the second surface 12 of the substrate layer 101, the dielectric layer 103 and the substrate layer 101 are etched to form a contact hole penetrating the dielectric layer 103 and the substrate layer 101, and an inner wall surface of the contact hole is formed.
- the isolation structure 401 is a single isolation ring.
- FIG. 8 is a schematic top view of the isolation structure 401 and the bonding pad 701.
- the pad 701 is a rectangle, the shape of the area surrounded by the isolation structure 401 is consistent with the shape of the pad 701, and the distance between the isolation structure 401 and the positions of the pad 701 is equal.
- the isolation structure 401 may also have other shapes such as a circular ring shape.
- the isolation structure may include two or more isolation rings that are nested.
- two isolation rings of the isolation structure are an isolation ring 401a and an isolation ring 401b, and the isolation ring 401a and the isolation ring 401b are nested.
- the distances between the isolation ring 401a and the isolation ring 401b are equal at all places, so that the isolation effect is the same everywhere.
- the isolation ring 401a may be located in the pad area I, and the isolation ring 401b may be located in the device area II; or the isolation ring 401a and the isolation ring 401b may be located in the device area II or both
- the pad area I is described. Isolation is performed by the substrate layer 101 in the area surrounded by two isolation rings, which can improve the isolation effect.
- a distance between the isolation ring 401a and the isolation ring 401b may be 0.8 ⁇ m to 1.2 ⁇ m. In other specific implementation manners, the distance between each position of the isolation ring 401a and the isolation ring 401b may also vary with different positions.
- the isolation structure includes three isolation rings, namely an isolation ring 401 a, an isolation ring 401 b, and an isolation ring 401 c.
- d1 d2; in other specific embodiments, d1 and d2 may also be not equal.
- An isolation structure with multiple isolation rings can further improve the isolation effect and minimize the parasitic capacitance between the bonding pad 701 and the substrate layer 101.
- a specific embodiment of the present invention also provides a storage structure formed by the above method.
- FIG. 7 is a schematic structural diagram of a storage structure according to an embodiment of the present invention.
- the storage structure includes a first substrate 100, which includes a substrate layer 101 and a storage layer 102.
- the substrate layer 101 has a first surface 11 and a second surface 12, and the storage layer 102 is opposite.
- the first substrate 100 Located on the first surface 11 of the substrate layer 101, the first substrate 100 includes a pad region I; a dielectric layer 103 on the second surface 12 of the substrate layer 101; a pad 701 on the solder A surface of the dielectric layer 103 on the pad region I; an isolation structure 401 that penetrates the substrate layer 101 and is located at the edge of the pad region I and surrounds the substrate layer 101 in the pad region I to isolate the solder The substrate layer 101 in the pad region I and the substrate layer 101 around the isolation structure 401.
- the substrate layer 101 is a semiconductor material layer, and may be a single crystal silicon wafer, a semiconductor epitaxial layer including a single crystal silicon wafer and a wafer surface, or a silicon-on-insulator substrate.
- the substrate layer 101 includes a single crystal silicon wafer and a single crystal silicon epitaxial layer on the surface of the single crystal silicon substrate.
- the surface of the single crystal silicon epitaxial layer is a first surface 11.
- the other surface of the single crystal silicon wafer is the second surface 12.
- the first substrate 100 is in an inverted state.
- the first surface 11 of the substrate layer 101 is a lower surface of the substrate layer 101
- the second surface 12 is an upper surface of the substrate layer 101.
- the storage layer 102 covers the first surface 11 of the substrate layer 101.
- the corresponding storage layer 102 is also located below the substrate layer 101.
- the memory layer 102 includes an insulating layer, a memory cell formed in the insulating layer, and a memory circuit connected to the memory cell.
- a 3D NAND memory cell is formed in the storage layer 102.
- a second contact portion 121 is also formed in the storage layer 102.
- the second contact portion 121 may be an interconnection structure for connecting a memory cell, or may be an interconnection structure for connecting a circuit in the substrate layer 101 and the second substrate 200.
- the other surface of the storage layer 102 opposite to the substrate layer 101 is also bonded to a second substrate 200, and peripheral circuits are formed in the second substrate 200;
- the substrate 200 is located on the surface of the memory layer 102, and an electrical connection is formed between the peripheral circuits in the second substrate 200 and the memory circuits in the memory layer 102.
- the surface of the second substrate 200 facing the storage layer 102 exposes the surface of the connection portion of the peripheral circuit, and the surface of the storage layer 102 exposes the surface of the connection portion of the storage circuit.
- the two are bonded to form Electrical connection.
- the first substrate 100 further includes a device region II.
- the device region II is used to form a semiconductor device.
- the pad region I is generally located on the periphery of the device region II.
- a doped well is formed in the substrate layer 101 in the device region II, and a memory cell is formed in the memory layer 102 in the device region II.
- the A current needs to pass through the substrate layer 101 of the device region II.
- the pad area I of the first substrate 100 is used to form a circuit connection structure for connecting layers of circuits, and subsequently, pads used to connect external circuits and internal circuits are formed on the pad area I.
- the pad area I A functional region such as a doped well is generally not formed in the inner substrate layer 101, and a second contact portion 121 is formed in the storage layer 102 in the pad region I for passing through the pad region I formed later
- the first contact portion of the substrate layer 101 connects the circuits in the memory layer 102.
- FIG. 1 a portion of the second contact portion 121 in the memory layer 102 is shown as a schematic illustration.
- the dielectric layer 103 serves as a passivation layer on the second surface 12 of the substrate layer 101 and is used to protect the second surface 12 of the substrate layer 101.
- the material of the dielectric layer 103 may be an insulating dielectric material such as TEOS, silicon nitride, silicon oxynitride, or silicon oxide.
- the dielectric layer 103 may be a single-layer structure or a multilayer stack structure.
- the dielectric layer 103 may be formed by various deposition processes such as a chemical vapor deposition process, a spin coating process, and an atomic layer deposition process. In this specific implementation manner, the thickness of the dielectric layer 103 is greater than 100 nm, and may be, for example, 100 nm to 500 nm. In a specific embodiment, the thickness of the dielectric layer 103 is 400 nm.
- the isolation structure 401 includes an isolation trench penetrating the substrate layer 101 and an isolation material filling the isolation trench.
- the isolation material may be an insulating dielectric material such as silicon oxide, silicon oxynitride, or silicon nitride.
- the isolation structure 401 further penetrates the dielectric layer 103.
- the isolation structure 401 may also be located only in the substrate layer 101.
- the isolation structure 401 is located at an edge of the pad region I and is disposed around the pad region I. In this specific implementation manner, the isolation structure 401 is located at an interface between the pad region I and the device region II, and a side wall of the isolation structure 401 is in contact with the substrate layer 101 in the pad region I. The other side wall is in contact with the substrate layer 101 in the device region II. In another specific embodiment, the isolation structure 401 is completely located in the pad region I. In another specific embodiment, the isolation structure 401 may also be completely located in the device region II, close to the device region II. Pad area I. In another specific embodiment, not only the isolation structure 401 is formed on the edge of the pad region I, but also the isolation structure may be formed between the metal pillars 403 of the first contact portion inside the pad region I at the same time.
- the isolation structure 401 surrounds the substrate layer 101 in the pad region I, and a physical isolation is formed between the substrate layer 101 in the pad region I and the substrate layer 101 around the isolation structure 401.
- a current passes through the substrate layer 101 in the device region II. Due to the isolation effect of the isolation structure 401, no current can pass through in the substrate layer 101 in the pad region I, so the substrate layer can be reduced.
- the parasitic capacitance formed between 101 and the bonding pad 701 above the bonding pad region I does not need to be reduced by increasing the thickness of the dielectric layer 103.
- the minimum distance between the projection of the bonding pad 701 on the substrate layer 101 and the isolation structure 401 is 0.5 ⁇ m, so that both the bonding pad 701 and the isolation structure 401 have sufficient process windows to ensure that they are located on the bonding pad 701.
- the underlying substrate layers 101 are all surrounded by the isolation structure 401.
- the bonding pad 701 is generally a rectangle with a side length between 70 ⁇ m and 80 ⁇ m, and has a large area, which easily causes a large parasitic capacitance. In the specific embodiment of the present invention, the bonding pad 701 is isolated by the isolation structure 401. No current flows through the underlying substrate layer 101, thereby reducing the parasitic capacitance formed between the bonding pad 701 and the substrate layer 101.
- the storage structure further includes a first contact portion penetrating the dielectric layer 103 and the substrate layer 101.
- the first contact portion includes a metal pillar 403 and an insulating sidewall 402 located on a sidewall surface of the metal pillar 403.
- the material of the metal pillar 403 may be a metal material such as W, Cu, Al, or Au.
- the metal pillar 403 is connected to the second contact portion 121 to achieve connection with a memory circuit in the memory layer 102.
- the first contact portion is formed in both the device region II and the pad region I.
- a characteristic size of the isolation structure 401 is smaller than a characteristic size of the first contact portion.
- the characteristic size of the isolation structure 401 is the width of the isolation structure 401
- the cross-section of the first contact portion is circular
- the characteristic size of the first contact portion is the lateral size of the first contact portion.
- Section diameter In a specific embodiment, the width of the isolation structure 401 is less than half of the cross-sectional diameter of the first contact portion and greater than 20 nm, and the maximum diameter of the cross-section of the first contact portion is 1500 nm.
- the isolation structure 401 and the first contact portion both penetrate the dielectric layer 103 and the substrate layer 101, the dielectric trench 103 and the substrate layer 101 are etched to form an isolation trench and a contact hole at the same time.
- an isolation structure 401 filling the isolation trench is formed without adding additional process steps.
- An interconnection line 702 is further formed on the surface of the dielectric layer 103 on the device region II, and is connected to the first contact portion in the device region II.
- the materials of the interconnection lines 702 and the bonding pads 701 may be metals such as Al, Cu, Au, or Ag.
- the characteristic size of the interconnection line 702 is small. In a specific embodiment of the present invention, the width of the interconnection line 702 is 600 nm, which does not cause a large parasitic capacitance and has a small impact on the performance of the memory. In other specific implementations, the width of the interconnection line 702 may also be 500 nm to 700 nm.
- the surface of the dielectric layer 103 further includes a protective layer 703 covering the dielectric layer 103, the interconnection line 702, and the solder pad 701.
- the protective layer 703 has an opening to expose the surface of the solder pad 701, so that the solder pad can be subsequently
- the 701 is connected to an external circuit.
- an isolation structure 401 is formed in the substrate layer 101 as a physical isolation structure between the substrate layer 101 under the bonding pad 701 and the substrate layer 101 under the device region II, and the substrate layer under the bonding pad 701 101 is isolated from the surroundings and no current is formed. Therefore, the parasitic capacitance between the bonding pad 701 and the substrate layer 101 is reduced, thereby improving the performance of the memory structure. Further, since the parasitic capacitance between the bonding pad 701 and the substrate layer 101 is reduced by the isolation structure 401, a lower thickness dielectric layer 103 can be used to further make the first contact through the dielectric layer 103 and the substrate layer 101. The depth and width of the external structure and the isolation structure 401 are relatively low, which can reduce the process difficulty.
- the isolation structure 401 is a single isolation ring.
- FIG. 8 is a schematic top view of the isolation structure 401 and the bonding pad 701.
- the pad 701 is a rectangle, the shape of the area surrounded by the isolation structure 401 is consistent with the shape of the pad 701, and the distance between the isolation structure 401 and the positions of the pad 701 is equal.
- the isolation structure 401 may also have other shapes such as a circular ring shape.
- the isolation structure may include two or more isolation rings that are nested.
- two isolation rings of the isolation structure are an isolation ring 401a and an isolation ring 401b, and the isolation ring 401a and the isolation ring 401b are nested.
- the distances between the isolation ring 401a and the isolation ring 401b are equal at all places, so that the isolation effect is the same everywhere.
- the isolation ring 401a may be located in the pad area I, and the isolation ring 401b may be located in the device area II; or the isolation ring 401a and the isolation ring 401b may be located in the device area II or both
- the pad area I is described. Isolation is performed by the substrate layer 101 in the area surrounded by two isolation rings, which can improve the isolation effect.
- the distance between the isolation ring 401a and the isolation ring 401b may be 0.8 ⁇ m to 1.2 ⁇ m. In other specific implementation manners, the distance between the isolation ring 401a and the isolation ring 401b at each position may be changed correspondingly according to different positions.
- the substrate layer 101 in the process of forming the isolation structure, can be etched to form two nested annular isolation trenches at the same time, and an insulating material is filled in the annular isolation trenches to form the isolation. Ring 401a and isolation ring 401b.
- the isolation structure includes three isolation rings, namely an isolation ring 401 a, an isolation ring 401 b, and an isolation ring 401 c.
- d1 d2; in other specific embodiments, d1 and d2 may also be not equal.
- An isolation structure with multiple isolation rings can further improve the isolation effect and minimize the parasitic capacitance between the bonding pad 701 and the substrate layer 101.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (20)
- 一种存储器结构,其特征在于,包括:第一基底,包括:衬底层和存储层,所述衬底层具有相对的第一表面和第二表面,所述存储层位于所述衬底层的第一表面上,所述第一基底包括焊垫区域;介质层,位于所述衬底层的第二表面上;焊垫,位于所述焊垫区域上方的介质层表面;隔离结构,贯穿所述衬底层,位于所述焊垫区域边缘,包围所述焊垫区域内的衬底层,用于隔离所述焊垫区域内的衬底层与所述隔离结构外围的衬底层。
- 根据权利要求1所述的存储器结构,其特征在于,还包括:第一接触部,所述第一接触部贯穿所述介质层和焊垫区域的衬底层;所述焊垫连接至所述第一接触部。
- 根据权利要求2所述的存储器结构,其特征在于,所述第一接触部包括金属柱以及位于所述金属柱侧壁表面的绝缘侧墙。
- 根据权利要求2所述的存储器结构,其特征在于,所述隔离结构的特征尺寸小于所述第一接触部的特征尺寸。
- 根据权利要求1所述的存储器结构,其特征在于,所述隔离结构包括贯穿所述衬底层的隔离沟槽和填充满所述隔离沟槽的隔离材料。
- 根据权利要求1所述的存储器结构,其特征在于,所述焊垫在衬底层上的投影与所述隔离结构之间的最小距离为0.5μm
- 根据权利要求1所述的存储器结构,其特征在于,所述隔离结构包括两个以上套嵌设置的隔离环。
- 根据权利要求7所述的存储器结构,其特征在于,相邻隔离环之间的距离为0.8μm~1.2μm。
- 根据权利要求1所述的存储器结构,其特征在于,所述存储层内形成有第二接触部,所述第一接触部连接至所述第二接触部。
- 根据权利要求1所述的存储器结构,其特征在于,还包括:第二基底,所述第二基底内形成有外围电路;所述第二基底键合于所述存储层表面,所 述存储层内形成有存储单元和连接所述存储单元的存储电路结构,所述第二基底内的外围电路与所述存储层内的存储电路结构之间形成电连接。
- 一种存储器结构的形成方法,其特征在于,包括:提供第一基底,包括衬底层和存储层,所述衬底层具有相对的第一表面和第二表面,所述存储层位于所述衬底层的第一表面上,所述第一基底包括焊垫区域;在所述衬底层的第二表面形成介质层;形成贯穿所述衬底层的隔离结构,所述隔离结构位于所述焊垫区域边缘,包围焊垫区域的衬底层,用于隔离所述焊垫区域内的衬底层与所述隔离结构外围的衬底层;在所述焊垫区域上方的介质层表面形成焊垫。
- 根据权利要求11所述的存储器结构的形成方法,其特征在于,还包括:形成贯穿所述介质层和焊垫区域的衬底层的第一接触部;所述焊垫连接至所述第一接触部。
- 根据权利要求12所述的存储器结构的形成方法,其特征在于,所述第一接触部和隔离结构的形成方法包括:刻蚀所述介质层至所述衬底层,在所述介质层内形成第一开口和第二开口;沿所述第一开口和所述第二开口同时刻蚀所述衬底层,分别形成贯穿所述衬底层的隔离沟槽和接触孔;形成填充满所述隔离沟槽、第一开口以及覆盖所述接触孔和第二开口内壁表面的绝缘材料层;去除位于所述接触孔底部的绝缘材料层;形成填充满所述接触孔和第二开口的金属材料层,并以所述介质层为停止层进行平坦化处理。
- 根据权利要求12所述的存储器结构的形成方法,其特征在于,所述隔离结构的特征尺寸小于所述第一接触部的特征尺寸。
- 根据权利要求11所述的存储器结构的形成方法,其特征在于,形成贯穿所述衬底层的隔离结构的步骤进一步包括:形成贯穿所述衬底层的隔离沟槽,所述隔离沟槽位于所述焊垫区域边缘,围绕所述焊垫区域;形成填充满所述隔离沟槽的隔离材料。
- 根据权利要求11所述的存储器结构的形成方法,其特征在于,所述焊垫在 衬底层上的投影与所述隔离结构之间的最小距离为0.5μm。
- 根据权利要求11所述的存储器结构的形成方法,其特征在于,所述隔离结构包括两个以上套嵌设置的隔离环。
- 根据权利要求17所述的存储器结构的形成方法,其特征在于,相邻隔离环之间的距离为0.8μm~1.2μm
- 根据权利要求11所述的存储器结构的形成方法,其特征在于,所述存储层内形成有贯穿所述存储层的第二接触部,所述第一接触部连接至所述第二接触部。
- 根据权利要求11所述的存储器结构的形成方法,其特征在于,所述第一基底的存储层表面还键合有第二基底;所述存储层内形成有存储单元和连接所述存储单元的存储电路结构,所述第二基底内的外围电路与所述存储层内的存储电路结构之间形成电连接。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111243473.0A CN114078954B (zh) | 2018-08-03 | 2018-08-03 | 存储器结构及其形成方法 |
CN201880096614.0A CN112567514B (zh) | 2018-08-03 | 2018-08-03 | 存储器结构及其形成方法 |
PCT/CN2018/098612 WO2020024282A1 (zh) | 2018-08-03 | 2018-08-03 | 存储器结构及其形成方法 |
PCT/CN2018/102496 WO2019042248A1 (zh) | 2017-08-31 | 2018-08-27 | 存储器结构及其形成方法 |
TW107131290A TWI704677B (zh) | 2018-08-03 | 2018-09-06 | 記憶體結構及其形成方法 |
US16/128,520 US10497708B1 (en) | 2018-08-03 | 2018-09-12 | Memory structure and forming method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2018/098612 WO2020024282A1 (zh) | 2018-08-03 | 2018-08-03 | 存储器结构及其形成方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/128,520 Continuation US10497708B1 (en) | 2018-08-03 | 2018-09-12 | Memory structure and forming method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2020024282A1 true WO2020024282A1 (zh) | 2020-02-06 |
Family
ID=68695788
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2018/098612 WO2020024282A1 (zh) | 2017-08-31 | 2018-08-03 | 存储器结构及其形成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10497708B1 (zh) |
CN (2) | CN112567514B (zh) |
TW (1) | TWI704677B (zh) |
WO (1) | WO2020024282A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018117102A (ja) * | 2017-01-20 | 2018-07-26 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置 |
CN111326511A (zh) * | 2020-03-09 | 2020-06-23 | 长江存储科技有限责任公司 | 存储器件及其制造方法 |
US11985808B2 (en) | 2021-07-05 | 2024-05-14 | Changxin Memory Technologies, Inc. | Memory and method for manufacturing same |
CN113594163B (zh) * | 2021-07-05 | 2023-12-19 | 长鑫存储技术有限公司 | 存储器及其制造方法 |
CN113725226B (zh) * | 2021-08-30 | 2024-04-16 | 长江存储科技有限责任公司 | 三维存储器及其制造方法 |
CN117649869A (zh) * | 2022-08-17 | 2024-03-05 | 长鑫存储技术有限公司 | 一种存储系统及电子设备 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104662660A (zh) * | 2012-08-30 | 2015-05-27 | 美光科技公司 | 具有通过控制栅极的连接件的存储器阵列 |
CN106057739A (zh) * | 2015-04-16 | 2016-10-26 | 台湾积体电路制造股份有限公司 | 用于防止浮置栅极变化的方法 |
CN106910746A (zh) * | 2017-03-08 | 2017-06-30 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法、封装方法 |
CN106920796A (zh) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法 |
US9960181B1 (en) * | 2017-04-17 | 2018-05-01 | Sandisk Technologies Llc | Three-dimensional memory device having contact via structures in overlapped terrace region and method of making thereof |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5637513A (en) * | 1994-07-08 | 1997-06-10 | Nec Corporation | Fabrication method of semiconductor device with SOI structure |
KR100268422B1 (ko) * | 1998-07-31 | 2000-10-16 | 윤종용 | 반도체 장치의 콘택 패드 및 그의 형성 방법 |
JP4439976B2 (ja) * | 2004-03-31 | 2010-03-24 | Necエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
KR101193740B1 (ko) * | 2004-06-30 | 2012-10-22 | 크리 인코포레이티드 | 발광 소자의 패키징을 위한 칩-규모 방법 및 칩 규모로 패키징된 발광 소자 |
JP4577687B2 (ja) * | 2005-03-17 | 2010-11-10 | エルピーダメモリ株式会社 | 半導体装置 |
US7745876B2 (en) * | 2007-02-21 | 2010-06-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices including gate patterns having step difference therebetween and a connection line disposed between the gate patterns and methods of fabricating the same |
US7882628B2 (en) * | 2007-05-30 | 2011-02-08 | Intel Corporation | Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias |
KR101419882B1 (ko) * | 2007-06-18 | 2014-08-14 | 삼성전자주식회사 | 패턴 형성 방법, 이를 이용한 전하 저장막 패턴 형성 방법,비휘발성 메모리 소자 및 이의 제조 방법. |
JP5302522B2 (ja) * | 2007-07-02 | 2013-10-02 | スパンション エルエルシー | 半導体装置及びその製造方法 |
KR101320518B1 (ko) * | 2007-10-24 | 2013-12-19 | 삼성전자주식회사 | 적층 레벨의 트랜지스터들을 갖는 집적 회로 반도체 소자및 그 제조방법 |
US20100224965A1 (en) * | 2009-03-09 | 2010-09-09 | Chien-Li Kuo | Through-silicon via structure and method for making the same |
US8263492B2 (en) * | 2009-04-29 | 2012-09-11 | International Business Machines Corporation | Through substrate vias |
JP5218497B2 (ja) * | 2009-12-04 | 2013-06-26 | 株式会社デンソー | 半導体装置およびその製造方法 |
KR101697573B1 (ko) * | 2010-11-29 | 2017-01-19 | 삼성전자 주식회사 | 반도체 장치, 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지 |
JP2012146861A (ja) * | 2011-01-13 | 2012-08-02 | Toshiba Corp | 半導体記憶装置 |
KR102076305B1 (ko) * | 2013-05-13 | 2020-04-02 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 형성 방법 |
US9236326B2 (en) * | 2014-04-25 | 2016-01-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and fabricating method thereof |
US9324632B2 (en) * | 2014-05-28 | 2016-04-26 | Globalfoundries Inc. | Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method |
CN105788632B (zh) * | 2016-02-26 | 2019-04-02 | 江苏时代全芯存储科技有限公司 | 记忆体电路 |
US20170317166A1 (en) * | 2016-04-29 | 2017-11-02 | Globalfoundries Inc. | Isolation structures for circuits sharing a substrate |
-
2018
- 2018-08-03 WO PCT/CN2018/098612 patent/WO2020024282A1/zh active Application Filing
- 2018-08-03 CN CN201880096614.0A patent/CN112567514B/zh active Active
- 2018-08-03 CN CN202111243473.0A patent/CN114078954B/zh active Active
- 2018-09-06 TW TW107131290A patent/TWI704677B/zh active
- 2018-09-12 US US16/128,520 patent/US10497708B1/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104662660A (zh) * | 2012-08-30 | 2015-05-27 | 美光科技公司 | 具有通过控制栅极的连接件的存储器阵列 |
CN106057739A (zh) * | 2015-04-16 | 2016-10-26 | 台湾积体电路制造股份有限公司 | 用于防止浮置栅极变化的方法 |
CN106910746A (zh) * | 2017-03-08 | 2017-06-30 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法、封装方法 |
CN106920796A (zh) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法 |
US9960181B1 (en) * | 2017-04-17 | 2018-05-01 | Sandisk Technologies Llc | Three-dimensional memory device having contact via structures in overlapped terrace region and method of making thereof |
Also Published As
Publication number | Publication date |
---|---|
CN112567514A (zh) | 2021-03-26 |
CN114078954A (zh) | 2022-02-22 |
TW202008566A (zh) | 2020-02-16 |
CN112567514B (zh) | 2021-11-12 |
US10497708B1 (en) | 2019-12-03 |
TWI704677B (zh) | 2020-09-11 |
CN114078954B (zh) | 2024-04-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2020024282A1 (zh) | 存储器结构及其形成方法 | |
US11043448B2 (en) | Semiconductor device with vertically separated openings and manufacturing method thereof | |
TWI505428B (zh) | 晶片封裝體及其形成方法 | |
US10943853B2 (en) | Semiconductor device and manufacturing method thereof | |
JP6034095B2 (ja) | 半導体装置およびその製造方法 | |
US8421238B2 (en) | Stacked semiconductor device with through via | |
JP5021992B2 (ja) | 半導体装置およびその製造方法 | |
JP5802515B2 (ja) | 半導体装置及びその製造方法 | |
TWI531053B (zh) | 半導體裝置與其形成方法與影像感測裝置 | |
JP2010205990A (ja) | 半導体装置及びその製造方法 | |
US20200075482A1 (en) | Semiconductor device and manufacturing method thereof | |
US10784163B2 (en) | Multi-wafer stacking structure and fabrication method thereof | |
CN104425453A (zh) | 3dic互连装置和方法 | |
KR20200047301A (ko) | 접합성 강화를 위한 패드 구조 | |
US11973006B2 (en) | Self-aligned contact openings for backside through substrate vias | |
TW201405676A (zh) | 晶片封裝體及其形成方法 | |
TWI670857B (zh) | 記憶體結構及其形成方法 | |
JP4389227B2 (ja) | 半導体装置の製造方法 | |
US11508619B2 (en) | Electrical connection structure and method of forming the same | |
TWI806077B (zh) | 積體電路晶片、積體電路封裝以及形成接墊結構的方法 | |
KR102076305B1 (ko) | 반도체 소자 및 그 형성 방법 | |
WO2022257313A1 (zh) | 半导体器件及其制造方法 | |
JP2015228473A (ja) | 半導体装置およびその製造方法 | |
WO2019042248A1 (zh) | 存储器结构及其形成方法 | |
TWI849617B (zh) | 晶片封裝體及其製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 18928569 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 18928569 Country of ref document: EP Kind code of ref document: A1 |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 06/07/2021) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 18928569 Country of ref document: EP Kind code of ref document: A1 |