TWI787842B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI787842B
TWI787842B TW110119223A TW110119223A TWI787842B TW I787842 B TWI787842 B TW I787842B TW 110119223 A TW110119223 A TW 110119223A TW 110119223 A TW110119223 A TW 110119223A TW I787842 B TWI787842 B TW I787842B
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insulating film
layer
pad
metal
semiconductor device
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TW110119223A
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TW202238919A (zh
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澤田元気
田上政由
飯島純
久米一平
吉田樹誉満
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日商鎧俠股份有限公司
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Abstract

實施方式提供可形成合適的墊的半導體裝置及其製造方法。 依一實施方式時，半導體裝置具備第1墊，其設於第1絕緣膜內，且包含設於前述第1絕緣膜之側面及下表面的第1層與隔著前述第1層而設於前述第1絕緣膜之側面及下表面的第2層。前述裝置進一步具備第2墊，其在設於前述第1絕緣膜上的第2絕緣膜內設於前述第1墊上，且包含設於前述第2絕緣膜之側面及上表面的第3層與隔著前述第3層而設於前述第2絕緣膜之側面及上表面的第4層。前述裝置進一步具備第1部分，其設於前述第1墊之上表面與前述第2絕緣膜的下表面之間或前述第2墊的下表面與前述第1絕緣膜之上表面之間，且包含與含於前述第1層或前述第3層的金屬元素相同的金屬元素。

Description

半導體裝置及其製造方法
本發明的實施方式涉及半導體裝置及其製造方法。 [關聯案] 本案主張以日本特願2020-208637號(申請日：2020年12月16日)為基礎申請案的優先權。本案參照此基礎申請案從而包含基礎申請案的全部的內容。
將一基板上的金屬墊及絕緣膜貼合於別的基板上的金屬墊及絕緣膜而製造半導體裝置的情況下，有時其中一基板上的金屬墊的表面曝露於另一基板上的絕緣膜的表面。此情況下，可能發生金屬原子(例如銅原子)從曝露於絕緣膜的表面的金屬墊的表面發生擴散等的問題。
實施方式提供可形成合適的墊的半導體裝置及其製造方法。 依一實施方式時，半導體裝置具備：第1絕緣膜；以及第1墊，其為設於前述第1絕緣膜內者，且包含設於前述第1絕緣膜之側面及下表面的第1層與隔著前述第1層而設於前述第1絕緣膜之側面及下表面的第2層。前述裝置進一步具備：第2絕緣膜，其設於前述第1絕緣膜上；以及第2墊，其在前述第2絕緣膜內設於前述第1墊上，且包含設於前述第2絕緣膜之側面及上表面的第3層與隔著前述第3層而設於前述第2絕緣膜之側面及上表面的第4層。前述裝置進一步具備第1部分，其設於前述第1墊之上表面與前述第2絕緣膜的下表面之間或前述第2墊的下表面與前述第1絕緣膜之上表面之間，且包含與含於前述第1層或前述第3層的金屬元素相同的金屬元素。
以下，就本發明的實施方式，參照圖式進行說明。圖1~圖20中，對相同的構成標注相同的符號，重複之說明省略。 (第1實施方式) 圖1為就第1實施方式的半導體裝置的構造進行繪示的剖面圖。圖1的半導體裝置為陣列晶片1與電路晶片2被貼合的3維記憶體。 陣列晶片1具備包含複數個記憶體單元的記憶體單元陣列11、記憶體單元陣列11上的絕緣膜12及記憶體單元陣列11下的層間絕緣膜13。絕緣膜12為例如矽氧化膜或矽氮化膜。層間絕緣膜13為例如矽氧化膜或包含矽氧化膜及其他絕緣膜的層積膜。層間絕緣膜13為第2絕緣膜之例。 電路晶片2設於陣列晶片1下。符號S表示陣列晶片1與電路晶片2的貼合面。電路晶片2具備層間絕緣膜14與層間絕緣膜14下的基板15。層間絕緣膜14為例如矽氧化膜或包含矽氧化膜及其他絕緣膜的層積膜。層間絕緣膜14為第1絕緣膜之例。基板15為例如矽基板等的半導體基板。 圖1示出平行於基板15的表面且彼此垂直的X方向及Y方向與垂直於基板15的表面的Z方向。本說明書中，將+Z方向視為上方向，將-Z方向視為下方向。-Z方向可與重力方向一致亦可不一致。 陣列晶片1以記憶體單元陣列11內的複數個電極層而具備複數個字線WL與源極線SL。圖1示出記憶體單元陣列11的階層構造部21。各字線WL經由接觸插塞22而與字佈線層23電連接。貫通複數個字線WL的各柱狀部CL經由導孔插塞24而與位元線BL，且與源極線SL電連接。源極線SL包含係半導體層的第1層SL1與係金屬層的第2層SL2。 電路晶片2具備複數個電晶體31。各電晶體31具備在基板15上隔著閘極絕緣膜而設的閘極電極32與設於基板15內的未圖示的源極擴散層及汲極擴散層。此外，電路晶片2具備設於此等電晶體31的閘極電極32、源極擴散層或汲極擴散層上的複數個接觸插塞33、設於此等接觸插塞33上且包含複數個佈線的佈線層34及設於佈線層34上且包含複數個佈線的佈線層35。 電路晶片2進一步具備設於佈線層35上且包含複數個佈線的佈線層36、設於佈線層36上的複數個導孔插塞37及設於此等導孔插塞37上的複數個金屬墊38。金屬墊38為例如包含Cu(銅)層的金屬層。金屬墊38為第1墊之例，導孔插塞37為第1插塞之例。電路晶片2作用為控制陣列晶片1的動作的控制電路(邏輯電路)。此控制電路由電晶體31等構成，並電連接於金屬墊38。 陣列晶片1具備設於金屬墊38上的複數個金屬墊41與設於金屬墊41上的複數個導孔插塞42。此外，陣列晶片1具備設於此等導孔插塞42上且包含複數個佈線的佈線層43與設於佈線層43上且複數個佈線的佈線層44。金屬墊41為例如包含Cu層的金屬層。金屬墊41為第2墊之例，導孔插塞42為第2插塞之例。上述的位元線BL包含於佈線層44中。上述的控制電路經由金屬墊41、38等電連接於記憶體單元陣列11，經由金屬墊41、38等控制記憶體單元陣列11的動作。 陣列晶片1進一步具備設於佈線層44上的複數個導孔插塞45、設於此等導孔插塞45上、絕緣膜12上的金屬墊46、設於金屬墊46上、絕緣膜12上的鈍化膜47。金屬墊46為例如包含Cu層的金屬層，並作用為圖1的半導體裝置的外部連接墊(接合墊)。鈍化膜47為例如矽氧化膜等的絕緣膜，並具有使金屬墊46之上表面曝露的開口部P。金屬墊46可經由此開口部P透過接合線、焊球、金屬凸塊等而連接於安裝基板、其他裝置。 圖2為就第1實施方式的柱狀部CL的構造進行繪示的剖面圖。 如示於圖2，記憶體單元陣列11具備交替層積於層間絕緣膜13(圖1)上的複數個字線WL與複數個絕緣層51。字線WL為例如W(鎢)層。絕緣層51為例如矽氧化膜。 柱狀部CL依序包含區塊絕緣膜52、電荷儲存層53、通道絕緣膜54、通道半導體層55及核心絕緣膜56。電荷儲存層53為例如矽氮化膜，並隔著區塊絕緣膜52形成於字線WL及絕緣層51之側面。電荷儲存層53亦可為多晶矽層等的半導體層。通道半導體層55為例如多晶矽層，並隔著通道絕緣膜54形成於電荷儲存層53之側面。區塊絕緣膜52、通道絕緣膜54及核心絕緣膜56為例如矽氧化膜或金屬絕緣膜。 圖3及圖4為就第1實施方式的半導體裝置的製造方法進行繪示的剖面圖。 圖3示出包含複數個陣列晶片1的陣列晶圓W1及包含複數個電路晶片2的電路晶圓W2。陣列晶圓W1亦稱為「記憶體晶圓」，電路晶圓W2亦稱為「CMOS晶圓」。 應留意圖3的陣列晶圓W1的朝向與圖1的陣列晶片1的朝向相反。在本實施方式，將陣列晶圓W1與電路晶圓W2予以貼合從而製造半導體裝置。圖3示出為了貼合而使朝向反轉前的陣列晶圓W1，圖1示出為了貼合而使朝向反轉以進行貼合及切割後的陣列晶片1。 圖3中，符號S1表示陣列晶圓W1之上表面，符號S2表示電路晶圓W2之上表面。應留意陣列晶圓W1具備設於絕緣膜12下的基板16。基板16為例如矽基板等的半導體基板。 在本實施方式，首先如示於圖3，在陣列晶圓W1的基板16上形成記憶體單元陣列11、絕緣膜12、層間絕緣膜13、階層構造部21、金屬墊41等，在電路晶圓W2的基板15上形成層間絕緣膜14、電晶體31、金屬墊38等。例如，在基板16上依序形成導孔插塞45、佈線層44、佈線層43、導孔插塞42及金屬墊41。此外，在基板15上依序形成接觸插塞33、佈線層34、佈線層35、佈線層36、導孔插塞37及金屬墊38。接著，如示於圖4，將陣列晶圓W1與電路晶圓W2透過機械壓力予以貼合。據此，層間絕緣膜13與層間絕緣膜14被黏合。接著，將陣列晶圓W1及電路晶圓W2以400℃進行退火。據此，金屬墊41與金屬墊38被接合。 之後，將基板15透過CMP(Chemical Mechanical Polishing)薄膜化，將基板16透過CMP除去後，將陣列晶圓W1及電路晶圓W2切斷為複數個晶片。以此方式製造圖1的半導體裝置。圖1示出包含金屬墊38及層間絕緣膜14的電路晶片2與包含分別配置於金屬墊38及層間絕緣膜14上的金屬墊41及層間絕緣膜13的陣列晶片1。另外，金屬墊46與鈍化膜47在例如基板15的薄膜化及基板16的除去的後被形成於絕緣膜12上。 另外，在本實施方式雖將陣列晶圓W1與電路晶圓W2予以貼合，惟亦可替而將陣列晶圓W1彼此予以貼合。先前參照圖1~圖4論述的內容、之後參照圖5~圖20論述的內容亦可適用於陣列晶圓W1彼此的貼合。 此外，圖1雖示出層間絕緣膜13與層間絕緣膜14的邊界面、金屬墊41與金屬墊38的邊界面，惟一般而言上述的退火後難以觀察到此等邊界面。然而，存在此等邊界面的位置可透過檢測例如金屬墊41之側面、金屬墊38之側面的傾斜、金屬墊41之側面與金屬墊38的偏位從而推定。 此外，本實施方式的半導體裝置可在切斷為複數個晶片後的圖1的狀態下成為涉及的對象，亦可在切斷為複數個晶片前的圖4的狀態下成為涉及的對象。圖1示出晶片的狀態的半導體裝置，圖4示出晶圓的狀態的半導體裝置。在本實施方式，從1個晶圓狀的半導體裝置(圖4)製造複數個晶片狀的半導體裝置(圖1)。 圖5為就第1實施方式的比較例的半導體裝置的構造進行繪示的剖面圖。圖6為就第1實施方式的半導體裝置的構造進行繪示的剖面圖。示於圖5的半導體裝置與示於圖6的半導體裝置的差異為例如金屬層61的有無。金屬層61為第1部分之例。 以下，參照圖6而說明本實施方式的半導體裝置的構造，之後參照圖5及圖6而比較本實施方式的半導體裝置與比較例的半導體裝置。 在本實施方式(圖6)，層間絕緣膜14包含在貼合面S下依序設置的絕緣膜14e、14d、14c、14b、14a，層間絕緣膜13包含在貼合面S上依序設置的絕緣膜13e、13d、13c、13b、13a。再者，金屬墊38包含依序設於層間絕緣膜14內的屏障金屬層38a與墊材層38b，金屬墊41包含依序設於層間絕緣膜13內的屏障金屬層41a與墊材層41b。本實施方式的半導體裝置進一步具備上述的金屬層61。 絕緣膜14a、14c、14e、13a、13c、13e為例如SiO 2膜(矽氧化膜)。絕緣膜14b、13b為例如SiN膜(矽氮化膜)。本實施方式的絕緣膜14b、13b例如分別在透過蝕刻將用於嵌入金屬墊38、41的孔形成於層間絕緣膜14、13內之際被作為蝕刻停止層而使用。絕緣膜14d、13d為例如SiCN膜(矽碳氮化膜)。本實施方式的絕緣膜14d、13d被例如為了防止金屬墊38、41內的Cu原子擴散至層間絕緣膜14、13內而形成。絕緣膜14d、13d分別為第3膜與第4膜之例。此外，絕緣膜14e、13e分別為第1膜與第2膜之例。 本實施方式的絕緣膜14e、13e為在將陣列晶圓W1與電路晶圓W2予以貼合前分別透過絕緣膜14d、13d的自然氧化而形成的自然氧化膜。為此，本實施方式的絕緣膜14e的下表面接於絕緣膜14d之上表面，本實施方式的絕緣膜13e之上表面接於絕緣膜13e的下表面。此外，本實施方式的絕緣膜14e之上表面接於絕緣膜13e的下表面。另外，絕緣膜14e、13e可因自然氧化以外的原因而形成，亦可透過例如層間絕緣膜14、13的表面的CMP、電漿處理而形成。 屏障金屬層38a形成於層間絕緣膜14之側面與下表面(底面)，並接於層間絕緣膜14之側面與下表面。墊材層38b隔著屏障金屬層38a形成於層間絕緣膜14之側面與下表面。同樣地，屏障金屬層41a形成於層間絕緣膜13之側面與上表面(底面)，並接於層間絕緣膜13之側面與上表面。墊材層41b隔著屏障金屬層41a形成於層間絕緣膜13之側面與上表面。屏障金屬層38a、41a分別為第1層與第3層之例。墊材層38b、41b分別為第2層與第4層之例。 屏障金屬層38a、41a為例如包含Ti(鈦)、Al(鋁)或Mn(錳)的金屬層，此處為Ti層。本實施方式的屏障金屬層38a、41a被例如為了防止金屬墊38、41內的Cu原子擴散至層間絕緣膜14、13內而形成。屏障金屬層38a、41a可為包含金屬元素與非金屬元素的金屬化合物層，例如可為金屬氧化膜、金屬氮化膜。此外，屏障金屬層38a、41a亦可為包含2種類以上的金屬元素的合金層。墊材層38b、41b為例如包含Cu的金屬層，此處為Cu層。墊材層38b、41b亦可為Cu層以外的金屬層。 本實施方式的金屬墊38與金屬墊41具有相同的平面形狀。此等平面形狀此處為具有延伸於X方向的二邊與延伸於Y方向的二邊的正方形或長方形。據此，本實施方式的金屬墊41的X方向的寬與Y方向的寬分別與金屬墊38的X方向的寬與Y方向的寬成為相同。 為此，若金屬墊41配置於金屬墊38的正上方時，變成金屬墊41的下表面僅與金屬墊38之上表面相接，且不接於金屬墊38以外的層之上表面。同樣地，變成金屬墊38的下表面僅與金屬墊41的下表面相接，且不接於金屬墊41以外的層的下表面。 然而，本實施方式的金屬墊41未配置於金屬墊38的正上方。為此，本實施方式的金屬墊41的下表面不僅與金屬墊38之上表面相接而設於層間絕緣膜14之上表面上。同樣地，本實施方式的金屬墊38之上表面不僅與金屬墊38的下表面相接而設於層間絕緣膜13的下表面下。並且，在本實施方式，金屬層61形成於金屬墊38之上表面與層間絕緣膜13的下表面之間及金屬墊41的下表面與層間絕緣膜14之上表面之間。 金屬層61包含例如與含於屏障金屬層38a、41a內的金屬元素相同的金屬元素。此金屬元素為例如Ti、Al、或Mn。金屬層61亦可進一步含有氧。在本實施方式，屏障金屬層38a、41a為Ti層，金屬層61為TiO x(氧化鈦)層。 本實施方式的金屬層61因屏障金屬層38a、41a內的Ti原子擴散至墊材層38b與絕緣膜13e的界面、墊材層41b與絕緣膜14e的界面從而被形成，被自對準地形成於此等界面的位置。本實施方式的金屬層61成為包含由來於屏障金屬層38a、41a的Ti原子與由來於絕緣膜14e、13e的O原子的TiO x層。據此，本實施方式的金屬層61的下表面接於絕緣膜14e之上表面、墊材層38b之上表面，本實施方式的金屬層61之上表面接於絕緣膜13e的下表面、墊材層41b的下表面。 另外，金屬層61亦可包含與僅含於屏障金屬層38a與屏障金屬層41a中的任一者的金屬元素相同的金屬元素。例如，僅屏障金屬層38a、41a之中的屏障金屬層38a包含Ti原子且由從屏障金屬層38a擴散的Ti原子而形成金屬層61的情況下，變成屏障金屬層38a與金屬層61包含Ti，屏障金屬層41a不含Ti。 此外，本實施方式的金屬層61為薄至無法稱之為層的程度、小的尺寸且亦可形成於金屬墊38與層間絕緣膜13之間、金屬墊41與層間絕緣膜14之間。形成本實施方式的金屬層61的過程的進一步的細節方面後述之。 接著，參照圖5及圖6，比較本實施方式的半導體裝置與比較例的半導體裝置。 在比較例(圖5)，屏障金屬層38a、41a非Ti層而為Ta(鉭)層。Ta原子比Ti原子難擴散。為此，在比較例，在金屬墊38與層間絕緣膜13之間、在金屬墊41與層間絕緣膜14之間未形成金屬層61。 此外，在比較例，絕緣膜14e、13e(SiO 2膜)如同本實施方式般形成於絕緣膜14d、13d(SiCN膜)間。SiO 2膜比起SiCN膜，防止Cu原子的擴散的作用小。為此，在比較例，金屬墊38、41內的Cu原子經由絕緣膜14e、13e擴散至層間絕緣膜14、13內。Cu原子的擴散可能在例如製造半導體裝置之際的退火程序發生。擴散至層間絕緣膜14、13內的Cu原子成為例如在金屬墊38彼此之間、金屬墊41彼此之間、金屬墊38與金屬墊41之間等發生漏電流的原因。 往層間絕緣膜14、13內的Cu原子的擴散只要金屬墊38、41具有相同的平面形狀且金屬墊41配置於金屬墊38的正上方則幾乎不會成為問題。原因在於，此情況下，變成金屬墊41的下表面僅接於金屬墊38之上表面，金屬墊38之上表面亦僅接於金屬墊41的下表面。 然而，在將陣列晶圓W1與電路晶圓W2予以貼合之際，有時在金屬墊38與金屬墊41的位置對準方面產生誤差。此情況下，變成金屬墊41未配置於金屬墊38的正上方，且金屬墊41的下表面亦接於層間絕緣膜14之上表面，金屬墊38之上表面亦接於層間絕緣膜13的下表面。 此情況下，亦只要層間絕緣膜14之上表面被以絕緣膜14d(SiCN膜)形成且層間絕緣膜13的下表面被以絕緣膜13d(SiCN膜)形成，即可抑制往層間絕緣膜14、13內的Cu原子的擴散。原因在於，SiCN膜防止Cu原子的擴散的作用大。然而，因自然氧化等使得層間絕緣膜14、13包含絕緣膜14e、13e(SiO 2膜)時，金屬墊38、41內的Cu原子會經由絕緣膜14e、13e擴散至層間絕緣膜14、13內。 另一方面，在本實施方式(圖6)，屏障金屬層38a、41a為Ti層。Ti原子比Ta原子容易擴散。為此，在本實施方式，在金屬墊38與層間絕緣膜13之間、在金屬墊41與層間絕緣膜14之間形成金屬層61。據此，依本實施方式時，金屬墊41未配置於金屬墊38的正上方且因自然氧化等使得層間絕緣膜14、13包含絕緣膜14e、13e(SiO 2膜)的情況下，仍可透過金屬層61抑制從金屬墊38、41往層間絕緣膜14、13的Cu原子的擴散。另外，導致金屬層61的Ti原子的擴散在例如製造半導體裝置之際的退火程序發生。 在屏障金屬層38a、41a方面使用Ti層具有在TiO x層(金屬層61)的屏障性高如此之優點、形成Ti層之成本便宜即可如此之優點。另外，如此的屏障效果亦可在使用Al層形成AlO x層的情況、使用Mn層形成MnO x層的情況獲得。 另外，本實施方式的金屬墊41不在金屬墊38的正上方的構造可透過金屬墊38與金屬墊41的位置對準的誤差而產生，亦可在製造半導體裝置之際有意地予以產生。 圖7~圖11為就第1實施方式的半導體裝置的製造方法進行繪示的剖面圖。示於圖7~圖11的方法相當於示於圖3及圖4的方法的具體例。 首先，將陣列晶圓W1及電路晶圓W2加工為示於圖7的構造。具體而言，在基板16(圖3參照)之上方形成絕緣膜13a，在絕緣膜13a內形成導孔插塞42，在絕緣膜13a及導孔插塞42上依序形成絕緣膜13b、13c、13d，在絕緣膜13b、13c、13d內依序形成屏障金屬層41a與墊材層41b。同樣地，在基板15(圖3參照)之上方形成絕緣膜14a，在絕緣膜14a內形成導孔插塞37，在絕緣膜14a及導孔插塞37上依序形成絕緣膜14b、14c、14d，在絕緣膜14b、14c、14d內依序形成屏障金屬層38a與墊材層38b。其結果，分別在層間絕緣膜13、14內形成金屬墊41、38。 接著，在絕緣膜13d、14d的表面，透過氧化分別形成絕緣膜13e、14e(圖8)。絕緣膜13e、14e因例如自然氧化而被形成。 接著，以金屬墊41被配置於金屬墊38上且層間絕緣膜13被配置於層間絕緣膜14上的方式，透過機械壓力將陣列晶圓W1與電路晶圓W2予以貼合(圖9)。據此，層間絕緣膜13與層間絕緣膜14被黏合。在圖9，於金屬墊38與金屬墊41的位置對準產生誤差，金屬墊38之上表面的一部分與金屬墊41的下表面的一部分相接。 接著，將陣列晶圓W1及電路晶圓W2退火(圖10)。據此，金屬墊41與金屬墊38被接合。圖10進一步示出墊材層38b、41b內的晶粒間的晶界α與沿著晶界α、貼合面S擴散的Ti原子群β。在本實施方式，透過示於圖10的程序的退火，使得Ti原子從屏障金屬層38a、41a擴散。 其結果，屏障金屬層38a、41a內的Ti原子擴散至墊材層38b與絕緣膜13e的界面、墊材層41b與絕緣膜14e的界面，在金屬層61被自對準地形成於此等界面的位置(圖11)。具體而言，從屏障金屬層38a、41a擴散至此等界面的Ti原子與絕緣膜14e、13e內的O原子反應，作為金屬層61形成TiO x層。據此，依本實施方式時，可透過金屬層61抑制從金屬墊38、41往層間絕緣膜14、13的Cu原子的擴散。 以此方式製造圖6的半導體裝置。之後，將基板15透過CMP薄膜化，將基板16透過CMP除去後，將陣列晶圓W1及電路晶圓W2切斷為複數個晶片。以此方式製造圖1的半導體裝置。 如以上，本實施方式的半導體裝置在金屬墊38之上表面與層間絕緣膜13的下表面之間、在金屬墊41的下表面與層間絕緣膜14之上表面之間具備含有與含於屏障金屬層38a、41a的金屬元素相同的金屬元素的金屬層61。據此，依本實施方式時，可形成可抑制從墊材層38b、41b往絕緣膜14e、13e的金屬原子(例如Cu原子)的擴散等合適的金屬墊38、41。 (第2實施方式) 圖12為就第2實施方式的半導體裝置的構造進行繪示的剖面圖。 本實施方式的層間絕緣膜13、14不具備絕緣膜13d、14d(SiCN膜)，其結果絕緣膜13e、14e(SiO 2膜)亦不具備。在本實施方式，層間絕緣膜13內的絕緣膜13c(SiO 2膜)與層間絕緣膜14內的絕緣膜14c(SiO 2膜)在貼合面S彼此相接。 本實施方式的半導體裝置亦具備金屬層61。本實施方式的金屬層61方面，因從屏障金屬層38a、41a擴散的Ti原子與絕緣膜14c、13c內的O原子產生反應而被形成。 依本實施方式時，可省略形成絕緣膜13d、14d的工夫。此外，依本實施方式時，在層間絕緣膜13、14的表面附近不存在絕緣膜13d、14d，因而可易於透過CMP將層間絕緣膜13、14的表面平坦化。另一方面，依第1實施方式時，不僅可透過金屬層61抑制Cu原子的擴散，透過絕緣膜13d、14d亦可抑制。 圖13~圖16為就第2實施方式的半導體裝置的製造方法進行繪示的剖面圖。示於圖13~圖16的方法相當於示於圖3及圖4的方法的具體例。 首先，將陣列晶圓W1及電路晶圓W2加工為示於圖13的構造。具體而言，在基板16(圖3參照)之上方形成絕緣膜13a，在絕緣膜13a內形成導孔插塞42，在絕緣膜13a及導孔插塞42上依序形成絕緣膜13b、13c，在絕緣膜13b、13c內依序形成屏障金屬層41a與墊材層41b。同樣地，在基板15(圖3參照)之上方形成絕緣膜14a，在絕緣膜14a內形成導孔插塞37，在絕緣膜14a及導孔插塞37上依序形成絕緣膜14b、14c，在絕緣膜14b、14c內依序形成屏障金屬層38a與墊材層38b。其結果，分別在層間絕緣膜13、14內形成金屬墊41、38。 接著，以金屬墊41被配置於金屬墊38上且層間絕緣膜13被配置於層間絕緣膜14上的方式，透過機械壓力將陣列晶圓W1與電路晶圓W2予以貼合(圖14)。據此，層間絕緣膜13與層間絕緣膜14被黏合。在圖14，於金屬墊38與金屬墊41的位置對準產生誤差，金屬墊38之上表面的一部分與金屬墊41的下表面的一部分相接。 接著，將陣列晶圓W1及電路晶圓W2退火(圖15)。據此，金屬墊41與金屬墊38被接合。圖15進一步示出墊材層38b、41b內的晶粒間的晶界α與沿著晶界α、貼合面S擴散的Ti原子群β。在本實施方式，透過示於圖15的程序的退火，使得Ti原子從屏障金屬層38a、41a擴散。 其結果，屏障金屬層38a、41a內的Ti原子擴散至墊材層38b與絕緣膜13c的界面、墊材層41b與絕緣膜14c的界面，在金屬層61被自對準地形成於此等界面的位置(圖16)。具體而言，從屏障金屬層38a、41a擴散至此等界面的Ti原子與絕緣膜14c、13c內的O原子反應，作為金屬層61形成TiO x層。據此，依本實施方式時，可透過金屬層61抑制從金屬墊38、41往層間絕緣膜14、13的Cu原子的擴散。 以此方式製造圖12的半導體裝置。之後，將基板15透過CMP薄膜化，將基板16透過CMP除去後，將陣列晶圓W1及電路晶圓W2切斷為複數個晶片。以此方式製造圖1的半導體裝置。 如以上，本實施方式的半導體裝置在金屬墊38之上表面與層間絕緣膜13的下表面之間、在金屬墊41的下表面與層間絕緣膜14之上表面之間具備含有與含於屏障金屬層38a、41a的金屬元素相同的金屬元素的金屬層61。據此，依本實施方式時，可形成可抑制從墊材層38b、41b往絕緣膜14c、13c的金屬原子(例如Cu原子)的擴散等合適的金屬墊38、41。 (第3實施方式) 圖17為就第3實施方式的半導體裝置的構造進行繪示的剖面圖。 本實施方式的層間絕緣膜13不具備絕緣膜13d(SiCN膜)，其結果絕緣膜13e(SiO 2膜)亦不具備。另一方面，本實施方式的層間絕緣膜14具備絕緣膜14d(SiCN膜)，其結果絕緣膜14e(SiO 2膜)亦具備。在本實施方式，層間絕緣膜13內的絕緣膜13c(SiO 2膜)與層間絕緣膜14內的絕緣膜14e(SiO 2膜)在貼合面S彼此相接。 本實施方式的半導體裝置亦具備金屬層61。本實施方式的金屬層61方面，因從屏障金屬層38a、41a擴散的Ti原子與絕緣膜14e、13c內的O原子產生反應而被形成。 依本實施方式時，層間絕緣膜14方面可享有與第1實施方式同樣的優點，層間絕緣膜13方面可享有與第2實施方式同樣的優點。本實施方式的半導體裝置可透過例如在陣列晶圓W1方面適用示於圖13~圖16的方法且在電路晶圓W2方面適用示於圖7~圖11的方法從而製造。 另外，本實施方式的半導體裝置方面，可層間絕緣膜13具備絕緣膜13d、13e，層間絕緣膜14不具備絕緣膜14d、14e。 (第4實施方式) 圖18為就第4實施方式的半導體裝置的構造進行繪示的剖面圖。 相對於第1~第3實施方式的金屬墊38與導孔插塞37為單鑲嵌佈線，本實施方式的金屬墊38與導孔插塞37為雙鑲嵌佈線。據此，本實施方式的導孔插塞37內的屏障金屬層37a及插塞材層37b分別與金屬墊38內的屏障金屬層38a及墊材層38b相同，導孔插塞37內的插塞材層37b與金屬墊38內的墊材層38b相接。換言之，在墊材層38b與插塞材層37b的邊界面未設置屏障金屬層38a、37b。屏障金屬層38a與屏障金屬層37b為第1層之例，墊材層38b與插塞材層37b為第2層之例。 同樣地，相對於第1~第3實施方式的金屬墊41與導孔插塞42為單鑲嵌佈線，本實施方式的金屬墊41與導孔插塞42為雙鑲嵌佈線。據此，本實施方式的導孔插塞42內的屏障金屬層42a及插塞材層42b分別與金屬墊41內的屏障金屬層41a及墊材層41b相同，導孔插塞42內的插塞材層42b與金屬墊41內的墊材層41b相接。換言之，在墊材層41b與插塞材層42b的邊界面未設置屏障金屬層41a、42b。屏障金屬層41a與屏障金屬層42b為第3層之例，墊材層41b與插塞材層42b為第4層之例。 依本實施方式時，能以少的程序形成金屬墊38與導孔插塞37，能以少的程序形成金屬墊41與導孔插塞42。本實施方式的半導體裝置可例如在適用示於圖7~圖11的方法之際在圖7的程序使用雙鑲嵌法代替單鑲嵌法從而製造。 (第5實施方式) 圖19為就第5實施方式的半導體裝置的構造進行繪示的剖面圖。 本實施方式的金屬墊38與金屬墊41具有不同的平面形狀。本實施方式的金屬墊38與金屬墊41的平面形狀皆為正方形或長方形，惟金屬墊41的X方向的寬與金屬墊38的X方向的寬不同，金屬墊41的Y方向的寬與金屬墊38的Y方向的寬不同。例如，金屬墊41的X方向的寬比金屬墊38的X方向的寬短，金屬墊41的Y方向的寬比金屬墊38的Y方向的寬短，金屬墊41的下表面的整體與金屬墊38之上表面的一部分相接。 本實施方式的半導體裝置亦具備金屬層61。本實施方式的金屬層61方面，因從屏障金屬層38a、41a擴散的Ti原子主要與絕緣膜13e內的O原子產生反應而被形成。 在第1~第4實施方式，在金屬墊38與金屬墊41的位置對準方面產生誤差時，金屬墊38與金屬墊41的接觸面積產生變化，金屬墊38與金屬墊41的接觸電阻產生變化。另一方面，在本實施方式，即使金屬墊38與金屬墊41的位置對準方面產生小的誤差，金屬墊38與金屬墊41的接觸面積仍不會變化，金屬墊38與金屬墊41的接觸電阻不變化。據此，依本實施方式時，可抑制隨金屬墊38與金屬墊41的位置對準的誤差而產生的問題。 本實施方式的金屬墊38與金屬墊41具有不同的平面形狀，故即使未產生金屬墊38與金屬墊41的位置對準的誤差，仍出現金屬墊38之上表面位於層間絕緣膜13的下表面下之部分或金屬墊41的下表面位於層間絕緣膜14之上表面上之部分。在本實施方式，可在如此的部分形成金屬層61。據此，依本實施方式時，可一面享有金屬墊38與金屬墊41具有不同的平面形狀的情況下的優點，一面抑制金屬墊38與金屬墊41具有不同的平面形狀的情況下的缺點。 本實施方式的半導體裝置可例如在適用示於圖7~圖11的方法之際在圖7的程序使金屬墊38的平面形狀與金屬墊41的平面形狀不同從而製造。另外，在本實施方式可使用單鑲嵌法代替雙鑲嵌法。 (第6實施方式) 圖20為就第6實施方式的半導體裝置的構造進行繪示的剖面圖。 本實施方式的半導體裝置不僅具備彼此相接的金屬墊38、41(參照圖1等)而亦具備如示於圖20般彼此不相接的金屬墊38、41。如此的金屬墊38、41被例如作為不使用於將陣列晶圓W1與電路晶圓W2電連接的仿真墊而形成。仿真墊被例如為了調整在貼合面S之金屬墊38、41的密度而形成。 本實施方式的半導體裝置亦具備金屬層61。本實施方式的金屬墊38上的金屬層61方面，因從屏障金屬層38a擴散的Ti原子主要與絕緣膜13e內的O原子產生反應而被形成。另一方面，本實施方式的金屬墊41下的金屬層61方面，因從屏障金屬層41a擴散的Ti原子主要與絕緣膜14e內的O原子反應而被形成。 本實施方式的半導體裝置可在例如適用示於圖7~圖11的方法之際在圖9的程序以示於圖20的金屬墊38與金屬墊41不相接的方式將陣列晶圓W1與電路晶圓W2予以貼合從而製造。 以上，雖說明若干實施方式，惟此等實施方式為僅作為舉例而提示者，非有意限定發明的範圍者。在本說明書說明的新穎的裝置及方法能以其他各種的方式實施。此外，對於在本說明書說明的裝置及方法的方式，在不脫離發明的要旨的範圍內可進行各種的省略、置換、變更。申請專利範圍及與其均等的範圍意在包含發明的範圍、要旨所含的如此的方式、變形例。
1:陣列晶片 2:電路晶片 11:記憶體單元陣列 12:絕緣膜 13:層間絕緣膜 13a:絕緣膜 13b:絕緣膜 13c:絕緣膜 13d:絕緣膜 13e:絕緣膜 14:層間絕緣膜 14a:絕緣膜 14b:絕緣膜 14c:絕緣膜 14d:絕緣膜 14e:絕緣膜 15:基板 16:基板 21:階層構造部 22:接觸插塞 23:字佈線層 24:導孔插塞 31:電晶體 32:閘極電極 33:接觸插塞 34:佈線層 35:佈線層 36:佈線層 37:導孔插塞 37a:屏障金屬層 37b:插塞材層 38:金屬墊 38a:屏障金屬層 38b:墊材層 41:金屬墊 41a:屏障金屬層 41b:墊材層 42:導孔插塞 42a:屏障金屬層 42b:插塞材層 43:佈線層 44:佈線層 45:導孔插塞 46:金屬墊 47:鈍化膜 51:絕緣層 52:區塊絕緣膜 53:電荷儲存層 54:通道絕緣膜 55:通道半導體層 56:核心絕緣膜 61:金屬層
[圖1]為就第1實施方式的半導體裝置的構造進行繪示的剖面圖。 [圖2]為就第1實施方式的柱狀部CL的構造進行繪示的剖面圖。 [圖3~圖4]為就第1實施方式的半導體裝置的製造方法進行繪示的剖面圖。 [圖5]為就第1實施方式的比較例的半導體裝置的構造進行繪示的剖面圖。 [圖6]為就第1實施方式的半導體裝置的構造進行繪示的剖面圖。 [圖7~圖11]為就第1實施方式的半導體裝置的製造方法進行繪示的剖面圖。 [圖12]為就第2實施方式的半導體裝置的構造進行繪示的剖面圖。 [圖13~圖16]為就第2實施方式的半導體裝置的製造方法進行繪示的剖面圖。 [圖17]為就第3實施方式的半導體裝置的構造進行繪示的剖面圖。 [圖18]為就第4實施方式的半導體裝置的構造進行繪示的剖面圖。 [圖19]為就第5實施方式的半導體裝置的構造進行繪示的剖面圖。 [圖20]為就第6實施方式的半導體裝置的構造進行繪示的剖面圖。
13:層間絕緣膜 13a:絕緣膜 13b:絕緣膜 13c:絕緣膜 13d:絕緣膜 13e:絕緣膜 14:層間絕緣膜 14a:絕緣膜 14b:絕緣膜 14c:絕緣膜 14d:絕緣膜 14e:絕緣膜 37:導孔插塞 38:金屬墊 38a:屏障金屬層 38b:墊材層 41:金屬墊 41a:屏障金屬層 41b:墊材層 42:導孔插塞 61:金屬層 W1:陣列晶圓 W2:電路晶圓 S:符號

Claims (15)

  1. 一種半導體裝置，其具備： 第1絕緣膜； 第1墊，其為設於前述第1絕緣膜內者，且包含設於前述第1絕緣膜之側面及下表面的第1層與隔著前述第1層而設於前述第1絕緣膜之側面及下表面的第2層； 第2絕緣膜，其設於前述第1絕緣膜上； 第2墊，其在前述第2絕緣膜內設於前述第1墊上，且包含設於前述第2絕緣膜之側面及上表面的第3層與隔著前述第3層而設於前述第2絕緣膜之側面及上表面的第4層；以及 第1部分，其設於前述第1墊之上表面與前述第2絕緣膜的下表面之間或前述第2墊的下表面與前述第1絕緣膜之上表面之間，且包含與含於前述第1層或前述第3層的金屬元素相同的金屬元素。
  2. 如請求項1的半導體裝置，其中，前述第1部分包含前述金屬元素與氧。
  3. 如請求項1或2的半導體裝置，其中，前述金屬元素包含鈦、鋁或錳。
  4. 如請求項1或2的半導體裝置，其中， 前述第1層接於前述第1絕緣膜之側面及下表面、或 前述第3層接於前述第2絕緣膜之側面及上表面。
  5. 如請求項1或2的半導體裝置，其中， 前述第1絕緣膜包含含有氧且接於前述第1部分的下表面的第1膜、或 前述第2絕緣膜包含含有氧且接於前述第1部分之上表面的第2膜。
  6. 如請求項5的半導體裝置，其中，前述第1膜或前述第2膜為自然氧化膜。
  7. 如請求項5的半導體裝置，其中， 前述第1絕緣膜包含前述第1膜及含有碳與氮且接於前述第1膜的下表面的第3膜，或 前述第2絕緣膜包含前述第2膜及含有碳與氮且接於前述第2膜之上表面的第4膜。
  8. 如請求項1或2的半導體裝置，其中，前述第1墊與前述第2墊具有相同的寬。
  9. 如請求項1或2的半導體裝置，其中，前述第1墊與前述第2墊具有不同的寬。
  10. 如請求項1或2的半導體裝置，其中， 前述第1墊設於包含前述第1層及前述第2層的第1插塞上且前述第1插塞內的前述第2層接於前述第1墊內的前述第2層，或 前述第2墊設於包含前述第3層及前述第4層的第2插塞下且前述第2插塞內的前述第4層與前述第2墊內的前述第4層相接。
  11. 一種半導體裝置，其具備： 第1絕緣膜； 第1墊，其為設於前述第1絕緣膜內者，且包含設於前述第1絕緣膜之側面及下表面的第1層與隔著前述第1層而設於前述第1絕緣膜之側面及下表面的第2層； 第2絕緣膜，其設於前述第1絕緣膜上； 第2墊，其在前述第2絕緣膜內設於不接於前述第1墊的位置，且包含設於前述第2絕緣膜之側面及上表面的第3層與隔著前述第3層而設於前述第2絕緣膜之側面及上表面的第4層；以及 第1部分，其設於前述第1墊之上表面與前述第2絕緣膜的下表面之間或前述第2墊的下表面與前述第1絕緣膜之上表面之間，且包含與含於前述第1層或前述第3層的金屬元素相同的金屬元素。
  12. 如請求項11的半導體裝置，其中，前述第1部分包含前述金屬元素與氧。
  13. 如請求項11或12的半導體裝置，其中，前述金屬元素包含鈦、鋁或錳。
  14. 一種半導體裝置之製造方法，其包含： 在第1絕緣膜內形成第1墊，前述第1墊包含設於前述第1絕緣膜之側面及底面的第1層與隔著前述第1層而設於前述第1絕緣膜之側面及底面的第2層； 在第2絕緣膜內形成第2墊，前述第2墊包含設於前述第2絕緣膜之側面及底面的第3層與隔著前述第3層而設於前述第2絕緣膜之側面及底面的第4層； 在前述第1絕緣膜上配置前述第2絕緣膜，且在前述第1墊上配置前述第2墊；以及 在前述第1墊之上表面與前述第2絕緣膜的下表面之間或在前述第2墊的下表面與前述第1絕緣膜之上表面之間形成含有與含於前述第1層或前述第3層的金屬元素相同的金屬元素的第1部分。
  15. 如請求項14的半導體裝置之製造方法，其中，前述第1部分由從前述第1層或前述第3層擴散的前述金屬元素形成。
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