TWI725489B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI725489B
TWI725489B TW108125975A TW108125975A TWI725489B TW I725489 B TWI725489 B TW I725489B TW 108125975 A TW108125975 A TW 108125975A TW 108125975 A TW108125975 A TW 108125975A TW I725489 B TWI725489 B TW I725489B
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bonding
wafer
semiconductor device
chip
plugs
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TW108125975A
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TW202034493A (zh
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飯島純
田上政由
荒井伸也
冨松孝宏
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日商東芝記憶體股份有限公司
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    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract

實施形態提供一種能使採用了貼合技術之半導體裝置中接合墊之配置或配線呈現更佳形態之半導體裝置及其製造方法。  根據一個實施形態，半導體裝置具備第1晶片，該第1晶片具有：第1基板；控制電路，其設置於上述第1基板上；及第1焊墊，其設置於上述控制電路之上方，且電性連接於上述控制電路。上述裝置進而具備第2晶片，該第2晶片具有：第2焊墊，其設置於上述第1焊墊上；插塞，其設置於上述第2焊墊之上方，沿著第1方向延伸，且包含距離上述第1基板越遠則與上述第1方向正交之截面上之直徑越大之部分；及接合墊，其設置於上述插塞上，與上述第1方向交叉，且藉由上述插塞與上述第2焊墊電性連接。

Description

半導體裝置及其製造方法
本發明之實施形態係關於一種半導體裝置及其製造方法。
於採用了使晶圓彼此貼合之貼合技術之半導體裝置中，接合墊之配置、或接合墊相對於邏輯電路等之配線要考慮到例如製造成本或可靠性等而擇優選用。
實施形態提供一種能使採用了貼合技術之半導體裝置中接合墊之配置或配線呈現更佳形態之半導體裝置及其製造方法。
根據一個實施形態，半導體裝置具備第1晶片，該第1晶片具有：第1基板；控制電路，其設置於上述第1基板上；及第1焊墊，其設置於上述控制電路之上方，且電性連接於上述控制電路。上述裝置進而具備第2晶片，該第2晶片具有：第2焊墊，其設置於上述第1焊墊上；插塞，其設置於上述第2焊墊之上方，沿著第1方向延伸，且包含距離上述第1基板越遠則與上述第1方向正交之截面上之直徑越大之部分；及接合墊，其設置於上述插塞上，與上述第1方向交叉，且藉由上述插塞與上述第2焊墊電性連接。
以下，參照圖式對本發明之實施形態進行說明。於圖1至圖11中，對相同或類似之構成標註相同之符號，對重複之說明予以省略。  (第1實施形態)
圖1係表示第1實施形態之半導體裝置之構造之剖視圖。圖1之半導體裝置係由陣列晶片1與電路晶片2貼合而成之三維記憶體。
陣列晶片1具備包含複數個記憶單元之記憶單元陣列11、記憶單元陣列11上之絕緣膜12、記憶單元陣列11下之層間絕緣膜13、及層間絕緣膜13下之絕緣膜14。絕緣膜12、14例如為氧化矽膜或氮化矽膜。
電路晶片2設置於陣列晶片1下。符號S表示陣列晶片1與電路晶片2之貼合面。電路晶片2具備絕緣膜15、絕緣膜15下之層間絕緣膜16、及層間絕緣膜16下之基板17。絕緣膜15例如為氧化矽膜或氮化矽膜。基板17例如為矽基板等半導體基板。基板17係第1基板之例。
圖1表示出了與基板17之表面平行且相互垂直之X方向及Y方向、以及與基板17之表面垂直且與基板17交叉之Z方向。於本說明書中，將+Z方向設為上方向，將-Z方向設為下方向。例如，記憶單元陣列11位於基板17之上方，基板17位於記憶單元陣列11之下方。-Z方向可與重力方向一致亦可不一致。Z方向係第1方向之例。再者，X方向及Y方向亦與下述基板18之表面平行，Z方向亦與該基板18之表面垂直。
陣列晶片1具備複數條字元線WL、源極側選擇閘極SGS、汲極側選擇閘極SGD及源極線SL，以此作為記憶單元陣列11內之電極層。圖1表示出了記憶單元陣列11之階梯構造部21。如圖1所示，各字元線WL經由接觸插塞22與字配線層23電性連接，源極側選擇閘極SGS經由接觸插塞24與源極側選擇閘極配線層25電性連接。進而，汲極側選擇閘極SGD經由接觸插塞26與汲極側選擇閘極配線層27電性連接，源極線SL經由接觸插塞29與源極配線層30電性連接。貫通字元線WL、源極側選擇閘極SGS及汲極側選擇閘極SGD之柱狀部CL經由插塞28與位元線BL電性連接，且與源極線SL電性連接。
電路晶片2具備複數個電晶體31。各電晶體31具備：閘極電極32，其隔著閘極絕緣膜設置於基板17上；以及未圖示之源極擴散層及汲極擴散層，其等設置於基板17內。電路晶片2進而具備：複數個插塞33，其等設置於該等電晶體31之源極擴散層或汲極擴散層上；配線層34，其設置於該等插塞33上，且包含複數條配線；及配線層35，其設置於配線層34上，且包含複數條配線。電路晶片2進而具備：複數個通孔插塞36，其等設置於配線層35上；及複數個金屬焊墊37，其等在絕緣膜15內設置於該等通孔插塞36上。金屬焊墊37係第1焊墊之例。金屬焊墊37例如為Cu(銅)層或Al(鋁)層。電路晶片2作為控制陣列晶片1之控制電路(邏輯電路)而發揮功能。該控制電路包含電晶體31等，且電性連接於金屬焊墊37。
陣列晶片1具備：複數個金屬焊墊41，其等在絕緣膜14內設置於金屬焊墊37上；複數個通孔插塞42，其等設置於金屬焊墊41上；及配線層43，其設置於該等通孔插塞42上，且包含複數條配線。各字元線WL及各位元線BL與配線層43內對應之配線電性連接。金屬焊墊41係第2焊墊之例。金屬焊墊41例如為Cu層或Al層。陣列晶片1進而具備：通孔插塞44，其設置於層間絕緣膜13內或絕緣膜12內，且設置於配線層43上；及金屬焊墊45，其設置於絕緣膜14上或通孔插塞44上。金屬焊墊45例如為Cu層或Al層，作為圖1之半導體裝置之外部連接焊墊(接合墊)而發揮功能，經由接合線、焊料球、金屬凸塊等能連接於安裝基板或其他裝置。
圖2係表示第1實施形態之半導體裝置中包含之柱狀部CL之構造之剖視圖。
如圖2所示，記憶單元陣列11具備交替地設置於層間絕緣膜13(圖1)上之複數條字元線WL及複數個絕緣層51。該等字元線WL係於Z方向上相互分離而積層。字元線WL係電極層之例。字元線WL例如為W(鎢)層。絕緣層51例如為氧化矽膜。
柱狀部CL依序包含阻擋絕緣膜52、電荷儲存層53、隧道絕緣膜54、通道半導體層55及核心絕緣膜56。電荷儲存層53例如為氮化矽膜，隔著阻擋絕緣膜52形成於字元線WL及絕緣層51之側面。通道半導體層55例如為多晶矽層，隔著隧道絕緣膜54形成於電荷儲存層53之側面。阻擋絕緣膜52、隧道絕緣膜54及核心絕緣膜56例如為氧化矽膜或金屬絕緣膜。
再者，圖1中，於層間絕緣膜13之下表面形成有絕緣膜14，但絕緣膜14亦可包含於層間絕緣膜13中，與層間絕緣膜13一體化。同樣地，圖1中，於層間絕緣膜16之上表面形成有絕緣膜15，但絕緣膜15亦可包含於層間絕緣膜16中，與層間絕緣膜16一體化。於下述圖3至圖11中，因絕緣膜14包含於層間絕緣膜13中，與層間絕緣膜13一體化，絕緣膜15包含於層間絕緣膜16中，與層間絕緣膜16一體化，故未標出符號14、15。但圖3至圖11中，亦可為於層間絕緣膜13之下表面形成有絕緣膜14，於層間絕緣膜16之上表面形成有絕緣膜15。
於圖1中，柱狀部CL設置於記憶單元陣列11內，位於構成記憶單元陣列11之複數條字元線WL內，而通孔插塞44設置於記憶單元陣列11之外部，位於構成記憶單元陣列11之複數條字元線WL之外部。通孔插塞44沿著記憶單元陣列11之側部方向設置，圖1中係沿著記憶單元陣列11之X方向設置。通孔插塞44例如為金屬層或半導體層。
本實施形態之基板17具有位於通孔插塞44下方之第1區域、及位於記憶單元陣列11下方之第2區域。第1區域係圖1中之右側區域，第2區域係圖1中之左側區域。通孔插塞44及電性連接於通孔插塞44之金屬焊墊37、41、45位於基板17之第1區域之上方。另一方面，記憶單元陣列11位於基板17之第2區域之上方。通孔插塞44經由該等金屬焊墊37、41電性連接於電路晶片2內之控制電路。
如圖1所示，本實施形態之通孔插塞44具有沿著Z方向較長地延伸之柱狀形狀之部分(柱狀部)。通孔插塞44之下端(-Z方向之端部)設置於較最下層之字元線WL之下表面更低之位置，通孔插塞44之上端(+Z方向之端部)設置於較最上層之字元線WL之上表面更高之位置。通孔插塞44之下端係電路晶片2側之端部，通孔插塞44之上端係電路晶片2之相反側之端部。關於通孔插塞44之詳細情況將於下文進行敍述。
圖3係表示第1實施形態之半導體裝置之另一構造之剖視圖。圖3與圖1同樣地表示出了半導體裝置之截面，但卻基於與圖1不同之觀點表示出了半導體裝置之配線構造。
本實施形態之陣列晶片1於金屬焊墊41與金屬焊墊45之間具備複數個通孔插塞44。該等通孔插塞44沿著Z方向延伸，並經由通孔插塞42及配線層43電性連接於金屬焊墊41，且電性連接於金屬焊墊45。於本實施形態中，藉由將金屬焊墊41與金屬焊墊45以複數個通孔插塞44電性連接，例如，能節約用以形成通孔插塞44之材料，或能簡單地形成通孔插塞44。
圖3表示出了各通孔插塞44之側面T、及各通孔插塞44之寬度W。本實施形態之各通孔插塞44之側面T具有錐形形狀。其結果，本實施形態之通孔插塞44之寬度W對應於與電路晶片2相距之距離而減少。藉此，通孔插塞44之上端之寬度W小於通孔插塞44之下端之寬度W。例如，於通孔插塞44之形狀為圓柱形之情形時，寬度W相當於通孔插塞44之插塞徑(直徑)。
此處，關於通孔插塞44之形狀為圓柱形以外形狀時之通孔插塞44之插塞徑，本實施形態中係按以下所述加以規定。首先，於考慮某Z座標中之通孔插塞44之插塞徑時，要著眼於該Z座標中之通孔插塞44之XY截面形狀。例如，通孔插塞44之XY截面形狀為橢圓形或四邊形。其次，將XY截面形狀替換成相同面積之圓。然後，將該圓之直徑規定為該Z座標中之通孔插塞44之插塞徑。於本實施形態中，以通孔插塞44之插塞徑對應於與電路晶片2相距之距離而減少，通孔插塞44之上端之插塞徑小於通孔插塞44之下端之插塞徑之方式，形成通孔插塞44。於通孔插塞44之形狀接近於圓柱形之情形時，通孔插塞44之插塞徑成為接近於通孔插塞44之寬度W之值。本實施形態之通孔插塞44之插塞徑係插塞之直徑之例。
陣列晶片1進而具備形成於絕緣膜12及金屬焊墊45上之鈍化膜46。鈍化膜46例如為氧化矽膜或氮化矽膜等絕緣膜。鈍化膜46具有使金屬焊墊45之上表面露出之開口部P。開口部P例如用以向金屬焊墊45連接接合線。本實施形態之開口部P形成於在Z方向上與各通孔插塞44重疊之位置，即，形成於各通孔插塞44之正上方。
圖4至圖10係表示第1實施形態之半導體裝置之製造方法之剖視圖。
圖4表示出了包含複數個陣列晶片1之陣列晶圓W1、及包含複數個電路晶片2之電路晶圓W2。陣列晶圓W1亦稱作記憶體晶圓，電路晶圓W2亦稱作CMOS CMOS(Complementary Metal Oxide Semiconductor，互補金氧半導體)晶圓。再者，陣列晶圓W1於絕緣膜12下具備基板18。基板18例如為矽基板等半導體基板。基板18係第2基板之例。
首先，準備圖4所示之記憶體晶圓W1及電路晶圓W2。圖4表示出了與圖3對應之截面，但要注意一點，圖4之記憶體晶圓W1之方向與圖3之記憶體晶片1之方向相反。圖4表示出了為了貼合而使方向反轉前之記憶體晶圓W1，圖3表示出了為了貼合而使方向反轉並加以貼合及切割後之記憶體晶片1。
圖4之步驟中，於基板17上形成電晶體31及層間絕緣膜16，於層間絕緣膜16內形成金屬焊墊37等，從而製作出電路晶圓W2。金屬焊墊37係藉由例如以下所述方法而形成：採用RIE(Reactive Ion Etching，反應式離子蝕刻)於層間絕緣膜16之表面形成凹部，然後向凹部內埋入金屬焊墊37。
圖4之步驟中，進而於基板18上隔著絕緣膜12形成記憶單元陣列11及層間絕緣膜13，於絕緣膜12或層間絕緣膜13內形成通孔插塞44、配線層43、通孔插塞42及金屬焊墊41，從而製作出陣列晶圓W1。金屬焊墊41係藉由例如以下所述方法而形成：採用RIE於層間絕緣膜16之表面形成凹部，然後向凹部內埋入金屬焊墊41。
又，通孔插塞44係以如下方法形成。首先，於基板18上，形成絕緣膜12、及層間絕緣膜13之一部分。其次，採用RIE形成貫通絕緣膜12、及層間絕緣膜13之一部分之貫通孔。其結果，貫通孔形成為藉由RIE之作用而具有錐形形狀之側面。其次，向貫通孔內埋入通孔插塞44。藉此，通孔插塞44形成為具有錐形形狀之側面T，通孔插塞44之寬度W或插塞徑被設定為對應於與基板18相距之距離而增加。其後，於基板18之上方，形成層間絕緣膜13之剩餘部分、配線層43、通孔插塞42及金屬焊墊41。
其次，使陣列晶圓W1貼合於電路晶圓W2(圖5)。具體而言，首先，使陣列晶圓W1與電路晶圓W2藉由機械壓力而貼合。藉此，層間絕緣膜13黏接於層間絕緣膜16。其次，以250℃～400℃對陣列晶圓W1及電路晶圓W2進行退火。藉此，金屬焊墊41接合於金屬焊墊37，並電性連接於金屬焊墊37。圖5表示出了金屬焊墊41配置於金屬焊墊37上之情形。
其次，將基板18自陣列晶圓W1去除(圖6)。其結果，通孔插塞44露出。基板18之去除係採用例如CMP(Chemical Mechanical Polishing，化學機械拋光)或濕式蝕刻而進行。
其次，於絕緣膜12及通孔插塞44上，形成用以形成金屬焊墊45之金屬層(圖7)。於圖7中，該金屬層亦用符號45表示，以使說明容易理解。其次，採用RIE蝕刻該金屬層，而於通孔插塞44上形成金屬焊墊45(圖8)。
其次，於絕緣膜12及金屬焊墊45上，形成鈍化膜46(圖9)。其次，採用RIE蝕刻鈍化膜46，而於鈍化膜46內形成使金屬焊墊45之上表面露出之開口部P(圖10)。
其後，採用CMP使基板17薄膜化後，將陣列晶圓W1及電路晶圓W2切斷(切割)成複數個晶片。按照如此之步驟，製造出圖3之半導體裝置。
按照上文所述，本實施形態之半導體裝置係使陣列晶片1(陣列晶圓W1)與電路晶片2(電路晶圓W2)貼合而製造獲得。因此，需要將陣列晶片1之金屬焊墊41與金屬焊墊45電性連接。因此，於本實施形態中，貼合前於陣列晶片1內形成通孔插塞44，其後藉由通孔插塞44將金屬焊墊41與金屬焊墊45電性連接。藉此，能將通孔插塞44連同記憶單元陣列11等一併形成於基板18上。於本實施形態中，通孔插塞44之寬度W係對應於與電路晶片2相距之距離而減少，其原因在於，貼合前便形成了通孔插塞44。
又，本實施形態之陣列晶片1於金屬焊墊41與金屬焊墊45之間具備複數個通孔插塞44。藉此，根據本實施形態，與形成1個粗大之通孔插塞時相比，能節約用以形成通孔插塞44之材料，或能簡單地形成通孔插塞44。於本實施形態中，此種通孔插塞44配置於記憶單元陣列11之外部，而非記憶單元陣列11之內部。
綜上所述，根據本實施形態，能使採用了貼合技術之半導體裝置中接合墊之配置或配線呈現更佳形態。
再者，本實施形態中係使陣列晶圓W1與電路晶圓W2貼合，但亦可取而代之地，使陣列晶圓W1彼此貼合，或使電路晶圓W2彼此貼合。即，作為貼合對象之晶圓可為任意種類之晶圓。參照圖1至圖10於上文敍述之內容、或參照圖11於下文敍述之內容亦適用於使陣列晶圓W1與電路晶圓W2貼合之情況以外之貼合。
又，圖1表示出了絕緣膜14與絕緣膜15之交界面、及金屬焊墊41與金屬焊墊37之交界面，但一般而言，於上述退火步驟後，該等交界面便看不到了。然而，該等交界面所處之位置可藉由檢測例如金屬焊墊41之側面或金屬焊墊37之側面之傾斜、或者金屬焊墊41之側面與金屬焊墊37之位置偏移加以推定。  (第2實施形態)
圖11係表示第2實施形態之半導體裝置之構造之剖視圖。
本實施形態之半導體裝置與第1實施形態之半導體裝置(圖3)同樣地，具備金屬焊墊45及鈍化膜46。但本實施形態之金屬焊墊45自通孔插塞44之正上方之區域延伸至記憶單元陣列11之正上方之區域。再者，本實施形態之開口部P設置於在Z方向上不與通孔插塞44重疊之位置，且設置於在Z方向上與記憶單元陣列11重疊之位置。即，本實施形態之開口部P設置於記憶單元陣列11之正上方。
本實施形態之半導體裝置與第1實施形態之半導體裝置同樣地，可藉由圖4至圖10之步驟製造。但圖8之步驟係以形成圖11所示之形狀之金屬焊墊45之方式進行。進而，圖10之步驟係以於圖11所示之位置形成開口部P之方式進行。
根據第1實施形態，能將金屬焊墊45之面積設定得較小。而根據本實施形態，能將開口部P配置於各種位置。開口部P本實施形態中係設置於記憶單元陣列11之正上方，但亦可設置於其他位置。
以上，對若干個實施形態進行了說明，但該等實施形態僅係作為示例而提出，並非要限定發明之範圍。本說明書中所說明之新穎之裝置及方法能以其他各種實施形態加以實施。又，對於本說明書中所說明之裝置及方法之實施形態，可於不脫離發明主旨之範圍內，進行各種省略、替換、變更。隨附之申請專利範圍及其均等範圍希望將發明之範圍或主旨中包含之該等實施形態及變化例包含於內。  [相關申請案]
本申請案享有以日本專利申請案2019-44106號(申請日：2019年3月11日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1:陣列晶片2:電路晶片11:記憶單元陣列12:絕緣膜13:層間絕緣膜14:絕緣膜15:絕緣膜16:層間絕緣膜17:基板18:基板21:階梯構造部22:接觸插塞23:字配線層24:接觸插塞25:源極側選擇閘極配線層26:接觸插塞27:汲極側選擇閘極配線層28:插塞29:接觸插塞30:源極配線層31:電晶體32:閘極電極33:插塞34:配線層35:配線層36:通孔插塞37:金屬焊墊41:金屬焊墊42:通孔插塞43:配線層44:通孔插塞45:金屬焊墊46:鈍化膜51:絕緣層52:阻擋絕緣膜53:電荷儲存層54:隧道絕緣膜55:通道半導體層56:核心絕緣膜BL:位元線CL:柱狀部P:開口部S:陣列晶片與電路晶片之貼合面SGD:汲極側選擇閘極SGS:源極側選擇閘極SL:源極線T:通孔插塞之側面W:通孔插塞之寬度WL:字元線W1:陣列晶圓W2:電路晶圓
圖1係表示第1實施形態之半導體裝置之構造之剖視圖。  圖2係表示第1實施形態之半導體裝置中包含之柱狀部之構造之剖視圖。  圖3係表示第1實施形態之半導體裝置之另一構造之剖視圖。  圖4～圖10係表示第1實施形態之半導體裝置之製造方法之剖視圖。  圖11係表示第2實施形態之半導體裝置之構造之剖視圖。
1:陣列晶片
2:電路晶片
11:記憶單元陣列
12:絕緣膜
13:層間絕緣膜
16:層間絕緣膜
17:基板
31:電晶體
32:閘極電極
33:插塞
34:配線層
35:配線層
36:通孔插塞
37:金屬焊墊
41:金屬焊墊
42:通孔插塞
43:配線層
44:通孔插塞
45:金屬焊墊
46:鈍化膜
P:開口部
S:陣列晶片與電路晶片之貼合面
T:通孔插塞之側面
W:通孔插塞之寬度

Claims (10)

  1. 一種半導體裝置，其具備第1晶片及第2晶片，該第1晶片具有：第1基板；複數個電晶體，其設置於上述第1基板上；及第1及第2焊墊，其設置於上述複數個電晶體之上方，且分別電性連接於上述複數個電晶體；該第2晶片具有：第3焊墊，其接觸設置於上述第1焊墊上；第4焊墊，其接觸設置於上述第2焊墊上；配線層，其設置於上述第3及第4焊墊之上方；複數個插塞，其分別接觸設置於上述配線層之上方，且分別沿著第1方向延伸，且包含距離上述第1基板越遠則與上述第1方向正交之截面上之直徑越小之部分；及接合墊，其設置於上述複數個插塞上，與上述第1方向交叉，且藉由上述複數個插塞、上述配線層、上述第3及第4焊墊、及上述第1及第2焊墊電性連接於上述複數個電晶體。
  2. 如請求項1之半導體裝置，其中上述第1晶片進而具備：第5焊墊，其設置於上述複數個電晶體之上方，且電性連接於上述複數個電晶體； 上述第2晶片進而具備：第6焊墊，其接觸設置於上述第5焊墊上；及記憶單元陣列，其藉由上述第5及第6焊墊電性連接於上述複數個電晶體。
  3. 如請求項1之半導體裝置，其中上述第2晶片進而具備設置於上述接合墊上之絕緣膜，且上述絕緣膜具有使上述接合墊之上表面露出之開口部。
  4. 如請求項3之半導體裝置，其中上述開口部設置於在上述第1方向上與上述複數個插塞重疊之位置。
  5. 如請求項3之半導體裝置，其中上述開口部設置於在上述第1方向上不與上述複數個插塞重疊之位置。
  6. 如請求項5之半導體裝置，其中上述開口部設置於在上述第1方向上與上述第2晶片內之記憶單元陣列重疊之位置。
  7. 如請求項1至6中任一項之半導體裝置，其中上述第2晶片內之上述記憶單元陣列具備於上述第1方向上相互分離而積層之複數個電極層，且上述複數個插塞之上述第1晶片側之端部設置於較最下層之上述電極層之下表面更低之位置，上述複數個插塞之上述第1晶片之相反側之端部設置於較最上層之上述電極層之上表面更高之位置。
  8. 一種半導體裝置之製造方法，其包含如下所述步驟：於第1晶圓上形成複數個電晶體；於上述第1晶圓之上述複數個電晶體之設置於上方之貼合面，形成電性連接於上述複數個電晶體之第1及第2焊墊；於第2晶圓之上方形成複數個插塞，該複數個插塞沿著第1方向延伸，且包含距離上述第2晶圓之設置於上方之貼合面越遠則與上述第1方向正交之截面上之直徑越小之部分；形成設置於上述複數個插塞之上述貼合面側之配線層，且該配線層分別接觸上述複數個插塞之上述變小之部分之端部；於上述第2晶圓之上述貼合面，形成接觸設置於上述第1焊墊、且電性連接於上述配線層之第3焊墊；於上述第2晶圓之上述貼合面，形成接觸設置於上述第2焊墊、且電性連接於上述配線層之第4焊墊；以上述第3及第4焊墊配置於上述第1及第2焊墊上之方式，使上述第2晶圓貼合於上述第1晶圓；於經貼合後之上述第2晶圓之與上述貼合面相反之面，使上述複數個插塞露出；於所露出之上述插塞上，形成與上述第1方向交叉之接合墊；及自經貼合後之晶圓切出晶片。
  9. 如請求項8之半導體裝置之製造方法，其進而包含如下所述步驟：於上述貼合步驟後，將上述第2晶圓之基板去除；且 上述基板被去除後，上述接合墊形成於上述複數個插塞上。
  10. 如請求項8或9之半導體裝置之製造方法，其進而包含如下所述步驟：於上述接合墊上，形成具有使上述接合墊之上表面露出之開口部之絕緣膜。
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