CN117855139A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN117855139A
CN117855139A CN202410183461.0A CN202410183461A CN117855139A CN 117855139 A CN117855139 A CN 117855139A CN 202410183461 A CN202410183461 A CN 202410183461A CN 117855139 A CN117855139 A CN 117855139A
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China
Prior art keywords
bonding
plugs
semiconductor device
bonding pad
chip
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CN202410183461.0A
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English (en)
Inventor
饭岛纯
田上政由
荒井伸也
冨松孝宏
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Kioxia Corp
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Kioxia Corp
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Publication of CN117855139A publication Critical patent/CN117855139A/zh
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract

实施方式提供一种能够使采用了贴合技术的半导体装置中接合垫的配置或配线呈现更好的形态的半导体装置及其制造方法。根据一个实施方式，半导体装置具备第1芯片，该第1芯片具有：第1衬底；控制电路，设置在所述第1衬底上；及第1焊垫，设置在所述控制电路的上方，且电连接于所述控制电路。所述装置还具备第2芯片，该第2芯片具有：第2焊垫，设置在所述第1焊垫上；插塞，设置在所述第2焊垫的上方，沿着第1方向延伸，且包含距离所述第1衬底越远则与所述第1方向正交的截面上的直径越大的部分；及接合垫，设置在所述插塞上，与所述第1方向交叉，且通过所述插塞与所述第2焊垫电连接。

Description

半导体装置及其制造方法
分案申请的相关信息
本案是分案申请。该分案的母案是申请日为2019年8月1日、申请号为201910709555.6、发明名称为“半导体装置及其制造方法”的发明专利申请案。
[相关申请案]
本申请案享有以日本专利申请案2019-44106号(申请日：2019年3月11日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
在采用了使晶圆彼此贴合的贴合技术的半导体装置中，接合垫的配置、或接合垫相对于逻辑电路等的配线要考虑到例如制造成本或可靠性等而择优选用。
发明内容
实施方式提供一种能够将采用了贴合技术的半导体装置中接合垫的配置或配线设定为更佳态样的半导体装置及其制造方法。
根据一个实施方式，半导体装置具备第1芯片，该第1芯片具有：第1衬底；控制电路，设置在所述第1衬底上；及第1焊垫，设置在所述控制电路的上方，且电连接于所述控制电路。所述装置还具备第2芯片，该第2芯片具有：第2焊垫，设置在所述第1焊垫上；插塞，设置在所述第2焊垫的上方，沿着第1方向延伸，且包含距离所述第1衬底越远则与所述第1方向正交的截面上的直径越大的部分；及接合垫，设置在所述插塞上，与所述第1方向交叉，且通过所述插塞与所述第2焊垫电连接。
附图说明
图1是表示第1实施方式的半导体装置的构造的截面图。
图2是表示第1实施方式的半导体装置中包含的柱状部的构造的截面图。
图3是表示第1实施方式的半导体装置的另一构造的截面图。
图4～图10是表示第1实施方式的半导体装置的制造方法的截面图。
图11是表示第2实施方式的半导体装置的构造的截面图。
具体实施方式
下面，参照附图对本发明的实施方式进行说明。在图1至图11中，对相同或类似的构成标注相同的符号，对重复的说明予以省略。
(第1实施方式)
图1是表示第1实施方式的半导体装置的构造的截面图。图1的半导体装置是由阵列芯片1与电路芯片2贴合而成的三维存储器。
阵列芯片1具备包含多个存储单元的存储单元阵列11、存储单元阵列11上的绝缘膜12、存储单元阵列11下的层间绝缘膜13、及层间绝缘膜13下的绝缘膜14。绝缘膜12、14例如为氧化硅膜或氮化硅膜。
电路芯片2设置在阵列芯片1下。符号S表示阵列芯片1与电路芯片2的贴合面。电路芯片2具备绝缘膜15、绝缘膜15下的层间绝缘膜16、及层间绝缘膜16下的衬底17。绝缘膜15例如为氧化硅膜或氮化硅膜。衬底17例如为硅衬底等半导体衬底。衬底17是第1衬底的例子。
图1表示出了与衬底17的表面平行且相互垂直的X方向及Y方向、以及与衬底17的表面垂直且与衬底17交叉的Z方向。在本说明书中，将+Z方向设为上方向，将-Z方向设为下方向。例如，存储单元阵列11位于衬底17的上方，衬底17位于存储单元阵列11的下方。-Z方向可以与重力方向一致也可以不一致。Z方向是第1方向的例子。此外，X方向及Y方向也与下述衬底18的表面平行，Z方向也与该衬底18的表面垂直。
阵列芯片1具备多条字线WL、源极侧选择栅极SGS、漏极侧选择栅极SGD及源极线SL，以此作为存储单元阵列11内的电极层。图1表示出了存储单元阵列11的阶梯构造部21。如图1所示，各字线WL经由接触插塞22与字配线层23电连接，源极侧选择栅极SGS经由接触插塞24与源极侧选择栅极配线层25电连接。进而，漏极侧选择栅极SGD经由接触插塞26与漏极侧选择栅极配线层27电连接，源极线SL经由接触插塞29与源极配线层30电连接。贯通字线WL、源极侧选择栅极SGS及漏极侧选择栅极SGD的柱状部CL经由插塞28与位线BL电连接，且与源极线SL电连接。
电路芯片2具备多个晶体管31。各晶体管31具备：栅极电极32，隔着栅极绝缘膜设置在衬底17上；以及未图示的源极扩散层及漏极扩散层，设置在衬底17内。电路芯片2还具备：多个插塞33，设置在这些晶体管31的源极扩散层或漏极扩散层上；配线层34，设置在这些插塞33上，且包含多条配线；及配线层35，设置在配线层34上，且包含多条配线。电路芯片2还具备：多个通孔插塞36，设置在配线层35上；及多个金属焊垫37，于绝缘膜15内设置在这些通孔插塞36上。金属焊垫37是第1焊垫的例子。金属焊垫37例如为Cu(铜)层或Al(铝)层。电路芯片2作为控制阵列芯片1的控制电路(逻辑电路)而发挥功能。该控制电路包含晶体管31等，且电连接于金属焊垫37。
阵列芯片1具备：多个金属焊垫41，于绝缘膜14内设置在金属焊垫37上；多个通孔插塞42，设置在金属焊垫41上；及配线层43，设置在这些通孔插塞42上，且包含多条配线。各字线WL及各位线BL与配线层43内对应的配线电连接。金属焊垫41是第2焊垫的例子。金属焊垫41例如为Cu层或Al层。阵列芯片1还具备：通孔插塞44，设置在层间绝缘膜13内或绝缘膜12内，且设置在配线层43上；及金属焊垫45，设置在绝缘膜14上或通孔插塞44上。金属焊垫45例如为Cu层或Al层，作为图1的半导体装置的外部连接焊垫(接合垫)而发挥功能，经由接合线、焊料球、金属凸块等能够连接于安装衬底或其他装置。
图2是表示第1实施方式的半导体装置中包含的柱状部CL的构造的截面图。
如图2所示，存储单元阵列11具备交替地设置在层间绝缘膜13(图1)上的多条字线WL及多个绝缘层51。这些字线WL是在Z方向上相互分离而积层的。字线WL是电极层的例子。字线WL例如为W(钨)层。绝缘层51例如为氧化硅膜。
柱状部CL依次包含阻挡绝缘膜52、电荷储存层53、隧道绝缘膜54、通道半导体层55及核心绝缘膜56。电荷储存层53例如为氮化硅膜，隔着阻挡绝缘膜52形成在字线WL及绝缘层51的侧面。通道半导体层55例如为多晶硅层，隔着隧道绝缘膜54形成在电荷储存层53的侧面。阻挡绝缘膜52、隧道绝缘膜54及核心绝缘膜56例如为氧化硅膜或金属绝缘膜。
此外，图1中，在层间绝缘膜13的下表面形成有绝缘膜14，但绝缘膜14也可以包含在层间绝缘膜13中，与层间绝缘膜13一体化。同样地，图1中，在层间绝缘膜16的上表面形成有绝缘膜15，但绝缘膜15也可以包含在层间绝缘膜16中，与层间绝缘膜16一体化。在下述图3至图11中，由于绝缘膜14包含在层间绝缘膜13中，与层间绝缘膜13一体化，绝缘膜15包含在层间绝缘膜16中，与层间绝缘膜16一体化，所以未标出符号14、15。但是，图3至图11中，也可以为在层间绝缘膜13的下表面形成有绝缘膜14，在层间绝缘膜16的上表面形成有绝缘膜15。
在图1中，柱状部CL设置在存储单元阵列11内，位于构成存储单元阵列11的多条字线WL内，而通孔插塞44设置在存储单元阵列11的外部，位于构成存储单元阵列11的多条字线WL的外部。通孔插塞44是沿着存储单元阵列11的侧部方向设置的，在图1中是沿着存储单元阵列11的X方向设置的。通孔插塞44例如为金属层或半导体层。
本实施方式的衬底17具有位于通孔插塞44下方的第1区域、及位于存储单元阵列11下方的第2区域。第1区域是图1中的右侧区域，第2区域是图1中的左侧区域。通孔插塞44及电连接于通孔插塞44的金属焊垫37、41、45位于衬底17的第1区域的上方。另一方面，存储单元阵列11位于衬底17的第2区域的上方。通孔插塞44经由这些金属焊垫37、41电连接于电路芯片2内的控制电路。
如图1所示，本实施方式的通孔插塞44具有沿着Z方向长长地延伸的柱状形状的部分(柱状部)。通孔插塞44的下端(-Z方向的端部)设置在比最下层的字线WL的下表面更低的位置，通孔插塞44的上端(+Z方向的端部)设置在比最上层的字线WL的上表面更高的位置。通孔插塞44的下端是电路芯片2侧的端部，通孔插塞44的上端是电路芯片2的相反侧的端部。关于通孔插塞44的详细情况将在下文进行叙述。
图3是表示第1实施方式的半导体装置的另一构造的截面图。图3与图1同样地表示出了半导体装置的截面，但却基于与图1不同的观点表示出了半导体装置的配线构造。
本实施方式的阵列芯片1在金属焊垫41与金属焊垫45之间具备多个通孔插塞44。这些通孔插塞44沿着Z方向延伸，并经由通孔插塞42及配线层43电连接于金属焊垫41，且电连接于金属焊垫45。在本实施方式中，通过将金属焊垫41与金属焊垫45以多个通孔插塞44电连接，例如，能够节约用来形成通孔插塞44的材料，或能够简单地形成通孔插塞44。
图3表示出了各通孔插塞44的侧面T、及各通孔插塞44的宽度W。本实施方式的各通孔插塞44的侧面T具有锥形形状。结果，本实施方式的通孔插塞44的宽度W对应于与电路芯片2相距的距离而减少。由此，通孔插塞44的上端的宽度W小于通孔插塞44的下端的宽度W。例如，在通孔插塞44的形状为圆柱形的情况下，宽度W相当于通孔插塞44的插塞径(直径)。
这里，关于通孔插塞44的形状为圆柱形以外形状时的通孔插塞44的插塞径，在本实施方式中是按以下所述加以规定的。首先，在考虑某Z坐标中的通孔插塞44的插塞径时，要着眼于该Z坐标中的通孔插塞44的XY截面形状。例如，通孔插塞44的XY截面形状为椭圆形或四边形。其次，将XY截面形状替换成相同面积的圆。然后，将该圆的直径规定为该Z坐标中的通孔插塞44的插塞径。在本实施方式中，是以通孔插塞44的插塞径对应于与电路芯片2相距的距离而减少，通孔插塞44的上端的插塞径小于通孔插塞44的下端的插塞径的方式，形成通孔插塞44。在通孔插塞44的形状接近于圆柱形的情况下，通孔插塞44的插塞径成为接近于通孔插塞44的宽度W的值。本实施方式的通孔插塞44的插塞径是插塞的直径的例子。
阵列芯片1还具备形成在绝缘膜12及金属焊垫45上的钝化膜46。钝化膜46例如为氧化硅膜或氮化硅膜等绝缘膜。钝化膜46具有使金属焊垫45的上表面露出的开口部P。开口部P例如用来向金属焊垫45连接接合线。本实施方式的开口部P形成于在Z方向上与各通孔插塞44重叠的位置，也就是说，形成在各通孔插塞44的正上方。
图4至图10是表示第1实施方式的半导体装置的制造方法的截面图。
图4表示出了包含多个阵列芯片1的阵列晶圆W1、及包含多个电路芯片2的电路晶圆W2。阵列晶圆W1也称作存储器晶圆，电路晶圆W2也称作CMOS CMOS(Complementary MetalOxide Semiconductor，互补金氧半导体)晶圆。此外，阵列晶圆W1在绝缘膜12下具备衬底18。衬底18例如为硅衬底等半导体衬底。衬底18是第2衬底的例子。
首先，准备图4所示的存储器晶圆W1及电路晶圆W2。图4表示出了与图3对应的截面，但要注意的一点是，图4的存储器晶圆W1的方向与图3的存储器芯片1的方向相反。图4表示出了为了贴合而使方向反转前的存储器晶圆W1，图3表示出了为了贴合而使方向反转并加以贴合及切割后的存储器芯片1。
图4的步骤中，在衬底17上形成晶体管31及层间绝缘膜16，在层间绝缘膜16内形成金属焊垫37等，从而制作出电路晶圆W2。金属焊垫37是通过例如以下所述方法而形成：采用RIE(Reactive Ion Etching，反应式离子蚀刻)在层间绝缘膜16的表面形成凹部，然后向凹部内埋入金属焊垫37。
图4的步骤中，进而在衬底18上隔着绝缘膜12形成存储单元阵列11及层间绝缘膜13，在绝缘膜12或层间绝缘膜13内形成通孔插塞44、配线层43、通孔插塞42及金属焊垫41，从而制作出阵列晶圆W1。金属焊垫41是通过例如以下所述方法而形成：采用RIE在层间绝缘膜16的表面形成凹部，然后向凹部内埋入金属焊垫41。
另外，通孔插塞44是以如下方法形成的。首先，在衬底18上，形成绝缘膜12、及层间绝缘膜13的一部分。其次，采用RIE形成贯通绝缘膜12、及层间绝缘膜13的一部分的贯通孔。结果，贯通孔形成为借由RIE的作用而具有锥形形状的侧面。其次，向贯通孔内埋入通孔插塞44。由此，通孔插塞44形成为具有锥形形状的侧面T，通孔插塞44的宽度W或插塞径被设定为对应于与衬底18相距的距离而增加。其后，在衬底18的上方，形成层间绝缘膜13的剩余部分、配线层43、通孔插塞42及金属焊垫41。
其次，使阵列晶圆W1贴合于电路晶圆W2(图5)。具体来说，首先，使阵列晶圆W1与电路晶圆W2通过机械压力而贴合。由此，层间绝缘膜13黏接于层间绝缘膜16。其次，以250℃～400℃对阵列晶圆W1及电路晶圆W2进行退火。由此，金属焊垫41接合于金属焊垫37，并电连接于金属焊垫37。图5表示出了金属焊垫41配置在金属焊垫37上的情形。
其次，将衬底18从阵列晶圆W1去除(图6)。结果，通孔插塞44露出。衬底18的去除是采用例如CMP(Chemical Mechanical Polishing，化学机械抛光)或湿式蚀刻而进行的。
其次，在绝缘膜12及通孔插塞44上，形成用来形成金属焊垫45的金属层(图7)。在图7中，该金属层也用符号45来表示，以使说明容易理解。其次，采用RIE蚀刻该金属层，而在通孔插塞44上形成金属焊垫45(图8)。
其次，在绝缘膜12及金属焊垫45上，形成钝化膜46(图9)。其次，采用RIE蚀刻钝化膜46，而在钝化膜46内形成使金属焊垫45的上表面露出的开口部P(图10)。
其后，采用CMP使衬底17薄膜化后，将阵列晶圆W1及电路晶圆W2切断(切割)成多个芯片。按照这样的步骤，制造出图3的半导体装置。
按照上文所述，本实施方式的半导体装置是使阵列芯片1(阵列晶圆W1)与电路芯片2(电路晶圆W2)贴合而制造获得。因此，需要将阵列芯片1的金属焊垫41与金属焊垫45电连接。因此，在本实施方式中，贴合前在阵列芯片1内形成通孔插塞44，其后通过通孔插塞44将金属焊垫41与金属焊垫45电连接。由此，能够将通孔插塞44连同存储单元阵列11等一起形成在衬底18上。在本实施方式中，通孔插塞44的宽度W是对应于与电路芯片2相距的距离而减少的，其原因在于，贴合前就形成了通孔插塞44。
另外，本实施方式的阵列芯片1在金属焊垫41与金属焊垫45之间具备多个通孔插塞44。由此，根据本实施方式，与形成1个粗大的通孔插塞时相比，能够节约用来形成通孔插塞44的材料，或能够简单地形成通孔插塞44。在本实施方式中，这种通孔插塞44配置在存储单元阵列11的外部，而非存储单元阵列11的内部。
综上所述，根据本实施方式，能够将采用了贴合技术的半导体装置中接合垫的配置或配线设定为更佳态样。
此外，本实施方式中是使阵列晶圆W1与电路晶圆W2贴合，但也可以取而代之地，使阵列晶圆W1彼此贴合，或使电路晶圆W2彼此贴合。也就是说，作为贴合对象的晶圆可以是任意种类的晶圆。参照图1至图10在上文叙述的内容、或参照图11在下文叙述的内容也适用于使阵列晶圆W1与电路晶圆W2贴合的情况以外的贴合。
另外，图1表示出了绝缘膜14与绝缘膜15的交界面、及金属焊垫41与金属焊垫37的交界面，但是一般来说，在所述退火步骤后，这些交界面便看不到了。然而，这些交界面所处的位置可以通过检测例如金属焊垫41的侧面或金属焊垫37的侧面的倾斜、或者金属焊垫41的侧面与金属焊垫37的位置偏移来加以推定。
(第2实施方式)
图11是表示第2实施方式的半导体装置的构造的截面图。
本实施方式的半导体装置与第1实施方式的半导体装置(图3)同样地，具备金属焊垫45及钝化膜46。但是，本实施方式的金属焊垫45从通孔插塞44的正上方的区域延伸到存储单元阵列11的正上方的区域。此外，本实施方式的开口部P设置于在Z方向上不与通孔插塞44重叠的位置，且设置于在Z方向上与存储单元阵列11重叠的位置。也就是说，本实施方式的开口部P设置在存储单元阵列11的正上方。
本实施方式的半导体装置与第1实施方式的半导体装置同样地，可以通过图4至图10的步骤来制造。但是，图8的步骤是以形成图11所示的形状的金属焊垫45的方式进行的。进而，图10的步骤是以在图11所示的位置形成开口部P的方式进行的。
根据第1实施方式，能够将金属焊垫45的面积设定得较小。而根据本实施方式，能够将开口部P配置在各种位置。开口部P在本实施方式中是设置在存储单元阵列11的正上方，但也可以设置在其他位置。
上面，对若干个实施方式进行了说明，但这些实施方式仅是作为例子而提出，并非是要限定发明的范围。本说明书中所说明的新颖的装置及方法能够以其他各种实施方式来实施。另外，对于本说明书中所说明的装置及方法的实施方式，可以在不脱离发明主旨的范围内，进行各种省略、替换、变更。随附的权利要求书的范围及其均等的范围希望将发明的范围或主旨中包含的这些实施方式及变化例包含在内。
[符号的说明]
1 阵列芯片
2 电路芯片
11 存储单元阵列
12 绝缘膜
13 层间绝缘膜
14 绝缘膜
15 绝缘膜
16 层间绝缘膜
17 衬底
18 衬底
21 阶梯构造部
22 接触插塞
23 字配线层
24 接触插塞
25 源极侧选择栅极配线层
26 接触插塞
27 漏极侧选择栅极配线层
28 插塞
29 接触插塞
30 源极配线层
31 晶体管
32 栅极电极
33 插塞
34 配线层
35 配线层
36 通孔插塞
37 金属焊垫
41 金属焊垫
42 通孔插塞
43 配线层
44 通孔插塞
45 金属焊垫
46 钝化膜
51 绝缘层
52 阻挡绝缘膜
53 电荷储存层，
54 隧道绝缘膜
55 通道半导体层
56 核心绝缘膜

Claims (12)

1.一种半导体装置，具备第1芯片及第2芯片，
该第1芯片具有：
第1衬底；
多个晶体管，设置在所述第1衬底上；
第1焊垫及第2焊垫，设置在所述多个晶体管的上方，且分别电连接于所述多个晶体管；
该第2芯片具有：
第3焊垫，接触设置在所述第1焊垫上；
第4焊垫，接触设置在所述第2焊垫上；
配线，设置在所述第3焊垫及第4焊垫的上方，分别电连接于所述第3焊垫及所述第4焊垫，且使所述第3焊垫与所述第4焊垫电连接；
多个插塞，分别接触设置在所述配线的上方，分别沿着第1方向延伸，且分别包含距离所述第1衬底越远则与所述第1方向正交的截面上的直径越小的部分；及
接合垫，设置在所述多个插塞上，与所述第1方向交叉，且通过所述多个插塞、所述配线、所述第3焊垫及第4焊垫以及所述第1焊垫及第2焊垫而电连接于多个晶体管。
2.根据权利要求1所述的半导体装置，其中
所述第1芯片还包含以第1方向设置在所述第1焊垫与所述多个晶体管之间并且使所述第1焊垫与所述第2焊垫电连接的配线。
3.根据权利要求1所述的半导体装置，其中
所述第1芯片还具备：
第5焊垫，设置在所述多个晶体管的上方，且电连接于所述多个晶体管；
所述第2芯片还具备：
第6焊垫，接触设置在所述第5焊垫上；及
存储单元阵列，通过所述第5焊垫及第6焊垫而电连接于所述多个晶体管。
4.根据权利要求1所述的半导体装置，其中
所述第2芯片还具备设置在所述接合垫上的绝缘膜，且
所述绝缘膜具有使所述接合垫的上表面露出的开口部。
5.根据权利要求4所述的半导体装置，其中
所述开口部设置于在所述第1方向上与所述多个插塞重叠的位置。
6.根据权利要求4所述的半导体装置，其中
所述开口部设置于在所述第1方向上不与所述多个插塞重叠的位置。
7.根据权利要求6所述的半导体装置，其中
所述开口部设置于在所述第1方向上与所述第2芯片内的存储单元阵列重叠的位置。
8.根据权利要求1至7中任一项所述的半导体装置，其中
所述第2芯片内的存储单元阵列具备在所述第1方向上相互分离而积层的多个电极层，且所述多个插塞的所述第1芯片侧的端部设置在比最下层的所述电极层的下表面更低的位置，所述多个插塞的与所述第1芯片相反侧的端部设置在比最上层的所述电极层的上表面更高的位置。
9.根据权利要求1至7中任一项所述的半导体装置，其中
所述第2芯片内的存储单元阵列还具备在所述第1方向上相互分离而积层的多个电极层、及设置在所述多个电极层的最上层的上方的源极线，
所述源极线与所述接合垫在所述第1方向上不重叠。
10.一种半导体装置的制造方法，包含如下所述步骤：
在第1晶圆上形成多个晶体管；
在所述第1晶圆的所述多个晶体管的上方所设置的贴合面，形成电连接于所述多个晶体管的第1焊垫及第2焊垫；
在第2晶圆的上方形成多个插塞，该多个插塞分别沿着第1方向延伸，且分别包含距离所述第2晶圆的上方所设置的贴合面越远则与所述第1方向正交的截面上的直径越小的部分；
形成设置于所述多个插塞的所述贴合面侧的配线，该配线分别接触所述多个插塞的变大的部分的端部；
在所述第2晶圆的所述贴合面，形成接触设置在所述第1焊垫且电连接于所述配线的第3焊垫；
在所述第2晶圆的所述贴合面，形成接触设置在所述第2焊垫且电连接于所述配线的第4焊垫；
以所述第3焊垫及第4焊垫配置在所述第1焊垫及第2焊垫上的方式，使所述第2晶圆贴合于所述第1晶圆；
在经贴合后的所述第2晶圆的与所述贴合面相反的面，使所述多个插塞露出；
在所露出的所述多个插塞上，形成与所述第1方向交叉的接合垫；及
从经贴合后的晶圆切出芯片。
11.根据权利要求10所述的半导体装置的制造方法，还包含如下所述步骤：
在所述贴合步骤后将所述第2晶圆的衬底去除；且
所述衬底被去除后，所述接合垫形成在所述多个插塞上。
12.根据权利要求10或11所述的半导体装置的制造方法，还包含如下所述步骤：
在所述接合垫上，形成具有使所述接合垫的上表面露出的开口部的绝缘膜。
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