CN114203656A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN114203656A
CN114203656A CN202110117503.7A CN202110117503A CN114203656A CN 114203656 A CN114203656 A CN 114203656A CN 202110117503 A CN202110117503 A CN 202110117503A CN 114203656 A CN114203656 A CN 114203656A
Authority
CN
China
Prior art keywords
insulating film
substrate
semiconductor device
opening
plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110117503.7A
Other languages
English (en)
Inventor
冨松孝宏
荒井伸也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Publication of CN114203656A publication Critical patent/CN114203656A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/09181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80095—Temperature settings
    • H01L2224/80096—Transient conditions
    • H01L2224/80097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80905—Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
    • H01L2224/80906—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/145—Read-only memory [ROM]
    • H01L2924/1451—EPROM
    • H01L2924/14511—EEPROM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

实施方式提供可以较适宜的形态将接合垫电连接到通孔插塞的半导体装置及其制造方法。根据一实施方式，半导体装置具备第1衬底、及设置在所述第1衬底上的第1绝缘膜。所述装置还具备：第1插塞，设置在所述第1绝缘膜内；及第2衬底，设置在所述第1绝缘膜上。所述装置还具备第1布线，所述第1布线包含：第1部分，设置在所述第2衬底内，设置在所述第1插塞上；及第2部分，设置在所述第2衬底上，包含接合垫，以与所述第1部分的材料相同的材料形成。

Description

半导体装置及其制造方法
[相关申请案]
本申请案享有以日本专利申请案第2020-156645号(申请日：2020年9月17日)为基础申请案的优先权。本申请案通过参考所述基础申请案而包含基础申请案的所有内容。
技术领域
本发明的实施方式涉及半导体装置及其制造方法。
背景技术
在衬底上形成通孔插塞与接合垫的情况下，期望以较适宜的形态将接合垫电连接到通孔插塞。
发明内容
实施方式提供可以较适宜的形态将接合垫电连接到通孔插塞的半导体装置及其制造方法。
根据一实施方式，半导体装置具备第1衬底、及设置在所述第1衬底上的第1绝缘膜。所述装置还具备：第1插塞，设置在所述第1绝缘膜内；及第2衬底，设置在所述第1绝缘膜上。所述装置还具备第1布线，所述第1布线包含：第1部分，设置在所述第2衬底内，设置在所述第1插塞上；及第2部分，设置在所述第2衬底上，包含接合垫，以与所述第1部分的材料相同的材料形成。
附图说明
图1是表示第1实施方式的半导体装置的构造的剖视图。
图2是表示第1实施方式的各柱状部的构造的剖视图。
图3(a)、(b)是用以比较第1实施方式的半导体装置与其比较例的半导体装置的剖视图。
图4(a)、(b)、图5(a)、(b)、图6(a)、(b)、图7(a)、(b)、图8(a)、(b)、图9(a)、(b)是表示第1实施方式的半导体装置的制造方法的剖视图。
具体实施方式
以下，参照附图说明本发明的实施方式。图1到图9中，对相同构成附注相同符号，省略重复的说明。
(第1实施方式)
图1是表示第1实施方式的半导体装置的构造的剖视图。图1的半导体装置是将阵列芯片1与电路芯片2加以贴合的3维存储器。
图1表示互相垂直的X方向、Y方向及Z方向。本说明书中，将+Z方向作为上方向处理，将-Z方向作为下方向处理。-Z方向可与重力方向一致，也可不与重力方向一致。
阵列芯片1具备包含多个存储单元的存储单元阵列11、存储单元阵列11上的衬底12、及存储单元阵列11下的层间绝缘膜13。衬底12例如为硅衬底等半导体衬底。图1表示形成在衬底12内的阱(well)区域12a。层间绝缘膜13例如为氧化硅膜、或包含氧化硅膜与其他绝缘膜的积层膜。衬底12为第2衬底的例子。层间绝缘膜13为第1绝缘膜的例子。
电路芯片2设置在阵列芯片1下。图1表示阵列芯片1与电路芯片2的贴合面S。电路芯片2具备层间绝缘膜14、层间绝缘膜14下的衬底15。层间绝缘膜14例如为氧化硅膜、或包含氧化硅膜与其他绝缘膜的积层膜。衬底15例如为硅衬底等半导体衬底。层间绝缘膜14与层间绝缘膜13同为第1绝缘膜的例子。衬底15为第1衬底的例子。
阵列芯片1具备多条字线WL作为存储单元阵列11内的电极层。图1表示存储单元阵列11内的台阶构造部21。各字线WL经由接触插塞22及通孔插塞23与字布线层WI电连接。图1中还表示出贯通所述多条字线WL的多个柱状部CL中的一个。各柱状部CL经由通孔插塞24与位线BL电连接。
电路芯片2具备多个晶体管31。图1表示所述晶体管31中的一个。各晶体管31具备介隔栅极绝缘膜设置在衬底15上的栅极电极32、及设置在衬底15内的未图示的源极扩散层及漏极扩散层。另外，电路芯片2还具备：多个接触插塞33，设置在所述晶体管31的栅极电极32、源极扩散层或者漏极扩散层上；布线层34，设置在所述接触插塞33上，包含多条布线；及多个通孔插塞35，设置在布线层34上。
电路芯片2还具备：布线层36，设置在所述通孔插塞35上，包含多条布线；多个通孔插塞37，设置在布线层36上；及多个金属焊垫38，设置在所述通孔插塞37上。金属焊垫38例如为包含Cu层或Al层的金属层(Cu表示铜，Al表示铝)。电路芯片2作为控制阵列芯片1的动作的控制电路(逻辑电路)发挥作用。所述控制电路由晶体管31等构成，电连接到金属焊垫38。
阵列芯片1具备：多个金属焊垫41，设置在金属焊垫38上；及多个通孔插塞42，设置在金属焊垫41上。另外，阵列芯片1具备：布线层43，设置在所述通孔插塞42上，包含多条布线；及多个通孔插塞44，设置在布线层43上。金属焊垫41例如为包含Cu层或Al层的金属层。所述位线BL或字布线层WI包含在布线层43内。另外，所述控制电路经由金属焊垫41、38等电连接到存储单元阵列11，经由金属焊垫41、38等控制存储单元阵列11的动作。
阵列芯片1还具备设置在所述多个通孔插塞44上的多个通孔插塞45。图1表示所述通孔插塞45中的2个。通孔插塞45设置在层间绝缘膜13内，设置在存储单元阵列11的侧方。通孔插塞45例如为包含W层的金属层(W表示钨)。通孔插塞45为第1插塞的例子。
阵列芯片1还具备依序形成在衬底12上的绝缘膜46、绝缘膜47及金属布线48。绝缘膜46为例如氧化硅膜。绝缘膜47为例如氧化硅膜。金属布线48为例如包含Al层的金属层。绝缘膜46为第2绝缘膜或第1膜的例子。绝缘膜47为第2绝缘膜或第2膜的例子。金属布线48为第1布线的例子。
绝缘膜47包含：侧方部47a，形成在衬底12及绝缘膜46的侧面；上方部47b，形成在绝缘膜46的上表面；及埋入部47c，埋入到衬底12及绝缘膜46内。侧方部47a及埋入部47c形成在衬底12及绝缘膜46的内部，上方部47b形成在衬底12及绝缘膜46的外部。本实施方式中，侧方部47a作为衬底12及绝缘膜46的侧面的侧壁绝缘膜发挥作用，埋入膜47c作为衬底12及绝缘膜46内的元件分离绝缘膜发挥作用。本实施方式的埋入部47c包含将埋入部47埋入到衬底12及绝缘膜46内时形成的气隙AG。侧方部47a为第3部分的例子。埋入部47c为与第3部分不同的第4部分的例子。
金属布线48包含：上方部48a，形成在层间绝缘膜13及所述多个通孔插塞45的上表面；侧方部48b，形成在绝缘膜47的侧面；及上方部48c，形成在绝缘膜47的上表面。金属布线48电连接到所述多个通孔插塞45。上方部48a及侧方部48b形成在衬底12、绝缘膜46及绝缘膜47的内部，上方部48c形成在衬底12、绝缘膜46及绝缘膜47的外部。因本实施方式的上方部48a、侧方部48b及上方部48c由相同的布线层同时形成，所以用相同的材料(例如铝)形成。本实施方式的上方部48a、侧方部48b及上方部48c形成连续的1条布线。上方部48a及侧方部48b为第1部分的例子。上方部48c为第2部分的例子。
阵列芯片1还具备形成在绝缘膜47及金属布线48上的钝化膜49。钝化膜49为第3绝缘膜的例子。
钝化膜49包含依序形成在绝缘膜47及金属布线48上的绝缘膜49a、绝缘膜49b、及绝缘膜49c。绝缘膜49a为例如氧化硅膜。绝缘膜49b为例如氮化硅膜。绝缘膜49c为例如聚酰亚胺膜。本实施方式的钝化膜49如图1所示包含介隔绝缘膜47(侧方部47a)与金属布线48(侧方部48a)形成在衬底12及绝缘膜46内的部分。
钝化膜49例如具有使金属层48的上方部48c的上表面露出的开口部P。在开口部P内露出的上方部48c作为图1的半导体装置的外部连接垫(接合垫)发挥作用。上方部48c可经由开口部P利用接合线、焊料球、金属凸块等连接到安装衬底或其他装置。
本实施方式的金属布线48包含：上方部48a，设置在所述多个通孔插塞45上；及上方部48c，包含接合垫；所述金属布线48作为电连接所述通孔插塞45与接合垫的连接布线发挥作用。与所述1条金属布线48电连接的通孔插塞45的个数可为任意个，例如为100～10000个。
阵列芯片1内的存储单元阵列11包含与所述多条字线WL交替积层的多个绝缘层51。绝缘层51例如为氧化硅膜。
阵列芯片1内的各柱状部CL包含存储器绝缘膜52、通道半导体层53、核心绝缘膜54、半导体层55及半导体层56。存储器绝缘膜52、通道半导体层53、及核心绝缘膜54依序形成在字线WL及绝缘层51内。半导体层55形成在通道半导体层53上，电连接通道半导体层53与衬底12。半导体层56在核心绝缘膜54下形成在通道半导体层53的侧面，电连接通道半导体层53与通孔插塞24。
图2是表示第1实施方式的各柱状部CL的构造的剖视图。图2相当于图1的剖视图的放大图。
如图2所示，存储器绝缘膜52包含依序形成在字线WL及绝缘层51内的阻挡绝缘膜52a、电荷蓄积层52b、及穿隧绝缘膜52c。阻挡绝缘膜52a、穿隧绝缘膜52c、及核心绝缘膜54例如为氧化硅膜或金属绝缘膜。电荷蓄积层52b例如为氮化硅膜。电荷蓄积层52b也可为多晶硅层等半导体层。通道半导体层53、半导体层55(图1)及半导体层56(图1)例如为多晶硅层或单晶硅层。
图3是用于比较第1实施方式的半导体装置及其比较例的半导体装置的剖视图。
图3(a)表示比较例的半导体装置的构造。比较例的半导体装置具有与本实施方式的半导体装置大致相同的构造。但是，比较例中，在所述多个通孔插塞45上形成着多个通孔插塞61，在所述通孔插塞61上形成着金属布线48的上方部48c。比较例的金属布线48不具备上方部48a或侧方部48b。
图3(a)所示的通孔插塞61与金属布线48例如以如下方式形成。首先，在衬底12内形成多个通孔，在所述通孔内露出多个通孔插塞45。接着，在所述通孔内介隔绝缘膜47形成通孔插塞61，在通孔插塞45上配置通孔插塞61。接着，在通孔插塞61上形成金属布线48。
另一方面，图3(b)表示第1实施方式的半导体装置的构造。图3(b)所示的金属布线48例如以如下方式形成。首先，在衬底12内形成1个开口部，在所述开口部内露出多个通孔插塞45。接着，跨及所述开口部的内部与外部形成金属布线48，在通孔插塞45上形成金属布线48。
比较例中，为了将接合垫(金属布线48的上方部48c)电连接到通孔插塞45，需要进行形成通孔的步骤、形成通孔插塞61的步骤、及形成金属布线48的步骤。另一方面，根据本实施方式，通过进行形成开口部的步骤与形成金属布线48的步骤，可将接合垫(金属布线48的上方部48c)电连接到通孔插塞45。如此，根据本实施方式，可省略形成通孔插塞61的步骤，由此，可削减半导体装置的制造步骤数、制造成本。
另外，比较例的所述通孔的长宽比较高，相对于此，本实施方式的所述开口部的长宽比降低。因此，根据本实施方式，可在衬底12内同时形成所述开口部与元件分离槽，由此，可进一步削减半导体装置的制造步骤数、制造成本。
本实施方式中，在所述元件分离槽内埋着元件分离绝缘膜(绝缘膜47的埋入部47c)。根据本实施方式，可与所述开口部的侧面的侧壁绝缘膜(绝缘膜47的侧方部47a)同时形成所述元件分离绝缘膜，由此，可进一步削减半导体装置的制造步骤数、制造成本。
另外，比较例的金属布线48经由通孔插塞61电连接到通孔插塞45，相对于此，本实施方式的金属布线48不经由其他层电连接到通孔插塞45。因此，根据本实施方式，可降低通孔插塞45与金属布线48间的电阻，由此，可降低通孔插塞45与接合垫间的电阻。
图4到图9是表示第1实施方式的半导体装置的制造方法的剖视图。本实施方式的半导体装置如后文所述，通过将包含多个阵列芯片1的阵列晶圆W1、与包含多个电路芯片2的电路晶圆W2贴合而制造。
首先，准备衬底12，在衬底12内形成阱区域12a(图4(a))。图4(a)表示衬底12内的阱区域12a与其他区域12b。接着，在衬底12上形成存储单元阵列11、层间绝缘膜13、通孔插塞45、通孔插塞44、布线层43、通孔插塞42、金属焊垫41等(图4(a))。图4(a)中还表示出存储单元阵列11中所含的字线WL、绝缘层51、柱状部CL、台阶构造部21等。例如，多个通孔插塞45在层间绝缘膜13内形成在衬底12(阱区域12a)上。如此，制造出阵列晶圆W1。图4(a)表示阵列晶圆W1的上表面S1。
接着，准备衬底15，在衬底15上形成层间绝缘膜14、晶体管31、栅极电极32、接触插塞33、布线层34、通孔插塞33、布线层36、通孔插塞37、金属焊垫38等(图4(b))。如此，制造出电路晶圆W2。图4(b)表示电路晶圆W2的上表面S2。
接着，将阵列晶圆W1与电路晶圆W2贴合(图5(a))。具体而言，将衬底12与衬底15介隔存储单元阵列11、层间绝缘膜13、层间绝缘膜14、晶体管31、通孔插塞45等贴合。图5(a)中，使阵列晶圆W1的上下方向翻转，将阵列晶圆W1贴合到电路晶圆W2上。结果，将衬底12配置到衬底15的上方。所述贴合步骤中，层间绝缘膜13与层间绝缘膜14通过机械压力而接着，金属焊垫41与金属焊垫38通过退火而接合。
接着，通过湿式蚀刻使衬底12薄膜化(图5(b))。结果，衬底12的厚度变薄。图5(b)中，衬底12内的阱区域12a在薄膜化后仍保留，衬底12内的其他区域12b通过薄膜化而去除。
接着，在衬底12上形成绝缘膜46(图6(a))。接着，利用RIE(Reactive IonEtching：反应离子蚀刻)来蚀刻绝缘膜46及衬底12(图6(b))。结果，在绝缘膜46及衬底12内形成开口部H1，在开口部H1内露出层间绝缘膜13与所述多个通孔插塞45。此外，在绝缘膜46及衬底12内形成开口部H2，在开口部H2内露出层间绝缘膜13。本实施方式的开口部H2为元件分离槽。图6(b)的步骤中，利用所述RIE同时形成开口部H1与开口部H2。开口部H1为第1开口部的例子。开口部H2为与第1开口部不同的第2开口部的例子。绝缘膜46为第1膜的例子。
接着，在衬底12的整面形成绝缘膜47(图7(a))。结果，在绝缘膜46、衬底12、层间绝缘膜13、及通孔插塞45的表面形成绝缘膜47。具体而言，开口部H1的侧面及底面被绝缘膜47覆盖，开口部H2被绝缘膜47填满。本实施方式中，利用图7(a)的步骤，在开口部H2内的绝缘膜47内形成气隙AG。接着，在衬底12的整面形成抗蚀剂层71，并从开口部H1的底面起去除抗蚀剂层71(图7(a))。
接着，使用抗蚀剂层71作为掩模，利用RIE蚀刻绝缘膜47(图7(b))。结果，从开口部H1的底面起去除绝缘膜47，在开口部H1内再次露出层间绝缘膜13与所述多个通孔插塞45。此外，将绝缘膜47加工成包含以下三部分的形状，所述三部分是指开口部H1的侧面的侧方部47a、绝缘膜46的上表面的上方侧47b、及开口部H2内的埋入部47c。本实施方式中，侧方部47a作为侧壁绝缘膜发挥作用，埋入膜47c作为元件分离绝缘膜发挥作用。如此，根据本实施方式，可同时形成侧壁绝缘膜与元件分离绝缘膜。绝缘膜47为第2膜的例子。
接着，在衬底12的整面，形成作为金属布线48的材料的金属布线层48(图8(a))。结果，在绝缘膜47、层间绝缘膜13及通孔插塞45的表面形成金属布线层48。具体而言，开口部H1的侧面介隔绝缘膜47而被金属布线层48覆盖，开口部H1的底面被金属布线层48覆盖。金属布线层48例如为包含Al层的金属层。接着，在衬底12的整面形成抗蚀剂层72，其后去除抗蚀剂层72的一部分(图8(a))。
接着，使用抗蚀剂层72作为掩模，利用RIE蚀刻金属布线层48(图8(b))。结果，金属布线层48被加工成包含开口部H1的底面的上方部48a、开口部H1的侧面的侧方部48b、及绝缘膜47的上表面的上方部48c这三个部分。因上方部48a形成在所述多个通孔插塞45上，所以金属布线48电连接到所述通孔插塞45。因本实施方式的上方部48a、侧方部48b及上方部48c由相同的金属布线层48同时形成，所以可由相同材料(例如铝)形成。本实施方式的上方部48a、侧方部48b及上方部48c形成连续的1条布线。
接着，在衬底12的整面，依序形成钝化膜49的绝缘膜49a、49b、49c(图9(a))。结果，在绝缘膜47及金属布线48的表面形成钝化膜49。本实施方式的钝化膜49包含介隔绝缘膜47(侧方部47a)与金属布线48(侧方部48a)形成在开口部H1内的部分。
接着，去除上方部48c的上表面的钝化膜49的一部分(图9(b))。结果，在钝化膜49内形成开口部P。在开口部P内，露出上方部48c的上表面。开口部P内露出的上方部48c作为接合垫发挥作用。因此，本实施方式的金属布线48包含与通孔插塞45相接的部分、及作为接合垫发挥作用的部分这两部分。
其后，利用切割器将阵列晶圆W1及电路晶圆W2切断成多个芯片。所述芯片以各芯片包含1个阵列芯片1与1个电路芯片2的方式被切断。如此，制造出图1的半导体装置。
如以上所述，本实施方式的金属布线48包含设置在通孔插塞45上的上方部48a、及包含接合垫的上方部48c。因此，根据本实施方式，可以较适宜的形态将接合垫电连接到通孔插塞45。例如，可不使用如比较例那样的通孔插塞61而将接合垫电连接到通孔插塞45，可减低接合垫与通孔插塞45间的电阻。由此，可削减半导体装置的制造步骤数、制造成本。
以上，已说明若干实施方式，但所述实施方式是仅作为例子而提示的，并非旨在限定发明范围。本说明书中说明的新颖的装置及方法可以其他各种形态实施。另外，对于本说明书中说明的装置及方法的形态可在不脱离发明主旨的范围内进行各种省略、置换、变更。附加的专利申请范围及与其均等的范围旨在包含发明范围及主旨所含的此种形态或变化例。
[符号的说明]
1 阵列芯片
2 电路芯片
11 存储器单元阵列
12 衬底
12a 阱区域
12b 其他区域
13 层间绝缘膜
14 层间绝缘膜
15 衬底
21 台阶构造部
22 接触插塞
23 通孔插塞
24 通孔插塞
31 晶体管
32 栅极电极
33 接触插塞
34 布线层
35 通孔插塞
36 布线层
37 通孔插塞
38 金属焊垫
41 金属焊垫
42 通孔插塞
43 布线层
44 通孔插塞
45 通孔插塞
46 绝缘膜
47 绝缘膜
47a 侧方部
47b 上方部
47c 埋入部
48 金属布线/金属布线层
48a 上方部
48b 侧方部
48c 上方部
49 钝化膜
49a 绝缘膜
49b 绝缘膜
49c 绝缘膜
51 绝缘层
52 存储器绝缘膜
52a 阻挡绝缘膜
52b 电荷蓄积层
52c 穿隧绝缘膜
53 通道半导体层
54 核心绝缘膜
55 半导体层
56 半导体层
61 通孔插塞
71 抗蚀剂层
72 抗蚀剂层。

Claims (12)

1.一种半导体装置，其特征在于具备：
第1衬底；
第1绝缘膜，设置在所述第1衬底上；
第1插塞，设置在所述第1绝缘膜内；
第2衬底，设置在所述第1绝缘上；及
第1布线，包含：第1部分，设置在所述第2衬底内，设置在所述第1插塞上；及第2部分，设置在所述第2衬底上，包含接合垫，以与所述第1部分的材料相同的材料形成。
2.根据权利要求1所述的半导体装置，其特征在于还具备：
第2绝缘膜，设置在所述第2衬底上；且
所述第1部分设置在所述第2衬底及所述第2绝缘膜内，
所述第2部分介隔所述第2绝缘膜设置在所述第2衬底上。
3.根据权利要求2所述的半导体装置，其特征在于
所述第2绝缘膜包含：第3部分，设置在所述第2衬底内，设置在所述第2衬底与所述第1部分之间；及第4部分，设置在所述第2衬底内，与所述第3部分不同。
4.根据权利要求3所述的半导体装置，其特征在于所述第4部分包含气隙。
5.根据权利要求1到4中任一项所述的半导体装置，其特征在于还具备：
第3绝缘膜，设置在所述第1布线上；
所述第3绝缘膜包含设置在所述第2衬底内的部分。
6.根据权利要求5所述的半导体装置，其特征在于所述接合垫在设置于所述第3绝缘膜内的开口部内露出。
7.根据权利要求1到4中任一项所述的半导体装置，其特征在于
具备多个插塞作为所述第1插塞，
具备设置在所述多个插塞上的1条布线，作为所述第1布线。
8.一种半导体装置的制造方法，其特征在于包含：
准备第1衬底与第2衬底；
在所述第2衬底上形成第1绝缘膜；
在所述第1绝缘膜内形成第1插塞；
将所述第1衬底与所述第2衬底介隔所述第1绝缘膜及所述第1插塞贴合，在所述第1衬底的上方配置所述第2衬底；
在所述第2衬底内形成第1开口部，在所述第1开口部内，使所述第1插塞露出；
形成第1布线，所述第1布线包含：第1部分，设置在所述第1开口部内，设置在所述第1插塞上；第2部分，设置在所述第2衬底上，包含接合垫，以与所述第1部分的材料相同的材料形成。
9.根据权利要求8所述的半导体装置的制造方法，其特征在于，所述第1布线介隔第2绝缘膜形成在所述第2衬底上。
10.根据权利要求9所述的半导体装置的制造方法，其特征在于还包含：在所述第2衬底内，形成与所述第1开口部不同的第2开口部，
所述第2绝缘膜包含：第3部分，设置在所述第1开口部内；及第4部分，设置在所述第2开口部内。
11.根据权利要求10所述的半导体装置的制造方法，其特征在于
所述第2绝缘膜包含：
第1膜，在形成所述第1及第2开口部前，形成在所述第2衬底上；及
第2膜，在形成所述第1及第2开口部后，形成在所述第1膜上与所述第1及第2开口部内。
12.根据权利要求8到11中任一项所述的半导体装置的制造方法，其特征在于还包含：在所述第1布线上形成第3绝缘膜，
所述第3绝缘膜包含设置在所述第1开口部内的部分。
CN202110117503.7A 2020-09-17 2021-01-28 半导体装置及其制造方法 Pending CN114203656A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020156645A JP2022050185A (ja) 2020-09-17 2020-09-17 半導体装置およびその製造方法
JP2020-156645 2020-09-17

Publications (1)

Publication Number Publication Date
CN114203656A true CN114203656A (zh) 2022-03-18

Family

ID=80627003

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110117503.7A Pending CN114203656A (zh) 2020-09-17 2021-01-28 半导体装置及其制造方法

Country Status (4)

Country Link
US (2) US11562976B2 (zh)
JP (1) JP2022050185A (zh)
CN (1) CN114203656A (zh)
TW (1) TWI782400B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022044428A (ja) * 2020-09-07 2022-03-17 キオクシア株式会社 半導体記憶装置及び半導体記憶装置の製造方法
KR20220053733A (ko) * 2020-10-22 2022-05-02 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 전자 시스템 및 이의 제조 방법
JP2022128770A (ja) * 2021-02-24 2022-09-05 キオクシア株式会社 半導体記憶装置
JP2022142498A (ja) * 2021-03-16 2022-09-30 キオクシア株式会社 半導体記憶装置および半導体記憶装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5376916B2 (ja) 2008-11-26 2013-12-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6203152B2 (ja) * 2014-09-12 2017-09-27 東芝メモリ株式会社 半導体記憶装置の製造方法
JP2020145351A (ja) * 2019-03-07 2020-09-10 キオクシア株式会社 半導体装置およびその製造方法
JP2020150037A (ja) 2019-03-11 2020-09-17 キオクシア株式会社 半導体装置およびその製造方法
US11211370B2 (en) * 2020-01-28 2021-12-28 Sandisk Technologies Llc Bonded assembly with vertical power and control signal connection adjacent to sense amplifier regions and methods of forming the same
US11444039B2 (en) * 2020-05-29 2022-09-13 Sandisk Technologies Llc Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same

Also Published As

Publication number Publication date
JP2022050185A (ja) 2022-03-30
TW202213554A (zh) 2022-04-01
US11562976B2 (en) 2023-01-24
US20220084970A1 (en) 2022-03-17
US20230129339A1 (en) 2023-04-27
TWI782400B (zh) 2022-11-01

Similar Documents

Publication Publication Date Title
US20210074658A1 (en) Semiconductor device
CN111681988B (zh) 半导体装置及其制造方法
US11626376B2 (en) Semiconductor device having a plurality of first structural bodies provided below a connection terminal and manufacturing method thereof
TWI814591B (zh) 半導體裝置
CN114203656A (zh) 半导体装置及其制造方法
US11594514B2 (en) Semiconductor device and method of manufacturing the same
JP2021150601A (ja) 半導体ウェハおよびその製造方法
CN111668206A (zh) 半导体装置及其制造方法
CN113380781A (zh) 半导体装置及其制造方法
TWI776181B (zh) 半導體裝置及半導體裝置的製造方法
US11769747B2 (en) Semiconductor device and method of manufacturing the same
US11152334B2 (en) Semiconductor device and method of manufacturing the same
CN112510011B (zh) 半导体装置及其制造方法
CN115732458A (zh) 半导体装置及衬底
CN115084156A (zh) 半导体存储装置以及半导体存储装置的制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination