CN115084156A - 半导体存储装置以及半导体存储装置的制造方法 - Google Patents
半导体存储装置以及半导体存储装置的制造方法 Download PDFInfo
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- CN115084156A CN115084156A CN202110911950.XA CN202110911950A CN115084156A CN 115084156 A CN115084156 A CN 115084156A CN 202110911950 A CN202110911950 A CN 202110911950A CN 115084156 A CN115084156 A CN 115084156A
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Abstract
本发明提供半导体存储装置以及半导体存储装置的制造方法,能够实现电气特性的提高。实施方式的半导体存储装置具有第1基板、第2基板、第1层叠体以及第2层叠体。上述第1层叠体设置在上述第1基板与上述第2基板之间,包括第1布线、与上述第1布线连接的第1焊盘、以及第1绝缘体。上述第2层叠体设置在上述第1层叠体与上述第2基板之间,包括第2布线、与上述第2布线连接的第2焊盘、以及第2绝缘体。上述第1焊盘包括分别与上述第1布线连接的多个第1电极部。在上述多个第1电极部之间设置有上述第1绝缘体。上述多个第1电极部与上述第2焊盘接合。
Description
本申请享受以日本专利申请2021-042688号(申请日:2021年3月16日)为基础申请的优先权。本申请通过参照该基础申请而包含该基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体存储装置以及半导体存储装置的制造方法。
背景技术
已知有通过对多个晶片彼此进行粘接而制造的半导体存储装置。
发明内容
本发明要解决的课题在于,提供能够实现电气特性的提高的半导体存储装置以及半导体存储装置的制造方法。
实施方式的半导体存储装置具有第1基板、第2基板、第1层叠体以及第2层叠体。上述第2基板在上述第1基板的厚度方向即第1方向上从上述第1基板分离。上述第1层叠体设置在上述第1基板与上述第2基板之间,包括第1布线、与上述第1布线连接的第1焊盘、以及第1绝缘体。上述第2层叠体设置在上述第1层叠体与上述第2基板之间,包括第2布线、与上述第2布线连接的第2焊盘、以及第2绝缘体。上述第1焊盘包括在与上述第1方向交叉的第2方向上相互分离且分别与上述第1布线连接的多个第1电极部。在上述多个第1电极部之间设置有上述第1绝缘体。上述多个第1电极部与上述第2焊盘接合。
附图说明
图1是表示实施方式的半导体存储装置的构成的截面图。
图2是表示实施方式的存储元件阵列的存储柱附近的截面图。
图3是表示实施方式的多个接合焊盘的截面图。
图4是表示实施方式的接合焊盘的图。
图5是表示实施方式的第1层叠体与第2层叠体粘接时的第1层叠体的电极部以及第2层叠体的电极部的状态的截面图。
图6是表示实施方式的半导体存储装置的制造方法的截面图。
图7是表示实施方式的半导体存储装置的制造方法的截面图。
图8是表示实施方式的半导体存储装置的制造方法的截面图。
图9是表示实施方式的半导体存储装置的制造方法的截面图。
图10是表示实施方式的变形例的半导体存储装置的截面图。
图11是将图10所示的由F11线包围的区域放大表示的截面图。
图12是表示实施方式的第1实施例的多个电极部的形状的截面图。
图13是表示实施方式的第2实施例的多个电极部的形状的截面图。
图14是表示实施方式的第3实施例的多个电极部的形状的截面图。
图15是表示实施方式的第4实施例的多个电极部的形状的截面图。
图16是表示实施方式的第5实施例的多个电极部的形状的截面图。
图17是表示实施方式的第6实施例的多个电极部的形状的截面图。
图18是表示实施方式的第7实施例的多个电极部的形状的截面图。
图19是表示实施方式的第8实施例的多个电极部的形状的截面图。
图20是表示实施方式的第9实施例的多个电极部的形状的截面图。
符号的说明
1:半导体存储装置;10:第1基板;30:第1层叠体;35:第1绝缘体;37:布线(第1布线);38:接合焊盘(第1焊盘);40:第2层叠体;45:第2绝缘体;47:布线(第2布线);48:接合焊盘(第2焊盘);81:电极部(第1电极部);82:电极部(第2电极部);101:保护层;R:焊盘区域。
具体实施方式
以下,参照附图对实施方式的半导体存储装置进行说明。在以下的说明中,对具有相同或者类似功能的构成标注相同的符号。并且,有时省略这些构成的重复说明。“连接”并不限定于物理地连接的情况,也包括电连接的情况。即,“连接”并不限定于直接连接的情况,也包括夹设其他部件的情况。“环状”并不限定于圆环状,也包括矩形状的环状。“平行”、“正交”、“相同”也分别包括“大致平行”、“大致正交”、“大致相同”的情况。
首先,定义X方向、Y方向、+Z方向以及-Z方向。X方向以及Y方向是沿着后述的第1基板10(参照图1)的表面10a的方向。Y方向是与X方向交叉(例如正交)的方向。+Z方向以及-Z方向是与X方向以及Y方向交叉(例如正交)的方向,且是第1基板10的厚度方向。+Z方向是从第1基板10朝向第2基板60(参照图1)的方向。-Z方向是与+Z方向相反的方向。在不区分+Z方向与-Z方向的情况下,简称为“Z方向”。在以下的说明中,有时将“+Z方向”称作“上”、将“-Z方向”称作“下”。但是,这些表现是为了便于说明,并不对重力方向进行规定。Z方向是“第1方向”的一例。X方向和Y方向中的任一方是“第2方向”的一例。X方向和Y方向中的另一方是“第3方向”的一例。
(实施方式)
<1.半导体存储装置的整体构成>
首先,对实施方式的半导体存储装置1的整体构成进行说明。半导体存储装置1是非易失性的半导体存储装置,例如是NAND型闪存器。
图1是表示半导体存储装置1的构成的截面图。半导体存储装置1例如是电路芯片2与阵列芯片3通过粘接面S粘接而成的三维存储器。电路芯片2是“第1芯片”的一例。阵列芯片3是“第2芯片”的一例。电路芯片2包括对阵列芯片3的动作进行控制的控制电路(逻辑电路)。以下,对这样的半导体存储装置1进行详细说明。
半导体存储装置1例如具备第1基板10、层叠体20、第2基板60以及绝缘层72、73。
第1基板10是包含于电路芯片2的基板。第1基板10例如是硅基板。第1基板10具有供层叠体20层叠的表面10a。在第1基板10上设置有层叠体20中所包含的晶体管31(后述)的源极区域以及漏极区域。
层叠体20在Z方向上位于第1基板10与第2基板60之间。层叠体20包括第1层叠体30以及第2层叠体40。第1层叠体30设置在第1基板10上。第1层叠体30在Z方向上位于第1基板10与第2层叠体40之间。在本实施方式中,由第1基板10和第1层叠体30构成电路芯片2。第1层叠体30包括多个晶体管31(在图1中仅图示一个)、多个接触插塞32、多条布线33、多个焊盘34以及第1绝缘体35。
晶体管31设置在第1基板10上。晶体管31与接触插塞32连接。晶体管31经由层叠体20中所包含的接触插塞32、42、布线33、43以及焊盘34、44,与存储元件阵列41或者外部连接焊盘71电连接。晶体管31例如对存储元件阵列41进行控制。
接触插塞32、布线33以及焊盘34将多个晶体管31与第2层叠体40电连接。接触插塞32、布线33以及焊盘34由铜(Cu)或者铝(Al)那样的导电材料形成。接触插塞32是沿着Z方向延伸,将第1层叠体30内的不同层之间电连接的布线。布线33是沿着X方向或者Y方向延伸的布线。
焊盘34是设置于第1层叠体30的连接用的电极。焊盘34包括设置在第1层叠体30内部的内部焊盘、以及在第1层叠体30的表面(粘接面S)上露出的接合焊盘38。接合焊盘38是“第1焊盘”的一例。多条布线33中的与接合焊盘38连接的布线37是“第1布线”的一例。对于接合焊盘38将在后面详细叙述。
第1绝缘体35设置于多个接触插塞32、多条布线33以及多个焊盘34之间,将这些要素相互电绝缘。第1绝缘体35例如由TEOS(原硅酸四乙酯(Si(OC2H5)4)、硅氧化物(SiO2)或者硅氮化物(SiN)等形成。
第2层叠体40设置在第1层叠体30上。第2层叠体40在Z方向上位于第1层叠体30与第2基板60之间。在本实施方式中,由第2基板60和第2层叠体40构成阵列芯片3。第2层叠体40包括存储元件阵列41、多个接触插塞42、多条布线43、多个焊盘44以及第2绝缘体45。
存储元件阵列41设置在第2基板60的下方。存储元件阵列41在制造时层叠在第2基板60上(参照图8)。存储元件阵列41具有多个导电层51以及多个存储柱(memory pillar)P。多个导电层51以及多个存储柱P分别与接触插塞42连接。
多个导电层51例如由掺杂有钨(W)或者杂质的多晶硅(Poly-Si)形成。多个导电层51夹着第2绝缘体45所包含的层间绝缘膜45b(参照图2)而在Z方向上层叠。多个导电层51中的第1层叠体30侧(-Z方向侧)的一个或者两个导电层51作为漏极侧选择栅极线SGD发挥功能。多个导电层51中的第2基板60侧(+Z方向侧)的一个或者两个导电层51作为源极侧选择栅极线SGS发挥功能。多个导电层51中的位于漏极侧选择栅极线SGD与源极侧选择栅极线SGS之间的剩余的导电层51作为多条字线WL发挥功能。
多个存储柱P沿着Z方向延伸,并贯通漏极侧选择栅极线SGD、多条字线WL以及源极侧选择栅极线SGS。在多条字线WL与多个存储柱P之间的交叉部分分别形成有存储元件MC。由此,多个存储元件MC在X方向、Y方向以及Z方向上隔开间隔而配置为三维状。对于存储元件MC将在后面详细叙述。
接触插塞42、布线43以及焊盘44将存储元件阵列41或者后述的外部连接焊盘71与第1层叠体30电连接。接触插塞42、布线43以及焊盘44由铜或者铝那样的导电材料形成。接触插塞42是沿着Z方向延伸,将第2层叠体40内的不同层之间电连接的布线。布线43是沿着X方向或者Y方向延伸的布线。
焊盘44是设置于第2层叠体40的连接用的电极。焊盘44包括设置在第2层叠体40内部的内部焊盘、以及在第2层叠体40的表面(粘接面S)上露出的接合焊盘48。在第1层叠体30与第2层叠体40层叠后的状态下,第2层叠体40的接合焊盘48设置在第1层叠体30的接合焊盘38上,并与第1层叠体30的接合焊盘38接合。接合焊盘48是“第2焊盘”的一例。多条布线43中的与接合焊盘48连接的布线47是“第2布线”的一例。对于接合焊盘48将在后面详细叙述。
第2绝缘体45设置在多个接触插塞42、多条布线43以及多个焊盘44之间,将这些要素相互电绝缘。第2绝缘体45例如由TEOS、硅氧化物或者硅氮化物等形成。
第2基板60设置在第2层叠体40的上方。第2基板60位于在Z方向上从第1基板10分离的位置。第2基板60是阵列芯片3所包含的基板。第2基板60例如是硅基板。在第2基板60上设置有作为存储元件阵列41的源极线发挥功能的导电区域。第2基板60具有面向存储元件阵列41的第1面60a、以及位于与第1面60a相反侧的第2面60b。在第2面60b上设置有外部连接焊盘71。外部连接焊盘71设置有未图示的外部连接端子(例如焊球),并经由该外部连接端子而与半导体存储装置1的外部电连接。
绝缘层72设置在第2基板60上。绝缘层73设置在绝缘层72上。绝缘层72、73是保护层叠体20的钝化膜。绝缘层72例如是硅氧化膜。绝缘层73例如是聚酰亚胺膜。
图2是表示存储元件阵列41的存储柱P附近的截面图。如图2所示,多条字线WL夹着层间绝缘膜45b而在Z方向上层叠。多条字线WL沿着X方向延伸。存储元件阵列41具有设置有存储柱P的存储孔MH。存储柱P在存储孔MH内部沿着Z方向延伸,并贯通多条字线WL。
在从Z方向观察的情况下,存储柱P例如为圆状或者椭圆状。存储柱P从内侧起依次具有芯绝缘体52、半导体主体53以及存储膜54。
芯绝缘体52是沿着Z方向延伸的柱状体。芯绝缘体52例如包含硅氧化物。芯绝缘体52位于半导体主体53的内侧。
半导体主体53沿着Z方向延伸,作为沟道发挥功能。半导体主体53与第2基板60的作为源极线发挥功能的导电区域连接。半导体主体53覆盖芯绝缘体52的外周面。半导体主体53例如包含硅。硅例如是使非晶硅结晶而成的多晶硅。
存储膜54沿着Z方向延伸。存储膜54覆盖半导体主体53的外周面。存储膜54位于存储孔MH的内表面与半导体主体53的外侧面之间。存储膜54例如包括隧道绝缘膜55以及电荷蓄积膜56。
隧道绝缘膜55位于电荷蓄积膜56与半导体主体53之间。隧道绝缘膜55例如包含硅氧化物或者硅氧化物和硅氮化物。隧道绝缘膜55是半导体主体53与电荷蓄积膜56之间的势垒。
电荷蓄积膜56设置在字线WL以及层间绝缘膜45b各自与隧道绝缘膜55之间。电荷蓄积膜56例如包含硅氮化物。电荷蓄积膜56与字线WL之间的交叉部分作为存储元件MC发挥功能。存储元件MC根据电荷蓄积膜56与字线WL之间的交叉部分(电荷蓄积部)内有无电荷或者所蓄积的电荷量来保持数据。电荷蓄积部位于字线WL与半导体主体53之间,周围被绝缘材料包围。
在字线WL与层间绝缘膜45b之间以及字线WL与存储膜54之间也可以设置有块绝缘膜57以及阻挡膜58。块绝缘膜57是抑制反向隧道效应的绝缘膜。反向隧道效应是电荷从字线WL向存储膜54返回的现象。块绝缘膜57例如是硅氧化膜、金属氧化物膜或者多个绝缘膜层叠而成的层叠构造膜。金属氧化物的一例是铝氧化物。阻挡膜58例如是氮化钛膜、或者氮化钛与钛的层叠构造膜。
在层间绝缘膜45b与电荷蓄积膜56之间也可以设置有覆盖绝缘膜59。覆盖绝缘膜59例如包含硅氧化物。覆盖绝缘膜59在加工时保护电荷蓄积膜56不被蚀刻。覆盖绝缘膜59可以不存在,也可以在导电层51与电荷蓄积膜56之间残留一部分而用作为块绝缘膜。
<2.接合焊盘的构成>
接着,对接合焊盘38、48的构成进行说明。图3是表示多个接合焊盘38、48的截面图。如图3所示,第1层叠体30的布线37包括相互电气独立的布线37A、37B、37C。在X方向以及Y方向上,在布线37A、37B、37C之间设置有第1绝缘体35。由此,布线37A、37B、37C相互电绝缘。布线37A、37B、37C能够成为互不相同的电位。在以下,在不将布线37A、37B、37C相互区分的情况下,称作“布线37”。
第1层叠体30的接合焊盘38包括与布线37A连接的接合焊盘38A、与布线37B连接的接合焊盘38B、以及与布线37C连接的接合焊盘38C。在X方向以及Y方向上,在接合焊盘38A、38B、38C之间设置有第1绝缘体35。接合焊盘38A、38B、38C能够成为互不相同的电位。在以下,在不将接合焊盘38A、38B、38C相互区分的情况下,称作“接合焊盘38”。
在本实施方式中,接合焊盘38A、38B、38C分别具有在X方向以及Y方向中的至少一方相互分离的多个电极部81。在此处说明的一例中,接合焊盘38A、38B、38C分别具有在X方向以及Y方向上分别相互分离的多个电极部81(参照图4)。在X方向以及Y方向上,在多个电极部81之间设置有第1绝缘体35。换言之,在沿着Z方向观察的情况下,在粘接面S中在多个电极部81之间设置有第1绝缘体35。电极部81是“第1电极部”的一例。
多个电极部81相互独立,且分别与布线37连接。即,相同的接合焊盘38所包含的多个电极部81与相同的布线37连接。相同的接合焊盘38所包含的多个电极部81成为相同电位。在图3所示的例子中,接合焊盘38A所包含的多个电极部81与布线37A连接。接合焊盘38B所包含的多个电极部81与布线37B连接。接合焊盘38C所包含的多个电极部81与布线37C连接。
同样,第2层叠体40的布线47包括相互电气独立的布线47A、47B、47C。在X方向以及Y方向上,在布线47A、47B、47C之间设置有第2绝缘体45。由此,布线47A、47B、47C相互电绝缘。布线47A、47B、47C能够成为互不相同的电位。在以下,在不将布线47A、47B、47C相互区分的情况下,称作“布线47”。
第2层叠体40的接合焊盘48包括与布线47A连接的接合焊盘48A、与布线47B连接的接合焊盘48B、以及与布线47C连接的接合焊盘48C。在X方向以及Y方向上,在接合焊盘48A、48B、48C之间设置有第2绝缘体45。接合焊盘48A、48B、48C能够成为互不相同的电位。在以下,在不将接合焊盘48A、48B、48C相互区分的情况下,称作“接合焊盘48”。
在本实施方式中,与第1层叠体30的接合焊盘38A、38B、38C同样,接合焊盘48A、48B、48C分别具有在X方向以及Y方向中的至少一方相互分离的多个电极部82。在此处说明的一例中,接合焊盘48A、48B、48C分别具有在X方向以及Y方向上分别相互分离的多个电极部82。在X方向以及Y方向上,在多个电极部82之间设置有第2绝缘体45。换言之,在沿着Z方向观察的情况下,在粘接面S中在多个电极部82之间设置有第2绝缘体45。电极部82是“第2电极部”的一例。
多个电极部82相互独立,并分别与布线47连接。即,相同的接合焊盘48所包含的多个电极部82与相同的布线47连接。相同的接合焊盘48所包含的多个电极部82成为相同电位。在图3所示的例子中,接合焊盘48A所包含的多个电极部82与布线47A连接。接合焊盘48B所包含的多个电极部82与布线47B连接。接合焊盘48C所包含的多个电极部82与布线47C连接。
第1层叠体30的接合焊盘38的多个电极部81与第2层叠体40的接合焊盘48的多个电极部82通过粘接面S而相互接合。由此,第1层叠体30的接合焊盘38与第2层叠体40的接合焊盘48相互接合。在图3所示的例子中,第1层叠体30的接合焊盘38的多个电极部81与第2层叠体40的接合焊盘48的多个电极部82以相互相同的方式设置。“方式相同”是指多个电极部81、82的形状相同。在该情况下,第1层叠体30的接合焊盘38的多个电极部81与第2层叠体40的接合焊盘48的多个电极部82以1对1的对应关系相互接合。
在本实施方式中,第1层叠体30的接合焊盘38A的多个电极部81与第2层叠体40的接合焊盘48A的多个电极部82相互接合,由此布线37A与布线47A电连接。同样,第1层叠体30的接合焊盘38B的多个电极部81与第2层叠体40的接合焊盘48B的多个电极部82相互接合,由此布线37B与布线47B电连接。第1层叠体30的接合焊盘38C的多个电极部81与第2层叠体40的接合焊盘48C的多个电极部82相互接合,由此布线37C与布线47C电连接。
在本实施方式中,接合焊盘38A、38B、38C、48A、48B、48C具有相互相同的形状。因此,在以下,对第1层叠体30的一个接合焊盘38进行详细说明。第2层叠体40的接合焊盘48也具有与以下说明的构造相同的构造。
图4是表示接合焊盘38的图。图4表示第1层叠体30与第2层叠体40被粘接之前的状态的接合焊盘38。在本实施方式中,多个电极部81例如包括在X方向以及Y方向上分开且被配置成3×3矩阵状的9个电极部81。即,多个电极部81包括在X方向上相互分离且等间隔地配置的多个电极部81。同样,多个电极部81包括在Y方向上相互分离且等间隔地配置的多个电极部81。但是,电极部81的数量以及配置并不限定于上述例子。
电极部81例如是沿着X方向以及Y方向的四边形状。在图4所示的例子中,X方向上的电极部81的宽度W1与在X方向上相邻的两个电极部81之间的距离L1相同。同样,Y方向上的电极部81的宽度W2与在Y方向上相邻的两个电极部81之间的距离L2相同。相邻的两个电极部81之间的距离L1、L2小于相邻的两个接合焊盘38之间的距离L3(参照图3)。
沿着Z方向观察,在将假想线IL的内侧区域定义为“焊盘区域R”的情况下,焊盘区域R中的多个电极部81的面积的合计小于焊盘区域R中的第1绝缘体35的面积,该假想线IL沿着一个接合焊盘38所包含的多个电极部81中的相对于接合焊盘38的中央部位于最外部的多个电极部81A的边缘而一体地包围多个电极部81。换言之,多个电极部81以比较大的间距相互分离地配置。
在本实施方式中,各电极部81具有电极主体91以及连接部92。电极主体91在粘接面S(参照图3)上露出,并与第2层叠体40的接合焊盘48接合。连接部92位于电极主体91与布线37之间,将电极主体91与布线37连接。连接部92比电极主体91细。例如,X方向上的连接部92的宽度W4小于X方向上的电极主体91的宽度W3。同样,Y方向上的连接部92的宽度小于Y方向上的电极主体91的宽度。各电极部81的电极主体91经由对应的连接部92而与布线37连接。
在另一个观点中,各电极部81具有导电部主体95以及阻挡金属层96。导电部主体95形成各电极部81的主要部分。阻挡金属层96在X方向以及Y方向上设置在导电部主体95与第1绝缘体35之间。阻挡金属层96是抑制导电部主体95所包含的导电材料(例如铜或者铝)向第1绝缘体35中扩散的金属层。导电部主体95以及阻挡金属层96分别设置于电极主体91以及连接部92的双方。
如图4所示,在第1层叠体30与第2层叠体40被粘接之前的状态下,各电极部81的端部E相对于第1绝缘体35的+Z方向侧的表面35a朝+Z方向突出。各电极部81的端部E具有朝-Z方向呈碗状凹陷的凹部RS。
以上,对第1层叠体30的接合焊盘38进行了说明。关于第2层叠体40的接合焊盘48,只要在上述说明中,将“接合焊盘38”替换为“接合焊盘48”,将“布线37”替换为“布线47”,将“+Z方向”替换为“-Z方向”,将“-Z方向”替换为“+Z方向”即可。
图5是表示第1层叠体30与第2层叠体40粘接时的第1层叠体30的电极部81以及第2层叠体40的电极部82的状态的截面图。在本实施方式中,在粘接第1层叠体30与第2层叠体40时,第1层叠体30以及第2层叠体40被加热,并且第2层叠体40被朝向第1层叠体30按压。即,在第1层叠体30的电极部81与第2层叠体40的电极部82相互抵接的状态下,第2层叠体40被朝向第1层叠体30按压。
由此,第1层叠体30的电极部81以及第2层叠体40的电极部82分别变形。即,第1层叠体30的电极部81变形为不从第1绝缘体35的表面35a突出的状态。进而,第1层叠体30的电极部81的端部E的凹部RS被填埋而消失(或者变小)。同样,第2层叠体40的电极部82变形为不从第2绝缘体45的表面45a突出的状态。进而,第2层叠体40的电极部82的端部的凹部RS被填埋而消失(或者变小)。
<3.半导体存储装置的制造方法>
接着,对半导体存储装置1的制造方法进行说明。图6至图9是表示半导体存储装置1的制造方法的截面图。
图6表示电路芯片2的制造阶段。电路芯片2被制造为电路晶片CW的一部分。电路晶片CW包括多个电路芯片2。通过在第1基板10上形成第1层叠体30而得到电路晶片CW。第1层叠体30包括晶体管31、接触插塞32、布线33、焊盘34以及第1绝缘体35。这些针对每个分层来形成。通过反复进行这些各层的成膜、基于光刻等的加工而形成电路晶片CW。接合焊盘38以外的成膜方法以及加工方法能够使用公知的方法。在电路晶片CW的与第1基板10相反侧的粘接面S1上露出多个接合焊盘38。由此,完成电路晶片CW。
此处,对接合焊盘38的形成方法进行详细说明。图7表示接合焊盘38的制造阶段的详细情况。首先,如图7中的(a)所示,在布线37上设置有第1绝缘体35的一部分。设置在布线37上的第1绝缘体35例如由硅氧化物(SiO2)形成。
接着,在第1绝缘体35上设置保护层101。保护层101由与第1绝缘体35不同的材料形成。保护层101例如由硅氮化物(SiN)形成。保护层101的厚度T1例如被设定为大于由于化学机械研磨的凹陷而产生的凹部RS的凹陷量K(参照图7中的(c))。例如,保护层101的厚度T1(例如Z方向的厚度)大于阻挡金属层96的厚度T2(例如X方向的厚度)。
接着,如图7中的(b)所示,通过照相蚀刻工序(Photo Engraving Process:PEP)来形成抗蚀剂图案,通过反应离子蚀刻(Reactive Ion Etching:RIE)对保护层101以及第1绝缘体35进行蚀刻。由此,在后续工序中设置多个电极部81的位置上形成多个孔102。
接着,如图7中的(c)所示,在孔102的内表面上形成成为阻挡金属层96的基础的导电层103a。之后,通过向孔102的内部填埋导电材料(例如铜或者铝那样的金属材料),由此形成成为导电部主体95的基础的导电部103b。由此,形成填埋孔102的导电部103。导电部103是成为多个电极部81的基础的导电部。
接着,将保护层101作为停止层而通过化学机械研磨(ChemicalMechanical.Polisher:CMP)来进行导电部103的平坦化。例如,通过检测保护层101的表面而使研磨结束的端点模式来进行CMP。由此,从导电部103形成多个电极部81。此时,在各电极部81的上端部的表面上形成由于凹陷(Dishing)而产生的凹部RS。
接着,如图7中的(d)所示,除去保护层101。在保护层101为硅氮化物的情况下,例如使用磷酸来进行保护层101的除去。由此,第1绝缘体35的表面35a露出。第1绝缘体35的表面35a形成与阵列芯片3粘接的粘接面S1。各电极部81的上端部即端部E从第1绝缘体35的表面35a(粘接面S1)朝上方突出。由此,完成接合焊盘38。
图8表示阵列芯片3的制造阶段。阵列芯片3被制造为阵列晶片AW的一部分。阵列晶片AW包括多个阵列芯片3。图8所示的阵列晶片AW处于与电路晶片CW粘接之前的状态,相对于图1所示的阵列芯片3为上下反转。
通过在第2基板60上形成第2层叠体40而得到阵列晶片AW。第2层叠体40包括存储元件阵列41、接触插塞42、布线43、焊盘44以及第2绝缘体45。这些针对每个分层来形成。通过反复进行这些各层的成膜、基于光刻等的加工而形成阵列晶片AW。接合焊盘48以外的成膜方法以及加工方法能够使用公知的方法。在阵列晶片AW的与第2基板60相反侧的粘接面S2上露出多个接合焊盘48。接合焊盘48的形成方法例如与参照图7说明过的接合焊盘38的形成方法相同。由此,完成电路晶片CW。
图9表示电路晶片CW与阵列晶片AW的粘接阶段。具体而言,对电路晶片CW以及阵列晶片AW进行加热,并且使电路晶片CW的粘接面S1与阵列晶片AW的粘接面S2相面对(即,使第1层叠体30的接合焊盘38与第2层叠体40的接合焊盘48相面对),通过机械压力将电路晶片CW与阵列晶片AW粘接。由此,第1绝缘体35与第2绝缘体45被粘接。
此时,如参照图5上述的那样,在接合焊盘38的电极部81的端部E从第1绝缘体35的表面35a突出且接合焊盘48的电极部82的端部E从第2绝缘体45的表面45a突出的状态下,电路晶片CW的接合焊盘38与阵列晶片AW的接合焊盘48相互抵接。然后,通过机械压力,使相互抵接的接合焊盘38的电极部81以及接合焊盘48的电极部82变形,在之前工序中由于凹陷而形成于电极部81、82的凹部RS被填埋而消失(或者变小)。
接着,阵列晶片AW以及电路晶片CW以400℃进行退火。由此,接合焊盘38的电极部81与接合焊盘48的电极部82被接合。由此,形成电路晶片CW与阵列晶片AW被粘接的粘接体111。
接着,第2基板60被薄型化。第2基板60的薄型化例如通过CMP来进行。接着,通过公知的方法,对第2基板60设置外部连接焊盘71以及绝缘层72、73。然后,沿着未图示的切割线来切断粘接体111。由此,粘接体111被分割成多个芯片(半导体存储装置1)。由此,得到半导体存储装置1。
<4.优点>
为了进行比较,对接合焊盘由比较大的一个电极部构成的情况进行考虑。在这样的比较例的构成中,当由于CMP或者其他理由而在接合焊盘的端部产生较大的凹陷时,有时在所粘接的两个接合焊盘之间会残留空间。在该情况下,在两个接合焊盘的接合面上形成空隙(Void)。在该情况下,接合焊盘的电阻变高。
进而,该空隙有时由于由室温引起的应力迁移而朝接合焊盘与布线之间的连接部移动(凝聚)。在该情况下,存在接合焊盘与布线之间成为断线状态的可能性。另一方面,当为了使两个接合焊盘更可靠地接合而以增大热膨胀的方式使退火温度上升时,阻挡金属层所包含的金属朝绝缘体的内部扩散,存在基于阻挡金属层的阻挡性降低的可能性。
另一方面,在本实施方式中,接合焊盘38包括在X方向上相互分离且分别与布线37连接的多个电极部81。在多个电极部81之间设置有第1绝缘体35。根据这种构成,接合焊盘38被分为多个较小的电极部81,因此在各电极部81中难以产生较大的凹陷,凹部RS的凹陷量K变小。因此,在所粘接的两个接合焊盘38、48之间难以残留空间,在两个接合焊盘的接合面上难以产生空隙。其结果,接合焊盘38、48的电阻难以变高。由此,能够实现半导体存储装置1的电气特性的提高。
此外,在本实施方式中,多个电极部81相互独立,并分别与布线37连接。根据这种构成,能够通过多个电极部81使作用于接合焊盘38的应力分散。由此,能够使由应力迁移导致的断线概率减少。
在本实施方式中,在半导体存储装置1的制造时,在第1绝缘体35上设置保护层101。之后,通过将保护层101作为停止层来进行化学机械研磨而形成多个电极部81。之后,除去保护层101。由此,使多个电极部81的端部E从第1绝缘体35突出。然后,在多个电极部81的端部E从第1绝缘体35突出的状态下,使接合焊盘38的多个电极部81与接合焊盘48抵接。根据这种构成,两个接合焊盘38、48在电极部81的端部E从第1绝缘体35突出的状态下接合,因此通过从第1绝缘体35突出的电极部81的端部E填埋由于凹陷而产生的凹部RS。因此,在所粘接的两个接合焊盘38、48之间难以残留空间,在两个接合焊盘38、48的接合面上难以产生空隙。由此,能够实现半导体存储装置1的电气特性的提高。
进而,在将保护层101作为停止层而进行化学机械研磨的情况下,与未设置保护层101的情况相比,相对于第1绝缘体35的表面35a在较高的位置上形成由于凹陷而产生的凹部RS。即,在形成凹陷的界面被提高的状态下形成多个电极部81。因此,在以第1绝缘体35的表面35a为基准进行观察的情况下,在电极部81难以产生较大的凹陷,凹部RS的凹陷量K变小。由于这样的理由,在所粘接的两个接合焊盘38、48之间也难以残留空间,在两个接合焊盘38、48的接合面上难以产生空隙。由此,能够实现半导体存储装置1的电气特性的提高。
在本实施方式中,沿着Z方向观察,在将沿着多个电极部81中的相对于接合焊盘38的中央部位于最外部的多个电极部81A的边缘而将多个电极部81一体地包围的区域定义为焊盘区域R的情况下,焊盘区域R中的多个电极部81的面积的合计小于焊盘区域R中的第1绝缘体35的面积。根据这种构成,接合焊盘38被分为多个更小的电极部81,因此在各电极部81更难以产生较大的凹陷。由此,能够实现半导体存储装置1的电气特性的提高。
在本实施方式中,多个电极部81包括在X方向上分离的多个电极部81以及在Y方向上分离的多个电极部81。根据这种构成,接合焊盘38在多个方向上被分为较小的电极部81,因此在各电极部81更难以产生较大的凹陷。由此,能够实现半导体存储装置1的电气特性的提高。
在本实施方式中,多个电极部81分别具有电极主体91、以及位于电极主体91与布线37之间的连接部92。X方向上的连接部92的宽度W4小于X方向上的电极主体91的宽度W3。根据这种构成,即使是由于连接部92变细而容易产生由于应力迁移引起的断线的构成,由于多个电极部81相互独立且分别与布线37连接,因此能够使由于应力迁移引起的断线概率减少。
<5.变形例>
以下,对变形例进行说明。在本变形例中,除了在以下说明以外的构成与上述实施方式的构成相同。
图10是表示变形例的半导体存储装置1的截面图。图11是将图10所示的由F11线包围的区域放大表示的截面图。在本变形例中,X方向上的第1层叠体30的接合焊盘38的各电极部81的宽度W1A大于X方向上的第2层叠体40的接合焊盘48的相邻的两个电极部82之间的距离L1B。同样,X方向上的第2层叠体40的接合焊盘48的各电极部82的宽度W1B大于X方向上的第1层叠体30的接合焊盘38的相邻的两个电极部81之间的距离L1A。该情况在Y方向上也相同。
在本变形例中,即使在第2层叠体40的接合焊盘48相对于第1层叠体30的接合焊盘38位置偏移了的情况下,接合焊盘38的电极部81的一部分与接合焊盘48的电极部82的一部分在Z方向上也可靠地相面对,接合焊盘38的电极部81与接合焊盘48的电极部82可靠地连接。由此,能够实现半导体存储装置1的电气特性的提高。
<6.实施例>
以下,对与接合焊盘38、48的电极部81、82的形状相关的几个实施例进行说明。在以下,以第1层叠体30的接合焊盘38的电极部81的形状为代表进行说明。第2层叠体40的接合焊盘48的电极部82的形状也相同。另外,电极部81、82的形状并不限定于在以下说明的实施例的内容。
<6.1第1实施例>
图12是表示第1实施例的多个电极部81的形状的截面图。在第1实施例中,多个电极部81在X方向以及Y方向上分别分离并被配置成矩阵状。在图12所示的例子中,设置有8×8的64个电极部81。
<6.2第2实施例>
图13是第2实施例的多个电极部81的形状的截面图。在第2实施例中,接合焊盘38包括框部121、多个第1直线部122以及多个第2直线部123。多个第1直线部122以及多个第2直线部123设置在框部121的内侧。多个第1直线部122在X方向上相互分离,且分别沿着Y方向延伸。在X方向上在多个第1直线部122之间设置有第1绝缘体35。另一方面,多个第2直线部123在Y方向上相互分离,且分别沿着X方向延伸。在Y方向上在多个第2直线部123之间设置有第1绝缘体35。多个第1直线部122与多个第2直线部123相互交叉。
在本实施例中,通过多个第1直线部122形成在X方向上相互分离的多个电极部81。同样,通过多个第2直线部123形成在Y方向上相互分离的多个电极部81。本说明书中,“相互分离”并不限定于如第1实施例那样完全独立的情况,也包括经由其他部分(例如框部121)而相互连接的情况。
在第2实施例中,第1直线部122在该第1直线部122的延伸方向(Y方向)上,具有遍及(跨越)多个第2直线部123中的至少两个以上第2直线部123的长度。根据这种构成,即使在接合焊盘38与接合焊盘48之间产生了Y方向的位置偏移的情况下,接合焊盘38与接合焊盘48也能够更可靠地连接。同样,第2直线部123在该第2直线部123的延伸方向(X方向)上,具有遍及(跨越)多个第1直线部122中的至少两个以上第1直线部122的长度。根据这种构成,即使在接合焊盘38与接合焊盘48之间产生了X方向的位置偏移的情况下,接合焊盘38与接合焊盘48也能够更可靠地连接。
<6.3第3实施例>
图14是第3实施例的多个电极部81的形状的截面图。在第3实施例中,接合焊盘38包括多个直线部131。多个直线部131在Y方向上相互分离,且分别沿着X方向延伸。在Y方向上在多个直线部131之间设置有第1绝缘体35。在本实施例中,通过多个直线部131形成在Y方向上相互分离的多个电极部81。根据这种构成,即使在接合焊盘38与接合焊盘48之间产生了X方向的位置偏移的情况下,接合焊盘38与接合焊盘48也容易更可靠地连接。
<6.4第4实施例>
图15是第4实施例的多个电极部81的形状的截面图。在第3实施例中,接合焊盘38包括多个直线部141。多个直线部141在X方向上相互分离,且分别沿着Y方向延伸。在X方向上在多个直线部141之间设置有第1绝缘体35。在本实施例中,通过多个直线部141形成在X方向上相互分离的多个电极部81。根据这种构成,即使在接合焊盘38与接合焊盘48之间产生了Y方向的位置偏移的情况下,接合焊盘38与接合焊盘48也容易更可靠地连接。
<6.5第5实施例>
图16是第5实施例的多个电极部81的形状的截面图。在第5实施例中,接合焊盘38包括框部151以及多个直线部152。多个直线部152设置在框部151的内侧。多个直线部152在Y方向上相互分离,且分别沿着X方向延伸。在Y方向上在多个直线部152之间设置有第1绝缘体35。在本实施例中,通过多个直线部152形成在Y方向上相互分离的多个电极部81。
<6.6第6实施例>
图17是第6实施例的多个电极部81的形状的截面图。在第6实施例中,接合焊盘38包括框部161以及多个直线部162。多个直线部162设置在框部161的内侧。多个直线部162在X方向上相互分离,且分别沿着Y方向延伸。在X方向上在多个直线部162之间设置有第1绝缘体35。在本实施例中,通过多个直线部162形成在X方向上相互分离的多个电极部81。
<6.7第7实施例>
图18是第7实施例的多个电极部81的形状的截面图。在第7实施例中,接合焊盘38包括多个框部171。多个框部171为大小互不相同的相似形状的环状,且呈同心状配置。在X方向以及Y方向上,在多个框部171之间设置有第1绝缘体35。在本实施例中,通过多个框部171分别形成环状的多个电极部81。从其他观点来看,通过多个框部171所包含的沿着Y方向的线状部171a,形成在X方向上相互分离的多个电极部81。同样,通过多个框部171所包含的沿着X方向的线状部171b,形成在Y方向上相互分离的多个电极部81。当接合焊盘38包括沿着Y方向延伸的部分和沿着X方向延伸的部分的双方时,即使在接合焊盘38与接合焊盘48之间产生了X方向和Y方向的任意方向的位置偏移的情况下,接合焊盘38与接合焊盘48也容易更可靠地连接。
<6.8第8实施例>
图19是第8实施例的多个电极部81、82的形状的截面图。图19中的(a)表示第1层叠体30的接合焊盘38的多个电极部81。图19中的(b)表示第2层叠体40的接合焊盘48的多个电极部82。
在本实施例中,第1层叠体30的接合焊盘38的多个电极部81以第1方式设置。本实施例的第1方式例如是与第3实施例(图14)相同的方式。另一方面,第2层叠体40的接合焊盘48的多个电极部82以与上述第1方式不同的第2方式设置。“方式不同”是指多个电极部81、82的形状不同。本实施例的第2方式例如是与第4实施例(图15)相同的方式。
图19中的(c)表示接合焊盘38的多个电极部81与接合焊盘48的多个电极部82重叠(粘接)的状态。在图19所示的例子中,接合焊盘38的多个电极部81相互分离的方向(Y方向)与接合焊盘48的多个电极部82相互分离的方向(X方向)不同。
接合焊盘38的各电极部81的至少一部分,在接合焊盘48的多个电极部82相互分离的方向(X方向)上,呈遍及(跨越)两个以上电极部82的直线状延伸。另一方面,接合焊盘48的各电极部82的至少一部分,在接合焊盘38的多个电极部81相互分离的方向(Y方向)上,呈遍及(跨越)两个以上电极部81的直线状延伸。根据这种构成,即使在接合焊盘38与接合焊盘48之间在X方向和Y方向的任意方向上产生了位置偏移的情况下,接合焊盘38与接合焊盘48也更可靠地连接。
<6.9第9实施例>
图20是表示第9实施例的多个电极部81、82的形状的截面图。图20中的(a)表示第1层叠体30的接合焊盘38的多个电极部81。图20中的(b)表示第2层叠体40的接合焊盘48的多个电极部82。
在本实施例中,第1层叠体30的接合焊盘38的多个电极部81以第1方式设置。本实施例的第1方式例如是与第1实施例(图12)相同的方式。另一方面,第2层叠体40的接合焊盘48的多个电极部82以与上述第1方式不同的第2方式设置。本实施例的第2方式例如是与第7实施例(图18)相同的方式。
图20中的(c)表示接合焊盘38的多个电极部81与接合焊盘48的多个电极部82重叠(粘接)的状态。在图20所示的例子中,接合焊盘38的多个电极部81在X方向以及Y方向上相互分离。另一方面,接合焊盘48的各电极部82的至少一部分(例如线状部171b),在接合焊盘38的多个电极部81相互分离的方向(X方向)上,呈遍及(跨越)两个以上电极部81的直线状延伸。接合焊盘48的各电极部82的至少一部分(例如线状部171a),在接合焊盘38的多个电极部81相互分离的方向(Y方向)上,呈遍及(跨越)两个以上电极部81的直线状延伸。根据这种构成,即使在接合焊盘38与接合焊盘48之间在X方向和Y方向的任意方向上产生了位置偏移的情况下,接合焊盘38与接合焊盘48也更可靠地连接。
以上,对实施方式、变形例以及几个实施例进行了说明。但是,实施方式、变形例、实施例并不限定于上述例子。例如,上述第1至第7实施例中的任意一个实施例的接合焊盘38的电极部81与上述第1至第7实施例中任意另一个实施例的接合焊盘48的电极部82也可以接合。在上述全部说明中,接合焊盘38以及接合焊盘48的形状也可以相反。在上述实施方式中,接合焊盘38被分为多个电极部81,并且接合焊盘48被分为多个电极部82。代替该情况,可以是接合焊盘38被分为多个电极部81,并且接合焊盘48为一个大的焊盘,也可以是接合焊盘48被分为多个电极部82,并且接合焊盘38为一个大的焊盘。
根据以上说明的至少一个实施方式,半导体存储装置具有第1层叠体以及第2层叠体。第1层叠体包括第1布线、与第1布线连接的第1焊盘、以及第1绝缘体。第2层叠体包括第2布线、与第2布线连接的第2焊盘、以及第2绝缘体。第1焊盘包括相互分离且分别与第1布线连接的多个第1电极部。在多个第1电极部之间设置有第1绝缘体。多个第1电极部与第2焊盘接合。根据这种构成,能够提供能够实现电气特性的提高的半导体存储装置以及半导体存储装置的制造方法。
对本发明的几个实施方式进行了说明,但这些实施方式是作为例子而提示的,并不意图对发明的范围进行限定。这些实施方式能够以其他各种方式加以实施,在不脱离发明的主旨的范围内能够进行各种省略、置换、变更。这些实施方式及其变形包含于发明的范围及主旨中,并且包含于专利请求范围所记载的发明和与其等同的范围中。
Claims (10)
1.一种半导体存储装置,具备:
第1基板;
第2基板,在上述第1基板的厚度方向即第1方向上从上述第1基板分离;
第1层叠体,设置在上述第1基板与上述第2基板之间,包括第1布线、与上述第1布线连接的第1焊盘、以及第1绝缘体;以及
第2层叠体,设置在上述第1层叠体与上述第2基板之间,包括第2布线、与上述第2布线连接的第2焊盘、以及第2绝缘体,
上述第1焊盘包括在与上述第1方向交叉的第2方向上相互分离且分别与上述第1布线连接的多个第1电极部,
在上述多个第1电极部之间设置有上述第1绝缘体,
上述多个第1电极部与上述第2焊盘接合。
2.根据权利要求1所述的半导体存储装置,其中,
上述第2焊盘包括在与上述第2方向、或者上述第1方向以及上述第2方向交叉的第3方向上相互分离且分别与上述第2布线连接的多个第2电极部,
在上述多个第2电极部之间设置有上述第2绝缘体,
上述多个第2电极部与上述多个第1电极部接合。
3.根据权利要求2所述的半导体存储装置,其中,
从上述第1方向观察,在将沿着上述多个第1电极部中的相对于上述第1焊盘的中央部位于最外部的多个电极部的边缘而将上述多个第1电极部一体地包围的区域定义为焊盘区域的情况下,上述焊盘区域中的上述多个第1电极部的面积的合计小于上述焊盘区域中的上述第1绝缘体的面积。
4.根据权利要求3所述的半导体存储装置,其中,
上述多个第1电极部分别包括:电极主体,与上述第2焊盘接合;以及连接部,位于上述电极主体与上述第1布线之间,将上述电极主体与上述第1布线连接,上述第2方向的宽度小于上述电极主体的上述第2方向的宽度。
5.根据权利要求1至4中任一项所述的半导体存储装置,其中,
上述多个第1电极部包括在上述第2方向上分离的多个电极部、以及在与上述第1方向以及上述第2方向不同的第3方向上分离的多个电极部。
6.根据权利要求1至4中任一项所述的半导体存储装置,其中,
上述多个第1电极部包括在上述第2方向上分离的多个电极部,
上述多个电极部分别沿着与上述第1方向以及上述第2方向不同的第3方向呈直线状延伸。
7.根据权利要求1至4中任一项所述的半导体存储装置,其中,
上述多个第1电极部包括为同心状的环状的多个电极部。
8.根据权利要求2所述的半导体存储装置,其中,
上述多个第1电极部包括以第1方式分离的多个电极部,
上述多个第2电极部包括以与上述第1方式不同的第2方式分离的多个电极部。
9.一种半导体存储装置的制造方法,其中,
在第1基板上形成包括第1布线、与上述第1布线连接的第1焊盘、以及第1绝缘体的第1层叠体,上述第1焊盘包括在与上述第1基板的厚度方向即第1方向交叉的第2方向上相互分离且分别与上述第1布线连接的多个第1电极部,在上述多个第1电极部之间设置有上述第1绝缘体,
在第2基板上形成包括第2布线、与上述第2布线连接的第2焊盘、以及第2绝缘体的第2层叠体,
使上述第1焊盘与上述第2焊盘相面对而将上述第1层叠体与上述第2层叠体粘接,将上述多个第1电极部与上述第2焊盘接合。
10.根据权利要求9所述的半导体存储装置的制造方法,其中,
形成上述第1层叠体包括:
在上述第1布线上设置上述第1绝缘体;
在上述第1绝缘体上设置保护层;
在上述第1绝缘体以及上述保护层上形成多个孔;
形成填埋上述多个孔的导电部,将上述保护层作为停止层而进行化学机械研磨,由此从上述导电部形成上述多个第1电极部;以及
除去上述保护层,由此使上述多个第1电极部的端部从上述第1绝缘体突出,
将上述第1层叠体与上述第2层叠体粘接包括:
在上述多个第1电极部的端部从上述第1绝缘体突出的状态下,使上述多个第1电极部与上述第2焊盘抵接。
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