CN113380781A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN113380781A
CN113380781A CN202010836511.2A CN202010836511A CN113380781A CN 113380781 A CN113380781 A CN 113380781A CN 202010836511 A CN202010836511 A CN 202010836511A CN 113380781 A CN113380781 A CN 113380781A
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China
Prior art keywords
metal layer
insulating film
pad
wiring
layer
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CN202010836511.2A
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田上政由
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Kioxia Corp
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Kioxia Corp
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Publication of CN113380781A publication Critical patent/CN113380781A/zh
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Abstract

实施方式提供一种能够形成适合于贴合的焊垫的半导体装置及其制造方法。根据一实施方式，半导体装置具备衬底、设置在所述衬底的上方的第1绝缘膜、设置在所述第1绝缘膜内的第1配线、在所述第1绝缘膜内，设置在所述第1配线上的第1焊垫、设置在所述第1绝缘膜的上的第2绝缘膜、在所述第2绝缘膜内，设置在所述第1焊垫上的第2焊垫、及在所述第2绝缘膜内，设置在所述第2焊垫上的第2配线。所述第1焊垫包含设置在所述第1绝缘膜内的第1金属层、及介隔所述第1金属层设置在所述第1绝缘膜内且与所述第1配线直接相接的第2金属层。

Description

半导体装置及其制造方法
[相关申请案]
本申请案享有以日本专利申请案2020-29644号(申请日：2020年2月25日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的所有内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
在将多个晶片的金属焊垫贴合制造半导体装置的情况下，期望形成适合于贴合的金属焊垫。
发明内容
实施方式提供一种能够形成适合于贴合的焊垫的半导体装置及其制造方法。
根据一实施方式，半导体装置具备衬底、设置在所述衬底的上方的第1绝缘膜、设置在所述第1绝缘膜内的第1配线、在所述第1绝缘膜内，设置在所述第1配线上的第1焊垫、设置在所述第1绝缘膜之上的第2绝缘膜、在所述第2绝缘膜内，设置在所述第1焊垫上的第2焊垫、及在所述第2绝缘膜内，设置在所述第2焊垫上的第2配线。所述第1焊垫包含设置在所述第1绝缘膜内的第1金属层、及介隔所述第1金属层设置在所述第1绝缘膜内且与所述第1配线直接相接的第2金属层。
附图说明
图1是表示第1实施方式的半导体装置的构造的剖视图。
图2是表示第1实施方式的柱状部的构造的剖视图。
图3是表示第1实施方式的半导体装置的制造方法的剖视图。
图4(a)、(b)是表示第1实施方式的半导体装置的构造的其它剖视图。
图5(a)、(b)是表示第1实施方式的比较例的半导体装置的构造的剖视图。
图6(a)及(b)、图7(a)及(b)、图8(a)及(b)、图9(a)及(b)是表示第1实施方式的半导体装置的制造方法的剖视图。
图10(a)及(b)、图11(a)及(b)是表示第1实施方式的半导体装置的制造方法的第1例的剖视图。
图12(a)及(b)、图13(a)及(b)是表示第1实施方式的半导体装置的制造方法的第2例的剖视图。
图14(a)、(b)是用来将第1实施方式的半导体装置与其比较例的半导体装置进行比较的俯视图。
图15(a)、(b)是表示用来将第1实施方式的半导体装置与其比较例的半导体装置进行比较的其它俯视图。
图16(a)、(b)是表示第2实施方式的半导体装置的构造的剖视图。
图17(a)、(b)是表示第2实施方式的变化例的半导体装置的构造的剖视图。
图18(a)及(b)、图19(a)及(b)是表示第2实施方式的半导体装置的制造方法的剖视图。
图20(a)及(b)、图21(a)及(b)是表示第2实施方式的半导体装置的制造方法的第1例的剖视图。
图22(a)及(b)、图23(a)及(b)是表示第2实施方式的半导体装置的制造方法的第2例的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。在图1至图23中，对相同构成标注相同符号，并省略重复的说明。
(第1实施方式)
图1是表示第1实施方式的半导体装置的构造的剖视图。图1的半导体装置是阵列芯片1与电路芯片2贴合而成的三维存储器。
阵列芯片1具备包含多个存储单元的存储单元阵列11、存储单元阵列11上的绝缘膜12、及存储单元阵列11下的层间绝缘膜13。绝缘膜12例如是氧化硅膜或氮化硅膜。层间绝缘膜13例如是氧化硅膜、或包含氧化硅膜与其它绝缘膜的积层膜。层间绝缘膜13是第2绝缘膜的例。
电路芯片2设置在阵列芯片1下。符号S表示阵列芯片1与电路芯片2的贴合面。电路芯片2具备层间绝缘膜14、及层间绝缘膜14下的衬底15。层间绝缘膜14例如是氧化硅膜、或包含氧化硅膜与其它绝缘膜的积层膜。层间绝缘膜14是第1绝缘膜的例。衬底15例如是硅衬底等半导体衬底。
图1表示与衬底15的表面平行且相互垂直的X方向及Y方向、及与衬底15的表面垂直的Z方向。在本说明书中，将+Z方向作为上方向处理，将-Z方向作为下方向处理。-Z方向既可以与重力方向一致也可以不一致。
阵列芯片1具备多条字线WL与源极线SL作为存储单元阵列11内的电极层。图1表示存储单元阵列11的阶梯构造部21。各字线WL经由接触插塞22而与字元配线层23电连接。贯通多条字线WL的各柱状部CL经由通孔插塞24而与位元线BL电连接，且与源极线SL电连接。源极线SL包含作为半导体层的第1层SL1、及作为金属层的第2层SL2。
电路芯片2具备多个晶体管31。各晶体管31具备介隔闸极绝缘膜设置在衬底15上的闸极电极GE、及设置在衬底15内的未图示的源极扩散层及汲极扩散层。又，电路芯片2具备：多个接触插塞32，设置在这些晶体管31的闸极电极GE、源极扩散层、或汲极扩散层上；配线层，设置在这些接触插塞32上且包含多条配线33；及多个通孔插塞34，设置在该配线层上。
电路芯片2进而具备设置在这些通孔插塞34上且包含多条配线35的配线层、设置在该配线层上的多个通孔插塞36、设置在这些通孔插塞36上且包含多条配线37的配线层、及设置在该配线层上的多个金属焊垫38。金属焊垫38例如包含Cu(铜)层或Al(铝)层。配线37是第1配线的例，金属焊垫38是第1焊垫的例。电路芯片2作为控制阵列芯片1的动作的控制电路(逻辑电路)发挥功能。该控制电路由晶体管31等构成，电连接于金属焊垫38。
阵列芯片1具备设置在金属焊垫38上的多个金属焊垫41、设置在金属焊垫41上且包含多条配线42的配线层、及设置在该配线层上的多个通孔插塞43。金属焊垫41例如包含Cu层或Al层。金属焊垫41是第2焊垫的例，配线42是第2配线的例。
阵列芯片1进而具备设置在这些通孔插塞43上且包含多条配线44的配线层、设置在该配线层上的多个通孔插塞45、设置在这些通孔插塞45上、绝缘膜12上的金属焊垫46、及设置在金属焊垫46上、绝缘膜12上的钝化膜47。金属焊垫46例如包含Cu层或Al层，作为图1的半导体装置的外部连接焊垫(接合焊垫)发挥功能。钝化膜47例如是氧化硅膜等绝缘膜，具有使金属焊垫46的上表面露出的开口部P。金属焊垫46能够经由该开口部P且通过接合线、焊球、金属凸块等而连接于安装衬底、其它装置。
图2是表示第1实施方式的柱状部CL的构造的剖视图。
如图2所示，存储单元阵列11具备交替地积层在层间绝缘膜13(图1)上的多条字线WL与多个绝缘层51。字线WL例如是W(钨)层。绝缘层51例如是氧化硅膜。
柱状部CL依次包含区块绝缘膜52、电荷储存层53、隧道绝缘膜54、通道半导体层55、及芯绝缘膜56。电荷储存层53例如是氮化硅膜，介隔区块绝缘膜52形成在字线WL及绝缘层51的侧面。电荷储存层53也可以为多晶硅层等半导体层。通道半导体层55例如是多晶硅层，介隔隧道绝缘膜54形成在电荷储存层53的侧面。区块绝缘膜52、隧道绝缘膜54、及芯绝缘膜56例如是氧化硅膜或金属绝缘膜。
图3是表示第1实施方式的半导体装置的制造方法的剖视图。图3表示包含多个阵列芯片1的阵列晶片W1与包含多个电路芯片2的电路晶片W2。阵列晶片W1也被称为存储器晶片，电路晶片W2也被称为CMOS(complementary metal oxide semiconductor，互补金氧半导体)晶片。
应注意图3的阵列晶片W1的方向与图1的阵列芯片1的方向相反。在本实施方式中，通过将阵列晶片W1与电路晶片W2贴合而制造半导体装置。图3表示为了贴合而使方向反转之前的阵列晶片W1，图1表示为了贴合而使方向反转来贴合及切割之后的阵列芯片1。
在图3中，符号S1表示阵列晶片W1的上表面，符号S2表示电路晶片W2的上表面。应注意阵列晶片W1具备设置在绝缘膜12下的衬底16。衬底16例如是硅衬底等半导体衬底。衬底15是第1衬底的例，衬底16是第2衬底的例。
在本实施方式中，首先，如图3所示，在阵列晶片W1的衬底16上形成存储单元阵列11、绝缘膜12、层间绝缘膜13、阶梯构造部21、金属焊垫41等，在电路晶片W2的衬底15上形成层间绝缘膜14、晶体管31、金属焊垫38等。例如，在衬底16上依次形成通孔插塞45、配线44、通孔插塞43、配线42、及金属焊垫41。又，在衬底15上依次形成接触插塞32、配线33、通孔插塞34、配线35、通孔插塞36、配线37、及金属焊垫38。其次，将阵列晶片W1与电路晶片W2通过机械性压力而贴合。由此，将层间绝缘膜13与层间绝缘膜14接着。其次，将阵列晶片W1及电路晶片W2以400℃退火。由此，将金属焊垫41与金属焊垫38接合。
然后，将衬底15通过CMP(Chemical Mechanical Polishing，化学机械抛光)而薄膜化，对衬底16通过CMP进行去除之后，将阵列晶片W1及电路晶片W2切断为多个晶片。如此一来，制造图1的半导体装置。此外，金属焊垫46与钝化膜47例如在衬底15的薄膜化及衬底16的去除之后形成在绝缘膜12上。
此外，在本实施方式中，将阵列晶片W1与电路晶片W2贴合，但也可以取而代之将阵列晶片W1彼此贴合。参照图1至图3所述的内容、参照图4至图23所述的内容也能够应用于阵列晶片W1彼此的贴合。
又，图1表示层间绝缘膜13与层间绝缘膜14的交界面、金属焊垫41与金属焊垫38的交界面，但一般在所述退火后观察不到这些交界面。然而，存在这些交界面的位置例如可通过检测金属焊垫41的侧面、金属焊垫38的侧面的斜率、金属焊垫41的侧面与金属焊垫38的位置偏移来推定。
图4是表示第1实施方式的半导体装置的构造的其它剖视图。
图4(a)表示图1所示的层间绝缘膜14、多条配线37中的1条、及多个金属焊垫38中的1个。以下，对图4(a)所示的层间绝缘膜14、配线37、及金属焊垫38的详细情况进行说明。此外，以下的说明也适用于图1所示的其它配线37、其它金属焊垫38。
层间绝缘膜14交替地包含多个绝缘膜14a与多个绝缘膜14b。绝缘膜14a例如是SiO2膜(氧化硅膜)。绝缘膜14b是与绝缘膜14a不同的绝缘膜，例如是SiCN膜(碳氮化硅膜)。在本实施方式中，可利用绝缘膜14a与绝缘膜14b的蚀刻速率的差异，通过蚀刻来形成配线37用的配线槽、金属焊垫38用的开口部。
配线37包含形成在层间绝缘膜14的侧面及上表面的阻障金属层37a、及介隔阻障金属层37a形成在层间绝缘膜14的侧面及上表面的配线材层37b。阻障金属层37a例如是Ti(钛)膜、TiN膜(氮化钛膜)、Ta(钽)膜、或TaN膜(氮化钽膜)。配线材层37b例如是Cu层。阻障金属层37a是第5层的例，配线材层37b是第6层的例。配线37的厚度例如为500nm。本实施方式的配线37也可以在XY平面内直线状或曲线状地延伸。
金属焊垫38包含形成在层间绝缘膜14的侧面的阻障金属层38a、及介隔阻障金属层38a形成在层间绝缘膜14的侧面且直接形成在配线37(配线材层37b)的上表面的焊垫材层38b。在本实施方式中，由于阻障金属层38a未覆盖配线37的上表面，所以焊垫材层38b与配线37的上表面相接。阻障金属层38a例如是Ti膜、TiN膜、Ta膜、或TaN膜。焊垫材层38b例如是Cu层。阻障金属层38a是第1层的例，焊垫材层38b是第2层的例。金属焊垫38的厚度例如为500nm，金属焊垫38的平面形状例如为正方形或长方形。
此外，配线材层37b与焊垫材层38b也可以为包含Cu元素以外的相同的金属元素的金属层。配线材层37b与焊垫材层38b例如也可以均为Al层，也可以均为W层。
图4(b)除了图4(a)的层间绝缘膜14、配线37、及金属焊垫38以外，还表示图1所示的层间绝缘膜13、多个金属焊垫41中的1个、及多条配线42中的1条。以下，对图4(b)所示的层间绝缘膜13、金属焊垫41、及配线42的详细情况进行说明。此外，以下的说明也适用于图1所示的其它金属焊垫41、其它配线42。
层间绝缘膜13交替地包含多个绝缘膜13a与多个绝缘膜13b。绝缘膜13a例如是SiO2膜。绝缘膜13b是与绝缘膜13a不同的绝缘膜，例如是SiCN膜。在本实施方式中，可利用绝缘膜13a与绝缘膜13b的蚀刻速率的差异，通过蚀刻来形成金属焊垫41用的开口部、配线42用的配线槽。
配线42包含形成在层间绝缘膜13的侧面及下表面的阻障金属层42a、及介隔阻障金属层42a形成在层间绝缘膜13的侧面及下表面的配线材层42b。阻障金属层42a例如是Ti膜、TiN膜、Ta膜、或TaN膜。配线材层42b例如是Cu层。阻障金属层42a是第7层的例，配线材层42b是第8层的例。配线42的厚度例如为500nm。本实施方式的配线42也可以在XY平面内直线状或曲线状地延伸。
金属焊垫41包含形成在层间绝缘膜13的侧面的阻障金属层41a、及介隔阻障金属层41a形成在层间绝缘膜13的侧面且直接形成在配线42(配线材层42b)的下表面的焊垫材层41b。在本实施方式中，由于阻障金属层41a未覆盖配线42的下表面，所以焊垫材层41b与配线42的下表面相接。阻障金属层41a例如是Ti膜、TiN膜、Ta膜、或TaN膜。焊垫材层41b例如是Cu层。阻障金属层41a是第3层的例，焊垫材层41b是第4层的例。金属焊垫41的厚度例如为500nm，金属焊垫41的平面形状例如为正方形或长方形。金属焊垫41形成在金属焊垫38上，焊垫材层41b形成在焊垫材层38b上。
此外，配线材层42b与焊垫材层41b也可以为包含Cu元素以外的相同的金属元素的金属层。配线材层42b与焊垫材层41b例如也可以均为Al层，也可以均为W层。
以下，参照图4(b)，对本实施方式的金属焊垫38、41的更详细情况进行说明。
金属焊垫38例如通过在层间绝缘膜14形成开口部，且在开口部内填埋金属焊垫38的材料，并将该材料的表面通过CMP平坦化而形成。在该情况下，有在金属焊垫38的上表面形成被称为凹陷的凹部，而金属焊垫38不易与金属焊垫41接合的情况。因此，较理想的是使金属焊垫38的厚度变厚，使金属焊垫38的焊垫材层38b的热膨胀量变大。由此，能够将金属焊垫38的上表面的凹陷通过焊垫材层38b的热膨胀而减少，使金属焊垫38与金属焊垫41正常地接合。
然而，为了使金属焊垫38的厚度变厚必须在层间绝缘膜14形成较深的开口部，用来形成开口部的RIE(Reactive Ion Etcing，反应性离子蚀刻)变得困难。进而，必须使金属焊垫38的材料变厚、使CMP研磨量变多，金属焊垫38的形成变得困难。结果，有产生电路芯片2的芯片厚度增大、半导体装置的制造成本增大、金属焊垫38的形状的不均等问题的担忧。
因此，在本实施方式中，通过不在配线37的上表面形成金属焊垫38的阻障金属层38a，而将金属焊垫38的焊垫材层38b直接形成在配线37的配线材层37b的上表面。因此，根据本实施方式，能够通过金属焊垫38的焊垫材层38b的热膨胀与配线37的配线材层37b的热膨胀，减少金属焊垫38的上表面的凹陷。换句话说，根据本实施方式，关于热膨胀，能够使金属焊垫38与配线37作为实效性的金属焊垫发挥功能。相对于金属焊垫38的厚度为500nm，而实效性的金属焊垫的厚度为1μm。根据本实施方式，能够使金属焊垫38的焊垫材层38b与配线37的配线材层37b一体化，由此能够利用较薄的金属焊垫38获得与较厚的金属焊垫相同的效果。具体而言，能够利用较薄的焊垫材层38b(Cu层)，获得与较厚的焊垫材层(Cu层)相同的热膨胀量。
进而，根据本实施方式，能够抑制使金属焊垫38变厚的情况下的问题。例如，无须在层间绝缘膜14形成较深的开口部，用来形成开口部的RIE变得容易。例如，又，无须使金属焊垫38的材料变厚、使CMP研磨量变多，金属焊垫38的形成变得容易。进而，由于包含配线37的配线层也可以用作通常的配线层，所以也可以抑制由配置配线37所致的电路芯片2的芯片厚度增大。包含配线37的配线层例如用于电源配线用。
以上情况对于金属焊垫41也同样地成立。在本实施方式中，通过不在配线42的下表面形成金属焊垫41的阻障金属层41a，而将金属焊垫41的焊垫材层41b直接形成在配线42的配线材层42b的下表面。因此，根据本实施方式，能够通过金属焊垫41的焊垫材层41b的热膨胀与配线42的配线材层42b的热膨胀，而减少金属焊垫41的下表面的凹陷。
像以上一样，根据本实施方式，能够形成适合于贴合的金属焊垫38、41。
图5是表示第1实施方式的比较例的半导体装置的构造的剖视图。
图5(a)表示与图4(a)相同的层间绝缘膜14、配线37、及金属焊垫38与多个通孔插塞39。以下，对这些通孔插塞39中的任意1个的详细情况进行说明。
通孔插塞39形成在配线37与金属焊垫38之间。通孔插塞39包含与金属焊垫38相同的阻障金属层38a及焊垫材层(插塞材层)38b。此种通孔插塞39及金属焊垫38能够通过双道金属镶嵌法而形成。本比较例的焊垫材层38b介隔阻障金属层38a形成在配线37上。
图5(b)表示图5(a)的层间绝缘膜14、配线37、金属焊垫38、及多个通孔插塞39与图4(b)的层间绝缘膜13、金属焊垫41、及配线42、及多个通孔插塞48。以下，对这些通孔插塞48中的任意1个的详细情况进行说明。
通孔插塞48形成在金属焊垫41与配线42之间。通孔插塞48包含与金属焊垫41相同的阻障金属层41a及焊垫材层(插塞材层)41b。此种通孔插塞48及金属焊垫41能够通过双道金属镶嵌法而形成。本比较例的焊垫材层41b介隔阻障金属层41a形成在配线42下。
以下，参照图5(b)对本比较例的金属焊垫38、41的更详细情况进行说明。
在本比较例中，在金属焊垫38及通孔插塞39的焊垫材层38b与配线37的配线材层37b之间，形成着阻障金属层38a。因此，金属焊垫38的上表面的凹陷通过焊垫材层38b的热膨胀而减少，但不会通过配线材层37b的热膨胀而减少。因此，在本比较例中，必须使金属焊垫38的厚度变厚。本比较例的金属焊垫38、通孔插塞39、及配线37的厚度例如为1μm、200nm、及500nm。以上情况对于本比较例的金属焊垫41也同样地成立。
另一方面，在本实施方式中，未在金属焊垫38的焊垫材层38b与配线37的配线材层37b之间形成阻障金属层38a。因此，根据本实施方式，使金属焊垫38的上表面的凹陷不仅能够通过焊垫材层38b的热膨胀而减少，而且也能够通过配线材层37b的热膨胀而减少。根据本实施方式，能够通过较薄的金属焊垫38等而获得此种效果。应注意相对于比较例的金属焊垫38、通孔插塞39、及配线37的合计厚度为1.7μm，而本实施方式的金属焊垫38及配线37的合计厚度为1μm。
此外，以上的说明在本比较例的金属焊垫38及通孔插塞39利用单金属镶嵌法形成的情况下、本比较例的金属焊垫41及通孔插塞48利用单金属镶嵌法形成的情况下也同样地成立。
图6至图9是表示第1实施方式的半导体装置的制造方法的剖视图。这些图所示的步骤是在制造图4(a)或图4(b)所示的半导体装置时进行，在图3所示的步骤中对电路晶片W2进行。
首先，在未图示的衬底15的上方，依次形成绝缘膜14a、绝缘膜14b、及绝缘膜14a(图6(a))。其次，在后者的绝缘膜14a及绝缘膜14b内，通过RIE而形成配线槽H1(图6(b))。其次，在衬底15的整个面，依次形成阻障金属层37a与配线材层37b(图7(a))。结果，阻障金属层37a形成在配线槽H1的侧面及底面，配线材层37b介隔阻障金属层37a形成在配线槽H1的侧面及底面。其次，将配线材层37b及阻障金属层37a的表面通过CMP而平坦化(图7(b))。结果，将配线槽H1外的阻障金属层37a及配线材层37b去除，将包含阻障金属层37a与配线材层37b的配线37形成在配线槽H1内。
其次，在衬底15的上方，依次形成绝缘膜14b与绝缘膜14a(图8(a))。其次，在这些绝缘膜14a及绝缘膜14b内，通过RIE而形成开口部H2(图8(b))。结果，配线37的上表面在开口部H2内露出。其次，在衬底15的整个面，依次形成阻障金属层38a与焊垫材层38b(图9(a))。结果，阻障金属层38a形成在开口部H2的侧面。进而，焊垫材层38b介隔阻障金属层38a形成在开口部H2的侧面，且直接形成在开口部H2的底面的配线37(配线材层37b)上。关于形成此种阻障金属层38a及焊垫材层38b的方法的例将在下文叙述。其次，将焊垫材层38b及阻障金属层38a的表面通过CMP而平坦化(图9(b))。结果，将开口部H2外的阻障金属层38a及焊垫材层38b去除，包含阻障金属层38a与焊垫材层38b的金属焊垫38形成在开口部H2内。
这些图所示的步骤在图3所示的步骤中对阵列晶片W1也同样地进行。具体而言，这些图所示的步骤是分别将衬底15、层间绝缘膜14、配线37、金属焊垫38置换为衬底16、层间绝缘膜13、配线42、金属焊垫41后进行。然后，在图3所示的步骤中将阵列晶片W1与电路晶片W2贴合，制造本实施方式的半导体装置。
图10及图11是表示第1实施方式的半导体装置的制造方法的第1例的剖视图。这些图所示的步骤表示图9(a)的步骤的一例。
首先，在衬底15的整个面沉积阻障金属层38a(图10(a))。结果，阻障金属层38a形成在开口部H2内的配线37的上表面、开口部H2内的层间绝缘膜14的侧面、及开口部H2外的层间绝缘膜14的上表面。此时，通过沉积阻障金属层38a的步骤的特性，而开口部H2内的配线37上的阻障金属层38a比开口部H2外的层间绝缘膜14上的阻障金属层38a变薄。
其次，将阻障金属层38a通过使用氩气(Ar)的再溅射而薄膜化(图10(b))。由此，可将开口部H2内的配线37上的阻障金属层38a去除。结果，配线37的上表面在开口部H2内再次露出。此外，开口部H2外的层间绝缘膜14上的阻障金属层38a比开口部H2内的配线37上的阻障金属层38a厚，所以未完全去除而薄膜化。又，通过再溅射的特性，也在开口部H2内的层间绝缘膜14的侧面残存阻障金属层38a。
在图10(b)的步骤中，有也将配线材层37b的一部分去除，而在配线材层37b的上表面形成凹部的可能性。图10(b)表示此种凹部的例。此外，如果将开口部H2的底面的阻障金属层38a去除，那么存在通过该阻障金属层38a的去除而产生的原子附着在开口部H2的侧面的阻障金属层38a的情形。在该情况下，开口部H2的侧面的阻障金属层38a的厚度通过此种原子的附着而变厚。
其次，在衬底15的整个面形成焊垫材层38b(图11(a))。结果，焊垫材层38b介隔阻障金属层38a形成在开口部H2的侧面，且直接形成在开口部H2的底面的配线37(配线材层37b)上。
其次，将焊垫材层38b及阻障金属层38a的表面通过CMP而平坦化(图11(b))。结果，将开口部H2外的阻障金属层38a及焊垫材层38b去除，包含阻障金属层38a与焊垫材层38b的金属焊垫38形成在开口部H2内。
图12及图13是表示第1实施方式的半导体装置的制造方法的第2例的剖视图。这些图所示的步骤表示图9(a)的步骤的其它例。
首先，在衬底15的整个面，通过溅镀而沉积金属层38c(图12(a))。结果，金属层38c形成在开口部H2内的配线37的上表面、开口部H2内的层间绝缘膜14的侧面、及开口部H2外的层间绝缘膜14的上表面。金属层38c例如是CuMn晶种层(Mn表示锰)。金属层38c是第1膜的例。
其次，在衬底15的整个面，通过镀覆法形成金属层38d(图12(b))。结果，金属层38d介隔金属层38c形成在开口部H2的侧面及底面。金属层38d例如是Cu层。金属层38d是第2膜的例。
其次，将金属层38c、38d等退火(图13(a))。结果，金属层38c的一部分通过层间绝缘膜14中的Si原子或O原子的影响，而变质为金属层38c1。金属层38c1例如是MnSiXOY层(X及Y为正整数)。另一方面，金属层38c的另一部分变质为金属层38c2。金属层38c2例如是Cu层。另一方面，存在金属层38c中的Mn原子扩散至金属层38d的上表面的情形。图13(a)表示通过该扩散而产生在金属层38d内的金属层38d1、38d2。金属层38d1例如是Cu层，金属层38d2例如是CuMn层。如此一来，形成包含金属层38c1的阻障金属层38a、及包含金属层38c2与金属层38d1的焊垫材层38b。
此外，由于金属层38c1是通过层间绝缘膜14中的Si原子或O原子的影响而产生，所以形成在开口部H2的侧面，但不形成在开口部H2的底面。结果，金属层38c2介隔金属层38c1形成在开口部H2的侧面，且直接形成在开口部H2的底面的配线37(配线材层37b)上。
其次，将金属层38d2、38d1、38c2、38c1的表面通过CMP而平坦化(图13(b))。结果，将开口部H2外的金属层38d2、38d1、38c2、38c1去除，包含金属层38c1、38c2、38d1的金属焊垫38形成在开口部H2内。也就是说，包含阻障金属层38a与焊垫材层38b的金属焊垫38形成在开口部H2内。
图14是用来将第1实施方式的半导体装置与其比较例的半导体装置进行比较的俯视图。
图14(a)表示图5(a)所示的比较例的半导体装置的平面构造的例。图14(a)表示多条配线37、配置在这些配线37上的多个通孔插塞39、及配置在这些通孔插塞39上的多个金属焊垫38。
但是，图14(a)不仅表示配置在配线37及通孔插塞39上的金属焊垫38，而且也表示未配置在配线37及通孔插塞39上的金属焊垫38。后者的金属焊垫38是为了将半导体装置内的构成要素彼此电连接而未使用的虚设焊垫。
图14(b)表示了图4(a)所示的第1实施方式的半导体装置的平面构造的例。图14(b)表示了多条配线37、及配置在这些配线37上的多个金属焊垫38。
图14(b)所示的金属焊垫38不包含如上所述的虚设焊垫。理由在于，由于本实施方式的金属焊垫38直接形成在配线37上，所以如果配置虚设焊垫，那么虚设焊垫在配置配线37时成为障碍。但是，在必须配置虚设焊垫的情况下，也可以配置当配置配线37时不成为障碍的个数、配置的虚设焊垫。
图14(b)所示的金属焊垫38的上表面具有与图14(b)所示的配线37的上表面大致相同的尺寸。此外，金属焊垫38的上表面的尺寸也可以大于配线37的上表面的尺寸，也可以小于配线37的上表面的尺寸。
图15是用来将第1实施方式的半导体装置与其比较例的半导体装置进行比较的其它俯视图。
图15(a)表示图5(a)所示的比较例的半导体装置的平面构造的其它例。图15(a)表示多条配线37、配置在这些配线37上的多个通孔插塞39、及配置在这些通孔插塞39上的多个金属焊垫38。图15(a)所示的配线37的上表面具有图15(a)所示的金属焊垫38的上表面的约一半的尺寸。又，图15(a)所示的金属焊垫38与图14(a)所示的金属焊垫38相同地，包含虚设焊垫。
图15(b)表示图4(a)所示的第1实施方式的半导体装置的平面构造的其它例。图15(b)表示多条配线37、及配置在这些配线37上的多个金属焊垫38。又，图15(b)所示的金属焊垫38与图14(b)所示的金属焊垫38相同地，不包含虚设焊垫。
此处，图15(b)所示的配线37的上表面具有与图15(a)所示的配线37的上表面相同的尺寸。也就是说，图15(b)所示的配线37的上表面具有图14(b)所示的配线37的上表面的约一半的尺寸。因此，在该例中，图15(b)所示的金属焊垫38的上表面的尺寸也设定为图14(b)所示的金属焊垫38的上表面的尺寸的约一半。如此，在本实施方式中，在减少配线37的尺寸的情况下，金属焊垫38的尺寸也可以减少。由此，例如，能够减少金属焊垫38相对于配线37的偏离。
此外，在下述第2实施方式中，在配线37与金属焊垫38之间，与所述比较例相同地配置通孔插塞。因此，第2实施方式的金属焊垫38与本比较例的金属焊垫38相同地，也可以包含多个虚设焊垫。
参照图14(a)至图15(b)所说明的内容不仅适用于电路芯片2而且也适用于阵列芯片1。在该情况下，该说明内的配线37、通孔插塞39、及金属焊垫38分别置换为配线42、通孔插塞48、及金属焊垫41。
像以上一样，本实施方式的金属焊垫38包含设置在层间绝缘膜14内的阻障金属层38a、及介隔阻障金属层38a设置在层间绝缘膜14内且与配线37直接相接的焊垫材层38b。同样地，本实施方式的金属焊垫41包含设置在层间绝缘膜13内的阻障金属层41a、及介隔阻障金属层41a设置在层间绝缘膜13内且与配线42直接相接的焊垫材层41b。
因此，根据本实施方式，能够形成适合于贴合的金属焊垫38、41。例如，能够将金属焊垫38、41的厚度设定得较薄，且使实效性的金属焊垫的厚度变厚。
(第2实施方式)
图16是表示第2实施方式的半导体装置的构造的剖视图。
图16(a)具备与图4(a)相同的层间绝缘膜14、配线37、及金属焊垫38与多个通孔插塞61。这些通孔插塞61是第1插塞的例。本实施方式的配线37、通孔插塞61、及金属焊垫38的厚度例如为500μm、200nm、及300nm。因此，本实施方式的配线37、通孔插塞61、及金属焊垫38的合计厚度与第1实施方式的配线37及金属焊垫38的合计厚度相同地为1μm。以下，对这些通孔插塞61中的任意1个的详细情况进行说明。
通孔插塞61形成在配线37与金属焊垫38之间。通孔插塞61包含与金属焊垫38相同的阻障金属层38a及焊垫材层(插塞材层)38b。此种通孔插塞61及金属焊垫38能够通过双道金属镶嵌法而形成。
但是，相对于所述比较例的焊垫材层38b介隔阻障金属层38a形成在配线37上，本实施方式的焊垫材层38b直接形成在配线37上。本实施方式的此种阻障金属层38a及焊垫材层38b例如如下所述，能够通过进行与图10(a)至图11(b)所示的步骤、图12(a)至图13(b)所示的步骤相同的处理而形成。此外，应注意本实施方式的阻障金属层38a不覆盖通孔插塞61下的配线37的上表面，但覆盖金属焊垫38下的层间绝缘膜14的上表面。
图16(b)除了图16(a)所示的构成要素以外，还表示与图4(b)相同的层间绝缘膜13、金属焊垫41、及配线42与多个通孔插塞62。这些通孔插塞62是第2插塞的例。本实施方式的金属焊垫41、通孔插塞62、及配线42的厚度例如为300μm、200nm、及500nm。因此，本实施方式的金属焊垫41、通孔插塞62、及配线42的合计厚度与第1实施方式的金属焊垫41及配线42的合计厚度相同地为1μm。以下，对这些通孔插塞62中的任意1个的详细情况进行说明。
通孔插塞62形成在金属焊垫41与配线42之间。通孔插塞62包含与金属焊垫41相同的阻障金属层41a及焊垫材层(插塞材层)42b。此种通孔插塞62及金属焊垫41能够通过双道金属镶嵌法而形成。
但是，相对于所述比较例的焊垫材层41b介隔阻障金属层41a形成在配线42下，本实施方式的焊垫材层41b直接形成在配线42下。本实施方式的此种阻障金属层41a及焊垫材层41b例如如下所述，能够通过进行与图10(a)至图11(b)所示的步骤、图12(a)至图13(b)所示的步骤相同的处理而形成。此外，应注意本实施方式的阻障金属层41a不覆盖通孔插塞42上的配线37的下表面，但覆盖金属焊垫41上的层间绝缘膜13的下表面。
以下，参照图16(b)，对本实施方式的金属焊垫38、41的更详细情况进行说明。
在本实施方式中，通过不将金属焊垫38及通孔插塞61的阻障金属层38a形成在配线37的上表面，而将金属焊垫38及通孔插塞61的焊垫材层(插塞材层)38b直接形成在配线37的配线材层37b的上表面。因此，根据本实施方式，与第1实施方式相同，能够通过焊垫材层38b的热膨胀与配线材层37b的热膨胀，而减少金属焊垫38的上表面的凹陷。换句话说，根据本实施方式，关于热膨胀，能够使金属焊垫38、通孔插塞61、及配线37作为实效性的金属焊垫发挥功能。相对于金属焊垫38的厚度为300nm，实效性的金属焊垫的厚度为1μm。根据本实施方式，能够使焊垫材层38b与配线材层37b一体化，由此能够利用较薄的金属焊垫38获得与较厚的金属焊垫相同的效果。具体而言，能够利用较薄的焊垫材层38b(Cu层)获得与较厚的焊垫材层(Cu层)相同的热膨胀量。
以上情况对于金属焊垫41也同样地成立。在本实施方式中，通过不将金属焊垫41及通孔插塞62的阻障金属层41a形成在配线42的下表面，而将金属焊垫41及通孔插塞62的焊垫材层(插塞材层)41b直接形成在配线42的配线材层42b的下表面。因此，根据本实施方式，能够通过焊垫材层41b的热膨胀与配线材层42b的热膨胀，而减少金属焊垫41的下表面的凹陷。
像以上一样，根据本实施方式，能够形成适合于贴合的金属焊垫38、41。
此外，本实施方式的金属焊垫38的上表面的凹陷在通孔插塞61的正上方的位置大幅度减少，但在通孔插塞61的正上方以外的位置未大幅度减少。理由在于，通孔插塞61的膨胀作用主要波及通孔插塞61的正上方的位置。因此，关于减少凹陷的作用，一般来说第1实施方式大于第2实施方式。另一方面，根据第2实施方式，如上所述，例如能够配置多个虚设焊垫。以上情况对于金属焊垫41也同样地成立。
图17是表示第2实施方式的变化例的半导体装置的构造的剖视图。
在图17(a)中，将图16(a)的多个较小的通孔插塞61置换为较大的通孔插塞63。同样地，在图17(b)中，将图16(b)的多个较小的通孔插塞62置换为较大的通孔插塞64。通孔插塞63、64的性质除了平面形状的尺寸以外，与通孔插塞61、62的性质相同。通孔插塞63是第1插塞的例，通孔插塞64是第2插塞的例。
根据本变化例，与第2实施方式相同，能够形成适合于贴合的金属焊垫38、41。又，根据本变化例，与第2实施方式相比，能够将减少凹陷的作用波及至通孔插塞63的正上方的较广区域。理由在于，通孔插塞63的尺寸较大。换句话说，根据本变化例，能够享受第2实施方式的优点，且也能够享受第1实施方式的优点。以上情况对于金属焊垫41也同样地成立。
图18及图19是表示第2实施方式的半导体装置的制造方法的剖视图。这些图所示的步骤是在制造图16(a)或图16(b)所示的半导体装置时进行，在图3所示的步骤中对电路晶片W2进行。
首先，实施图6(a)至图7(b)的步骤。结果，在未图示的衬底15的上方，形成包含阻障金属层37a与配线材层37b的配线37(图18(a))。其次，在衬底15的上方，依次形成绝缘膜14b、绝缘膜14a、绝缘膜14b、及绝缘膜14a(图18(a))。其次，在后者的绝缘膜14a及后者的绝缘膜14b内，通过RIE形成开口部H3(图18(a))。其次，在前者的绝缘膜14a及前者的绝缘膜14b内，通过RIE形成多个导孔H4(图18(b))。结果，配线37的上表面在开口部H3下的这些导孔H4内露出。
其次，在衬底15的整个面，依次形成阻障金属层38a与焊垫材层38b(图19(a))。结果，阻障金属层38a形成在开口部H3的侧面及底面、导孔H4的侧面。进而，焊垫材层38b介隔阻障金属层38a形成在开口部H3的侧面及底面、导孔H4的侧面，且直接形成在导孔H4的底面的配线37(配线材层37b)上。关于形成此种阻障金属层38a及焊垫材层38b的方法的例将在下文叙述。其次，将焊垫材层38b及阻障金属层38a的表面通过CMP而平坦化(图19(b))。结果，将除开口部H3及导孔H4以外的阻障金属层38a及焊垫材层38b去除，包含阻障金属层38a与焊垫材层38b的金属焊垫38形成在开口部H3内，包含阻障金属层38a与焊垫材层38b的通孔插塞61形成在导孔H4内。
这些图所示的步骤在图3所示的步骤中对阵列晶片W1也同样地进行。具体而言，这些图所示的步骤是将衬底15、层间绝缘膜14、配线37、通孔插塞61、金属焊垫38分别置换为衬底16、层间绝缘膜13、配线42、通孔插塞62、金属焊垫41而进行。然后，在图3所示的步骤中将阵列晶片W1与电路晶片W2贴合，而制造本实施方式的半导体装置。
此外，以上的方法也能够应用于制造图17(a)或图17(b)所示的半导体装置时。在该情况下，将与通孔插塞61、62相关的步骤置换为与通孔插塞63、64相关的步骤。例如，将多个较小的导孔H4置换为较大的1个导孔。
图20及图21是表示第2实施方式的半导体装置的制造方法的第1例的剖视图。这些图所示的步骤表示图19(a)的步骤的一例。
首先，在衬底15的整个面沉积阻障金属层38a(图20(a))。结果，阻障金属层38a形成在导孔H4内的配线37的上表面、导孔H4及开口部H3内的层间绝缘膜14的侧面及上表面、以及除导孔H4及开口部H3以外的层间绝缘膜14的上表面。此时，通过沉积阻障金属层38a的步骤的特性，而导孔H4内的配线37上的阻障金属层38a比开口部H3内的层间绝缘膜14的上表面的阻障金属层38a变薄，开口部H3内的层间绝缘膜14的上表面的阻障金属层38a比除导孔H4及开口部H3以外的层间绝缘膜14上的阻障金属层38a变薄。
其次，将阻障金属层38a通过使用氩气的再溅射而薄膜化(图20(b))。由此，可将导孔H4内的配线37上的阻障金属层38a去除。结果，配线37的上表面在导孔H4内再次露出。此外，由于开口部H3内的层间绝缘膜14的上表面的阻障金属层38a、除导孔H4及开口部H3以外的层间绝缘膜14上的阻障金属层38a，比导孔H4内的配线37上的阻障金属层38a厚，所以未完全去除而薄膜化。又，通过再溅射的特性，而在导孔H4及开口部H3内的层间绝缘膜14的侧面也残存阻障金属层38a。
在图20(b)的步骤中，存在将配线材层37b的一部分也去除，而在配线材层37b的上表面形成凹部的可能性。图20(b)表示了此种凹部的例。此外，存在如果将导孔H4的底面的阻障金属层38a去除，那么通过该阻障金属层38a的去除而产生的原子附着在导孔H4的侧面的阻障金属层38a的情形。在该情况下，导孔H4的侧面的阻障金属层38a的厚度通过此种原子的附着而变厚。该情况对于开口部H3内的阻障金属层38a也相同。
其次，在衬底15的整个面形成焊垫材层38b(图21(a))。结果，焊垫材层38b介隔阻障金属层38a形成在开口部H3的侧面及底面、导孔H4的侧面，且直接形成在导孔H4的底面的配线37(配线材层37b)上。
其次，将焊垫材层38b及阻障金属层38a的表面通过CMP而平坦化(图21(b))。结果，将导孔H4及开口部H3外的阻障金属层38a及焊垫材层38b去除，包含阻障金属层38a与焊垫材层38b的金属焊垫38形成在开口部H3内，包含阻障金属层38a与焊垫材层38b的通孔插塞61形成在导孔H4内。
图22及图23是表示第2实施方式的半导体装置的制造方法的第2例的剖视图。这些图所示的步骤表示图19(a)的步骤的其它例。
首先，在衬底15的整个面，通过溅镀沉积金属层38c(图22(a))。结果，金属层38c形成在导孔H4内的配线37的上表面、导孔H4及开口部H3内的层间绝缘膜14的侧面及上表面、以及除导孔H4及开口部H3外的层间绝缘膜14的上表面。金属层38c例如是CuMn晶种层。金属层38c是第1膜的例。
其次，在衬底15的整个面，通过镀覆法而形成金属层38d(图22(b))。结果，金属层38d介隔金属层38c形成在导孔H4及开口部H3的侧面及底面。金属层38d例如是Cu层。金属层38d是第2膜的例。
其次，将金属层38c、38d等退火(图23(a))。结果，金属层38c的一部分通过层间绝缘膜14中的Si原子或O原子的影响，而变质为金属层38c1。金属层38c1例如是MnSiXOY层。另一方面，金属层38c的另一部分变质为金属层38c2。金属层38c2例如是Cu层。另一方面，存在金属层38c中的Mn原子扩散至金属层38d的上表面的情形。图13(a)表示通过该扩散而产生在金属层38d内的金属层38d1、38d2。金属层38d1例如是Cu层，金属层38d2例如是CuMn层。如此一来，形成包含金属层38c1的阻障金属层38a与包含金属层38c2与金属层38d1的焊垫材层38b。
此外，由于金属层38c1通过层间绝缘膜14中的Si原子或O原子的影响而产生，所以形成在开口部H3的侧面及底面、导孔H4的侧面，但不形成在导孔H4的底面。结果，金属层38c2介隔金属层38c1形成在开口部H3的侧面及底面、导孔H4的侧面，且直接形成在导孔H4的底面的配线37(配线材层37b)上。
其次，将金属层38d2、38d1、38c2、38c1的表面通过CMP而平坦化(图23(b))。结果，将除导孔H4及开口部H3以外的金属层38d2、38d1、38c2、38c1去除，包含金属层38c1、38c2、38d1的金属焊垫38形成在开口部H3内，包含金属层38c1、38c2、38d1的通孔插塞38形成在导孔H4内。也就是说，包含阻障金属层38a与焊垫材层38b的金属焊垫38形成在开口部H3内，包含阻障金属层38a与焊垫材层38b的通孔插塞61形成在导孔H4内。
像以上一样，本实施方式的金属焊垫38及通孔插塞61(或63)包含设置在层间绝缘膜14内的阻障金属层38a、及介隔阻障金属层38a设置在层间绝缘膜14内且与配线37直接相接的焊垫材层38b。同样地，本实施方式的金属焊垫41及通孔插塞62(或64)包含设置在层间绝缘膜13内的阻障金属层41a、及介隔阻障金属层41a设置在层间绝缘膜13内且与配线42直接相接的焊垫材层41b。
因此，根据本实施方式，与第1实施方式相同地，能够形成适合于贴合的金属焊垫38、41。例如，能够将金属焊垫38、41的厚度设定得较薄，且使实效性的金属焊垫的厚度变厚。
以上，对几个实施方式进行了说明，但这些实施方式是仅作为例而提出的，并不旨在限定发明的范围。本说明书中所说明的新颖的装置及方法能够以其它各种形态实施。又，可对本说明书中所说明的装置及方法的形态，在不脱离发明主旨的范围内，进行各种省略、置换、变更。随附的权利要求书及其均等的范围意图包含发明的范围、主旨中所包含的此种形态、变化例。
[符号的说明]
1 阵列芯片
2 电路芯片
11 存储单元阵列
12 绝缘膜
13、14 层间绝缘膜
13a、13b、14a、14b 绝缘膜
15、16 衬底
21 阶梯构造部
22 接触插塞
23 字元配线层
24 通孔插塞
31 晶体管
32 接触插塞
33 配线
34 通孔插塞
35 配线
36 通孔插塞
37 配线
37a 阻障金属层
37b 配线材层
38 金属焊垫
38a 阻障金属层
38b 焊垫材层(插塞材层)
38c、38c1、38c2、38d1、38d2 金属层
39 通孔插塞
41 金属焊垫
41a 阻障金属层
41b 焊垫材层(插塞材层)
42 配线
42a 阻障金属层
42b 配线材层
43 通孔插塞
44 配线
45 通孔插塞
46 金属焊垫
47 钝化膜
48 通孔插塞
51 绝缘层
52 区块绝缘膜
53 电荷储存层
54 隧道绝缘膜
55 通道半导体层
56 芯绝缘膜
61、62、63、64 通孔插塞

Claims (20)

1.一种半导体装置，其特征在于包括：
衬底；
第1绝缘膜，设置在所述衬底的上方；
第1配线，设置在所述第1绝缘膜内；
第1焊垫，在所述第1绝缘膜内，设置在所述第1配线上；
第2绝缘膜，设置在所述第1绝缘膜之上；
第2焊垫，在所述第2绝缘膜内，设置在所述第1焊垫上；以及
第2配线，在所述第2绝缘膜内，设置在的所述第2焊垫上；
所述第1焊垫包括：第1金属层以及第2金属层，所述第1金属层设置在所述第1绝缘膜内，所述第2金属层介隔所述第1金属层设置在所述第1绝缘膜内且与所述第1配线直接相接的。
2.根据权利要求1所述的半导体装置，其特征在于：
所述第2焊垫包括：第3金属层以及第4金属层，所述第3金属层设置在所述第2绝缘膜内，所述第4金属层介隔所述第3金属层设置在所述第2绝缘膜内且与所述第2配线直接相接。
3.根据权利要求1所述的半导体装置，其特征在于进而包括：
设置在所述第1绝缘膜内的所述第1配线与所述第1焊垫之间的第1插塞，
所述第1插塞包括所述第1金属层、及与所述第1配线直接相接的所述第2金属层。
4.根据权利要求2所述的半导体装置，其特征在于进而包括：
设置在所述第2绝缘膜内的所述第2焊垫与所述第2配线之间的第2插塞，
所述第2插塞包括所述第3金属层、及与所述第2配线直接相接的所述第4金属层。
5.根据权利要求1所述的半导体装置，其特征在于：
所述第1配线包括：第5金属层以及第6金属层，所述第5金属层设置在所述第1绝缘膜内，所述第6金属层介隔所述第5金属层设置在所述第1绝缘膜内且与所述第2金属层直接相接。
6.根据权利要求5所述的半导体装置，其特征在于：
所述第2金属层与所述第6金属层含有相同的金属元素。
7.根据权利要求1所述的半导体装置，其特征在于：
所述第2配线包含：第7金属层以及第8金属层，所述第7金属层设置在所述第2绝缘膜内所述第8金属层介隔所述第7金属层设置在所述第2绝缘膜内且与所述第4金属层直接相接。
8.根据权利要求7所述的半导体装置，其特征在于：
所述第4金属层与所述第8金属层含有相同的金属元素。
9.根据权利要求1所述的半导体装置，其特征在于：
所述第2金属层含有Cu。
10.根据权利要求9所述的半导体装置，其特征在于：
所述第2金属层进而含有Ti、Mn、Zn、Al、Sn、V、W中的至少一种元素。
11.一种半导体装置的制造方法，其特征在于包括：
在第1衬底的上方形成第1绝缘膜；
在所述第1绝缘膜内形成第1配线；
在所述第1绝缘膜内，在所述第1配线上形成第1焊垫；
在第2衬底的上方形成第2绝缘膜；
在所述第2绝缘膜内形成第2配线；
在所述第2绝缘膜内，在所述第2配线上形成第2焊垫；以及
通过将所述第1焊垫与所述第2焊垫贴合，而在所述第1焊垫上配置所述第2焊垫；
所述第1焊垫包括：第1金属层以及第2金属层，所述第1金属层设置在所述第1绝缘膜内，所述第2金属层介隔所述第1金属层设置在所述第1绝缘膜内且与所述第1配线直接相接，
在所述第1焊垫的形成中，
在所述第1绝缘膜的侧面以及所述第1配线的上表面形成第1金属层，
使所述第1金属层残存在所述第1绝缘膜的侧面，且自所述第1配线的上表面去除所述第1金属层，而使所述第1配线露出，
在所述第1金属层的侧面以及所述第1配线的露出面形成第2金属层。
12.根据权利要求11所述的半导体装置的制造方法，其特征在于：
所述第2焊垫包括：第3金属层以及第4金属层，所述第3金属层设置在所述第2绝缘膜内，所述第4金属层介隔所述第3金属层设置在所述第2绝缘膜内且与所述第2配线直接相接，
在所述第2焊垫的形成中，在所述第2绝缘膜的侧面与所述第2配线的上表面形成所述第3金属层，并且使所述第3金属层残存在所述第2绝缘膜的侧面，且自所述第2配线的上表面去除所述第3金属层，在所述第3金属层的侧面与所述第2配线的上表面形成所述第4金属层。
13.根据权利要求11所述的半导体装置的制造方法，其特征在于进而包括：
设置在所述第1绝缘膜内的所述第1配线与所述第1焊垫之间的第1插塞，
所述第1插塞包括所述第1金属层、及与所述第1配线直接相接的所述第2金属层。
14.根据权利要求12的半导体装置的制造方法，其特征在于进而包括：
设置在所述第2绝缘膜内的所述第2焊垫与所述第2配线之间的第2插塞，
所述第2插塞包括所述第3金属层、及与所述第2配线直接相接的所述第4金属层。
15.根据权利要求11所述的半导体装置的制造方法，其特征在于：
所述第1配线包含：第5金属层以及第6金属层，所述第5金属层设置在所述第1绝缘膜内，所述第6金属层介隔所述第5金属层设置在所述第1绝缘膜内且与所述第2金属层直接相接。
16.根据权利要求15所述的半导体装置的制造方法，其特征在于：
所述第2金属层与所述第6金属层包括相同的金属元素。
17.根据权利要求11所述的半导体装置的制造方法，其特征在于：
所述第2配线包括：第7金属层以及第8金属层，所述第7金属层设置在所述第2绝缘膜内，所述第8金属层介隔所述第7金属层设置在所述第2绝缘膜内且与所述第4金属层直接相接的第8金属层。
18.根据权利要求17所述的半导体装置的制造方法，其特征在于：
所述第4金属层与所述第8金属层含有相同的金属元素。
19.一种半导体装置的制造方法，其特征在于包括：
在第1衬底的上方形成第1绝缘膜；
在所述第1绝缘膜内形成第1配线；
在所述第1绝缘膜内，在所述第1配线上形成第1焊垫；
在第2衬底的上方形成第2绝缘膜；
在所述第2绝缘膜内形成第2配线；
在所述第2绝缘膜内，在所述第2配线上形成第2焊垫；以及
通过将所述第1焊垫与所述第2焊垫贴合，而在所述第1焊垫上配置所述第2焊垫；
所述第1焊垫包括：第1金属层以及第2金属层，所述第1金属层设置在所述第1绝缘膜内，所述第2金属层介隔所述第1金属层设置在所述第1绝缘膜内且与所述第1配线直接相接，
在所述第1焊垫的形成中，在所述第1绝缘膜的侧面与所述第1配线的上表面依次形成第1膜以及第2膜，使所述第1膜的一部分变质而形成所述第1金属层，通过所述第1膜的另一部分与所述第2膜而形成所述第2金属层。
20.根据权利要求19的半导体装置的制造方法，其特征在于：
所述第2焊垫包括：第3金属层以及第4金属层，所述第3金属层设置在所述第2绝缘膜内，所述第4金属层介隔所述第3金属层设置在所述第2绝缘膜内且与所述第2配线直接相接，
在所述第2焊垫的形成中，在所述第2绝缘膜的侧面与所述第2配线的上表面依次形成第3膜及第4膜，使所述第3膜的一部分变质而形成所述第3金属层，通过所述第3膜的另一部分与所述第4膜而形成所述第4金属层。
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