TW202133369A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW202133369A
TW202133369A TW109128101A TW109128101A TW202133369A TW 202133369 A TW202133369 A TW 202133369A TW 109128101 A TW109128101 A TW 109128101A TW 109128101 A TW109128101 A TW 109128101A TW 202133369 A TW202133369 A TW 202133369A
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Taiwan
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metal layer
wiring
insulating film
pad
layer
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TW109128101A
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TWI743954B (zh
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田上政由
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日商鎧俠股份有限公司
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Abstract

實施方式提供一種能夠形成適合於貼合之焊墊之半導體裝置及其製造方法。  根據一實施方式，半導體裝置具備基板、設置於上述基板之上方之第1絕緣膜、設置於上述第1絕緣膜內之第1配線、於上述第1絕緣膜內設置於上述第1配線上之第1焊墊、設置於上述第1絕緣膜之上之第2絕緣膜、於上述第2絕緣膜內設置於上述第1焊墊上之第2焊墊、及於上述第2絕緣膜內設置於上述第2焊墊上之第2配線。上述第1焊墊包含設置於上述第1絕緣膜內之第1金屬層、及介隔上述第1金屬層設置於上述第1絕緣膜內且與上述第1配線直接相接之第2金屬層。

Description

半導體裝置及其製造方法
本發明之實施方式係關於一種半導體裝置及其製造方法。
於將複數個晶圓之金屬焊墊貼合製造半導體裝置之情形時，期望形成適合於貼合之金屬焊墊。
實施方式提供一種能夠形成適合於貼合之焊墊之半導體裝置及其製造方法。
根據一實施方式，半導體裝置具備基板、設置於上述基板之上方之第1絕緣膜、設置於上述第1絕緣膜內之第1配線、於上述第1絕緣膜內設置於上述第1配線上之第1焊墊、設置於上述第1絕緣膜之上之第2絕緣膜、於上述第2絕緣膜內設置於上述第1焊墊上之第2焊墊、及於上述第2絕緣膜內設置於上述第2焊墊上之第2配線。上述第1焊墊包含設置於上述第1絕緣膜內之第1金屬層、及介隔上述第1金屬層設置於上述第1絕緣膜內且與上述第1配線直接相接之第2金屬層。
以下，參照圖式對本發明之實施方式進行說明。於圖1至圖23中，對相同構成標註相同符號，並省略重複之說明。  (第1實施方式)
圖1係表示第1實施方式之半導體裝置之構造之剖視圖。圖1之半導體裝置係陣列晶片1與電路晶片2貼合而成之三維記憶體。
陣列晶片1具備包含複數個記憶胞之記憶胞陣列11、記憶胞陣列11上之絕緣膜12、及記憶胞陣列11下之層間絕緣膜13。絕緣膜12例如係氧化矽膜或氮化矽膜。層間絕緣膜13例如係氧化矽膜、或包含氧化矽膜與其他絕緣膜之積層膜。層間絕緣膜13係第2絕緣膜之例。
電路晶片2設置於陣列晶片1下。符號S表示陣列晶片1與電路晶片2之貼合面。電路晶片2具備層間絕緣膜14、及層間絕緣膜14下之基板15。層間絕緣膜14例如係氧化矽膜、或包含氧化矽膜與其他絕緣膜之積層膜。層間絕緣膜14係第1絕緣膜之例。基板15例如係矽基板等半導體基板。
圖1表示與基板15之表面平行且相互垂直之X方向及Y方向、及與基板15之表面垂直之Z方向。於本說明書中，將+Z方向作為上方向處理，將-Z方向作為下方向處理。-Z方向既可與重力方向一致亦可不一致。
陣列晶片1具備複數條字元線WL與源極線SL作為記憶胞陣列11內之電極層。圖1表示記憶胞陣列11之階梯構造部21。各字元線WL經由接觸插塞22而與字元配線層23電性地連接。貫通複數條字元線WL之各柱狀部CL經由通孔插塞24而與位元線BL電性地連接，且與源極線SL電性地連接。源極線SL包含作為半導體層之第1層SL1、及作為金屬層之第2層SL2。
電路晶片2具備複數個電晶體31。各電晶體31具備介隔閘極絕緣膜設置於基板15上之閘極電極GE、及設置於基板15內之未圖示之源極擴散層及汲極擴散層。又，電路晶片2具備：複數個接觸插塞32，其等設置於該等電晶體31之閘極電極GE、源極擴散層、或汲極擴散層上；配線層，其設置於該等接觸插塞32上且包含複數條配線33；及複數個通孔插塞34，其等設置於該配線層上。
電路晶片2進而具備設置於該等通孔插塞34上且包含複數條配線35之配線層、設置於該配線層上之複數個通孔插塞36、設置於該等通孔插塞36上且包含複數條配線37之配線層、及設置於該配線層上之複數個金屬焊墊38。金屬焊墊38例如包含Cu(銅)層或Al(鋁)層。配線37係第1配線之例，金屬焊墊38係第1焊墊之例。電路晶片2作為控制陣列晶片1之動作之控制電路(邏輯電路)發揮功能。該控制電路由電晶體31等構成，電性地連接於金屬焊墊38。
陣列晶片1具備設置於金屬焊墊38上之複數個金屬焊墊41、設置於金屬焊墊41上且包含複數條配線42之配線層、及設置於該配線層上之複數個通孔插塞43。金屬焊墊41例如包含Cu層或Al層。金屬焊墊41係第2焊墊之例，配線42係第2配線之例。
陣列晶片1進而具備設置於該等通孔插塞43上且包含複數條配線44之配線層、設置於該配線層上之複數個通孔插塞45、設置於該等通孔插塞45上、絕緣膜12上之金屬焊墊46、及設置於金屬焊墊46上、絕緣膜12上之鈍化膜47。金屬焊墊46例如包含Cu層或Al層，作為圖1之半導體裝置之外部連接焊墊(接合焊墊)發揮功能。鈍化膜47例如係氧化矽膜等絕緣膜，具有使金屬焊墊46之上表面露出之開口部P。金屬焊墊46能夠經由該開口部P且藉由接合線、焊球、金屬凸塊等而連接於安裝基板或其他裝置。
圖2係表示第1實施方式之柱狀部CL之構造之剖視圖。
如圖2所示，記憶胞陣列11具備交替地積層於層間絕緣膜13(圖1)上之複數條字元線WL與複數個絕緣層51。字元線WL例如係W(鎢)層。絕緣層51例如係氧化矽膜。
柱狀部CL依次包含區塊絕緣膜52、電荷儲存層53、隧道絕緣膜54、通道半導體層55、及芯絕緣膜56。電荷儲存層53例如係氮化矽膜，介隔區塊絕緣膜52形成於字元線WL及絕緣層51之側面。電荷儲存層53亦可為多晶矽層等半導體層。通道半導體層55例如係多晶矽層，介隔隧道絕緣膜54形成於電荷儲存層53之側面。區塊絕緣膜52、隧道絕緣膜54、及芯絕緣膜56例如係氧化矽膜或金屬絕緣膜。
圖3係表示第1實施方式之半導體裝置之製造方法之剖視圖。圖3表示包含複數個陣列晶片1之陣列晶圓W1與包含複數個電路晶片2之電路晶圓W2。陣列晶圓W1亦被稱為記憶體晶圓，電路晶圓W2亦被稱為CMOS(complementary metal oxide semiconductor，互補金氧半導體)晶圓。
應注意圖3之陣列晶圓W1之方向與圖1之陣列晶片1之方向相反。於本實施方式中，藉由將陣列晶圓W1與電路晶圓W2貼合而製造半導體裝置。圖3表示為了貼合而使方向反轉之前之陣列晶圓W1，圖1表示為了貼合而使方向反轉來貼合及切割之後之陣列晶片1。
於圖3中，符號S1表示陣列晶圓W1之上表面，符號S2表示電路晶圓W2之上表面。應注意陣列晶圓W1具備設置於絕緣膜12下之基板16。基板16例如係矽基板等半導體基板。基板15係第1基板之例，基板16係第2基板之例。
於本實施方式中，首先，如圖3所示，於陣列晶圓W1之基板16上形成記憶胞陣列11、絕緣膜12、層間絕緣膜13、階梯構造部21、金屬焊墊41等，於電路晶圓W2之基板15上形成層間絕緣膜14、電晶體31、金屬焊墊38等。例如，於基板16上依次形成通孔插塞45、配線44、通孔插塞43、配線42、及金屬焊墊41。又，於基板15上依次形成接觸插塞32、配線33、通孔插塞34、配線35、通孔插塞36、配線37、及金屬焊墊38。其次，將陣列晶圓W1與電路晶圓W2藉由機械性壓力而貼合。藉此，將層間絕緣膜13與層間絕緣膜14接著。其次，將陣列晶圓W1及電路晶圓W2以400℃退火。藉此，將金屬焊墊41與金屬焊墊38接合。
然後，將基板15藉由CMP(Chemical Mechanical Polishing，化學機械拋光)而薄膜化，對基板16藉由CMP進行去除之後，將陣列晶圓W1及電路晶圓W2切斷為複數個晶片。如此一來，製造圖1之半導體裝置。再者，金屬焊墊46與鈍化膜47例如於基板15之薄膜化及基板16之去除之後形成於絕緣膜12上。
再者，於本實施方式中，將陣列晶圓W1與電路晶圓W2貼合，但亦可取而代之將陣列晶圓W1彼此貼合。參照圖1至圖3所述之內容、參照圖4至圖23所述之內容亦能夠應用於陣列晶圓W1彼此之貼合。
又，圖1表示層間絕緣膜13與層間絕緣膜14之交界面、金屬焊墊41與金屬焊墊38之交界面，但一般於上述退火後觀察不到該等交界面。然而，存在該等交界面之位置例如可藉由檢測金屬焊墊41之側面、金屬焊墊38之側面之斜率、金屬焊墊41之側面與金屬焊墊38之位置偏移來推定。
圖4係表示第1實施方式之半導體裝置之構造之其他剖視圖。
圖4(a)表示圖1所示之層間絕緣膜14、複數條配線37中之1條、及複數個金屬焊墊38中之1個。以下，對圖4(a)所示之層間絕緣膜14、配線37、及金屬焊墊38之詳細情況進行說明。再者，以下之說明亦應用於圖1所示之其他配線37、其他金屬焊墊38。
層間絕緣膜14交替地包含複數個絕緣膜14a與複數個絕緣膜14b。絕緣膜14a例如係SiO2 膜(氧化矽膜)。絕緣膜14b係與絕緣膜14a不同之絕緣膜，例如係SiCN膜(碳氮化矽膜)。於本實施方式中，可利用絕緣膜14a與絕緣膜14b之蝕刻速率之差異，藉由蝕刻而形成配線37用之配線槽、金屬焊墊38用之開口部。
配線37包含形成於層間絕緣膜14之側面及上表面之阻障金屬層37a、及介隔阻障金屬層37a形成於層間絕緣膜14之側面及上表面之配線材層37b。阻障金屬層37a例如係Ti(鈦)膜、TiN膜(氮化鈦膜)、Ta(鉭)膜、或TaN膜(氮化鉭膜)。配線材層37b例如係Cu層。阻障金屬層37a係第5層之例，配線材層37b係第6層之例。配線37之厚度例如為500 nm。本實施方式之配線37亦可於XY平面內直線狀或曲線狀地延伸。
金屬焊墊38包含形成於層間絕緣膜14之側面之阻障金屬層38a、及介隔阻障金屬層38a形成於層間絕緣膜14之側面且直接形成於配線37(配線材層37b)之上表面之焊墊材層38b。於本實施方式中，由於阻障金屬層38a未覆蓋配線37之上表面，故而焊墊材層38b與配線37之上表面相接。阻障金屬層38a例如係Ti膜、TiN膜、Ta膜、或TaN膜。焊墊材層38b例如係Cu層。阻障金屬層38a係第1層之例，焊墊材層38b係第2層之例。金屬焊墊38之厚度例如為500 nm，金屬焊墊38之平面形狀例如為正方形或長方形。
再者，配線材層37b與焊墊材層38b亦可為包含Cu元素以外之相同之金屬元素之金屬層。配線材層37b與焊墊材層38b例如亦可均為Al層，亦可均為W層。
圖4(b)除了圖4(a)之層間絕緣膜14、配線37、及金屬焊墊38以外，還表示圖1所示之層間絕緣膜13、複數個金屬焊墊41中之1個、及複數條配線42中之1條。以下，對圖4(b)所示之層間絕緣膜13、金屬焊墊41、及配線42之詳細情況進行說明。再者，以下之說明亦應用於圖1所示之其他金屬焊墊41、其他配線42。
層間絕緣膜13交替地包含複數個絕緣膜13a與複數個絕緣膜13b。絕緣膜13a例如係SiO2 膜。絕緣膜13b係與絕緣膜13a不同之絕緣膜，例如係SiCN膜。於本實施方式中，可利用絕緣膜13a與絕緣膜13b之蝕刻速率之差異，藉由蝕刻而形成金屬焊墊41用之開口部、配線42用之配線槽。
配線42包含形成於層間絕緣膜13之側面及下表面之阻障金屬層42a、及介隔阻障金屬層42a形成於層間絕緣膜13之側面及下表面之配線材層42b。阻障金屬層42a例如係Ti膜、TiN膜、Ta膜、或TaN膜。配線材層42b例如係Cu層。阻障金屬層42a係第7層之例，配線材層42b係第8層之例。配線42之厚度例如為500 nm。本實施方式之配線42亦可於XY平面內直線狀或曲線狀地延伸。
金屬焊墊41包含形成於層間絕緣膜13之側面之阻障金屬層41a、及介隔阻障金屬層41a形成於層間絕緣膜13之側面且直接形成於配線42(配線材層42b)之下表面之焊墊材層41b。於本實施方式中，由於阻障金屬層41a未覆蓋配線42之下表面，故而焊墊材層41b與配線42之下表面相接。阻障金屬層41a例如係Ti膜、TiN膜、Ta膜、或TaN膜。焊墊材層41b例如係Cu層。阻障金屬層41a係第3層之例，焊墊材層41b係第4層之例。金屬焊墊41之厚度例如為500 nm，金屬焊墊41之平面形狀例如為正方形或長方形。金屬焊墊41形成於金屬焊墊38上，焊墊材層41b形成於焊墊材層38b上。
再者，配線材層42b與焊墊材層41b亦可為包含Cu元素以外之相同之金屬元素之金屬層。配線材層42b與焊墊材層41b例如亦可均為Al層，亦可均為W層。
以下，參照圖4(b)，對本實施方式之金屬焊墊38、41之更詳細情況進行說明。
金屬焊墊38例如藉由於層間絕緣膜14形成開口部，且於開口部內填埋金屬焊墊38之材料，並將該材料之表面藉由CMP平坦化而形成。於該情形時，有於金屬焊墊38之上表面形成被稱為凹陷之凹部，而金屬焊墊38不易與金屬焊墊41接合之情況。因此，較理想的是使金屬焊墊38之厚度變厚，使金屬焊墊38之焊墊材層38b之熱膨脹量變大。藉此，能夠將金屬焊墊38之上表面之凹陷藉由焊墊材層38b之熱膨脹而減少，使金屬焊墊38與金屬焊墊41正常地接合。
然而，為了使金屬焊墊38之厚度變厚必須於層間絕緣膜14形成較深之開口部，用以形成開口部之RIE(Reactive Ion Etcing，反應性離子蝕刻)變得困難。進而，必須使金屬焊墊38之材料變厚或使CMP研磨量變多，金屬焊墊38之形成變得困難。其結果，有產生電路晶片2之晶片厚度增大、半導體裝置之製造成本增大、金屬焊墊38之形狀之不均等問題之虞。
因此，於本實施方式中，藉由不於配線37之上表面形成金屬焊墊38之阻障金屬層38a，而將金屬焊墊38之焊墊材層38b直接形成於配線37之配線材層37b之上表面。因此，根據本實施方式，能夠藉由金屬焊墊38之焊墊材層38b之熱膨脹與配線37之配線材層37b之熱膨脹，減少金屬焊墊38之上表面之凹陷。換言之，根據本實施方式，關於熱膨脹，能夠使金屬焊墊38與配線37作為實效性的金屬焊墊發揮功能。相對於金屬焊墊38之厚度為500 nm，而實效性的金屬焊墊之厚度為1 μm。根據本實施方式，能夠使金屬焊墊38之焊墊材層38b與配線37之配線材層37b一體化，藉此能夠利用較薄之金屬焊墊38獲得與較厚之金屬焊墊相同之效果。具體而言，能夠利用較薄之焊墊材層38b(Cu層)，獲得與較厚之焊墊材層(Cu層)相同之熱膨脹量。
進而，根據本實施方式，能夠抑制使金屬焊墊38變厚之情形時之問題。例如，無須於層間絕緣膜14形成較深之開口部，用以形成開口部之RIE變得容易。例如，又，無須使金屬焊墊38之材料變厚、使CMP研磨量變多，金屬焊墊38之形成變得容易。進而，由於包含配線37之配線層亦可用作通常之配線層，故而亦可抑制由配置配線37所致之電路晶片2之晶片厚度增大。包含配線37之配線層例如用於電源配線用。
以上情況對於金屬焊墊41亦同樣地成立。於本實施方式中，藉由不於配線42之下表面形成金屬焊墊41之阻障金屬層41a，而將金屬焊墊41之焊墊材層41b直接形成於配線42之配線材層42b之下表面。因此，根據本實施方式，能夠藉由金屬焊墊41之焊墊材層41b之熱膨脹與配線42之配線材層42b之熱膨脹，而減少金屬焊墊41之下表面之凹陷。
如以上般，根據本實施方式，能夠形成適合於貼合之金屬焊墊38、41。
圖5係表示第1實施方式之比較例之半導體裝置之構造之剖視圖。
圖5(a)表示與圖4(a)相同之層間絕緣膜14、配線37、及金屬焊墊38與複數個通孔插塞39。以下，對該等通孔插塞39中之任意1個之詳細情況進行說明。
通孔插塞39形成於配線37與金屬焊墊38之間。通孔插塞39包含與金屬焊墊38相同之阻障金屬層38a及焊墊材層(插塞材層)38b。此種通孔插塞39及金屬焊墊38能夠藉由雙道金屬鑲嵌法而形成。本比較例之焊墊材層38b介隔阻障金屬層38a形成於配線37上。
圖5(b)表示圖5(a)之層間絕緣膜14、配線37、金屬焊墊38、及複數個通孔插塞39與圖4(b)之層間絕緣膜13、金屬焊墊41、及配線42、及複數個通孔插塞48。以下，對該等通孔插塞48中之任意1個之詳細情況進行說明。
通孔插塞48形成於金屬焊墊41與配線42之間。通孔插塞48包含與金屬焊墊41相同之阻障金屬層41a及焊墊材層(插塞材層)41b。此種通孔插塞48及金屬焊墊41能夠藉由雙道金屬鑲嵌法而形成。本比較例之焊墊材層41b介隔阻障金屬層41a形成於配線42下。
以下，參照圖5(b)對本比較例之金屬焊墊38、41之更詳細情況進行說明。
於本比較例中，於金屬焊墊38及通孔插塞39之焊墊材層38b與配線37之配線材層37b之間，形成有阻障金屬層38a。因此，金屬焊墊38之上表面之凹陷藉由焊墊材層38b之熱膨脹而減少，但不會藉由配線材層37b之熱膨脹而減少。因此，於本比較例中，必須使金屬焊墊38之厚度變厚。本比較例之金屬焊墊38、通孔插塞39、及配線37之厚度例如為1 μm、200 nm、及500 nm。以上情況對於本比較例之金屬焊墊41亦同樣地成立。
另一方面，於本實施方式中，未於金屬焊墊38之焊墊材層38b與配線37之配線材層37b之間形成阻障金屬層38a。因此，根據本實施方式，使金屬焊墊38之上表面之凹陷不僅能夠藉由焊墊材層38b之熱膨脹而減少，而且亦能夠藉由配線材層37b之熱膨脹而減少。根據本實施方式，能夠藉由較薄之金屬焊墊38等而獲得此種效果。應注意相對於比較例之金屬焊墊38、通孔插塞39、及配線37之合計厚度為1.7 μm，而本實施方式之金屬焊墊38及配線37之合計厚度為1 μm。
再者，以上之說明於本比較例之金屬焊墊38及通孔插塞39利用單金屬鑲嵌法形成之情形時、本比較例之金屬焊墊41及通孔插塞48利用單金屬鑲嵌法形成之情形時亦同樣地成立。
圖6至圖9係表示第1實施方式之半導體裝置之製造方法之剖視圖。該等圖所示之步驟係於製造圖4(a)或圖4(b)所示之半導體裝置時進行者，於圖3所示之步驟中對電路晶圓W2進行。
首先，於未圖示之基板15之上方，依次形成絕緣膜14a、絕緣膜14b、及絕緣膜14a(圖6(a))。其次，於後者之絕緣膜14a及絕緣膜14b內，藉由RIE而形成配線槽H1(圖6(b))。其次，於基板15之整個面，依次形成阻障金屬層37a與配線材層37b(圖7(a))。其結果，阻障金屬層37a形成於配線槽H1之側面及底面，配線材層37b介隔阻障金屬層37a形成於配線槽H1之側面及底面。其次，將配線材層37b及阻障金屬層37a之表面藉由CMP而平坦化(圖7(b))。其結果，將配線槽H1外之阻障金屬層37a及配線材層37b去除，將包含阻障金屬層37a與配線材層37b之配線37形成於配線槽H1內。
其次，於基板15之上方，依次形成絕緣膜14b與絕緣膜14a(圖8(a))。其次，於該等絕緣膜14a及絕緣膜14b內，藉由RIE而形成開口部H2(圖8(b))。其結果，配線37之上表面於開口部H2內露出。其次，於基板15之整個面，依次形成阻障金屬層38a與焊墊材層38b(圖9(a))。其結果，阻障金屬層38a形成於開口部H2之側面。進而，焊墊材層38b介隔阻障金屬層38a形成於開口部H2之側面，且直接形成於開口部H2之底面之配線37(配線材層37b)上。關於形成此種阻障金屬層38a及焊墊材層38b之方法之例將於下文敍述。其次，將焊墊材層38b及阻障金屬層38a之表面藉由CMP而平坦化(圖9(b))。其結果，將開口部H2外之阻障金屬層38a及焊墊材層38b去除，包含阻障金屬層38a與焊墊材層38b之金屬焊墊38形成於開口部H2內。
該等圖所示之步驟於圖3所示之步驟中對陣列晶圓W1亦同樣地進行。具體而言，該等圖所示之步驟係分別將基板15、層間絕緣膜14、配線37、金屬焊墊38置換為基板16、層間絕緣膜13、配線42、金屬焊墊41後進行。然後，於圖3所示之步驟中將陣列晶圓W1與電路晶圓W2貼合，製造本實施方式之半導體裝置。
圖10及圖11係表示第1實施方式之半導體裝置之製造方法之第1例的剖視圖。該等圖所示之步驟表示圖9(a)之步驟之一例。
首先，於基板15之整個面沈積阻障金屬層38a(圖10(a))。其結果，阻障金屬層38a形成於開口部H2內之配線37之上表面、開口部H2內之層間絕緣膜14之側面、及開口部H2外之層間絕緣膜14之上表面。此時，藉由沈積阻障金屬層38a之步驟之特性，而開口部H2內之配線37上之阻障金屬層38a較開口部H2外之層間絕緣膜14上之阻障金屬層38a變薄。
其次，將阻障金屬層38a藉由使用氬氣(Ar)之再濺射而薄膜化(圖10(b))。藉此，可將開口部H2內之配線37上之阻障金屬層38a去除。其結果，配線37之上表面於開口部H2內再次露出。再者，開口部H2外之層間絕緣膜14上之阻障金屬層38a較開口部H2內之配線37上之阻障金屬層38a厚，故而未完全去除而薄膜化。又，藉由再濺射之特性，亦於開口部H2內之層間絕緣膜14之側面殘存阻障金屬層38a。
於圖10(b)之步驟中，有亦將配線材層37b之一部分去除，而於配線材層37b之上表面形成凹部之可能性。圖10(b)表示此種凹部之例。再者，若將開口部H2之底面之阻障金屬層38a去除，則存在藉由該阻障金屬層38a之去除而產生之原子附著於開口部H2之側面之阻障金屬層38a之情形。於該情形時，開口部H2之側面之阻障金屬層38a之厚度藉由此種原子之附著而變厚。
其次，於基板15之整個面形成焊墊材層38b(圖11(a))。其結果，焊墊材層38b介隔阻障金屬層38a形成於開口部H2之側面，且直接形成於開口部H2之底面之配線37(配線材層37b)上。
其次，將焊墊材層38b及阻障金屬層38a之表面藉由CMP而平坦化(圖11(b))。其結果，將開口部H2外之阻障金屬層38a及焊墊材層38b去除，包含阻障金屬層38a與焊墊材層38b之金屬焊墊38形成於開口部H2內。
圖12及圖13係表示第1實施方式之半導體裝置之製造方法之第2例的剖視圖。該等圖所示之步驟表示圖9(a)之步驟之其他例。
首先，於基板15之整個面，藉由濺鍍而沈積金屬層38c(圖12(a))。其結果，金屬層38c形成於開口部H2內之配線37之上表面、開口部H2內之層間絕緣膜14之側面、及開口部H2外之層間絕緣膜14之上表面。金屬層38c例如係CuMn晶種層(Mn表示錳)。金屬層38c係第1膜之例。
其次，於基板15之整個面，藉由鍍覆法形成金屬層38d(圖12(b))。其結果，金屬層38d介隔金屬層38c形成於開口部H2之側面及底面。金屬層38d例如係Cu層。金屬層38d係第2膜之例。
其次，將金屬層38c、38d等退火(圖13(a))。其結果，金屬層38c之一部分藉由層間絕緣膜14中之Si原子或O原子之影響，而變質為金屬層38c1。金屬層38c1例如係MnSiX OY 層(X及Y為正整數)。另一方面，金屬層38c之另一部分變質為金屬層38c2。金屬層38c2例如係Cu層。另一方面，存在金屬層38c中之Mn原子擴散至金屬層38d之上表面之情形。圖13(a)表示藉由該擴散而產生於金屬層38d內之金屬層38d1、38d2。金屬層38d1例如係Cu層，金屬層38d2例如係CuMn層。如此一來，形成包含金屬層38c1之阻障金屬層38a、及包含金屬層38c2與金屬層38d1之焊墊材層38b。
再者，由於金屬層38c1係藉由層間絕緣膜14中之Si原子或O原子之影響而產生，故而形成於開口部H2之側面，但不形成於開口部H2之底面。其結果，金屬層38c2介隔金屬層38c1形成於開口部H2之側面，且直接形成於開口部H2之底面之配線37(配線材層37b)上。
其次，將金屬層38d2、38d1、38c2、38c1之表面藉由CMP而平坦化(圖13(b))。其結果，將開口部H2外之金屬層38d2、38d1、38c2、38c1去除，包含金屬層38c1、38c2、38d1之金屬焊墊38形成於開口部H2內。即，包含阻障金屬層38a與焊墊材層38b之金屬焊墊38形成於開口部H2內。
圖14係用以將第1實施方式之半導體裝置與其比較例之半導體裝置進行比較之俯視圖。
圖14(a)表示圖5(a)所示之比較例之半導體裝置之平面構造之例。圖14(a)表示複數條配線37、配置於該等配線37上之複數個通孔插塞39、及配置於該等通孔插塞39上之複數個金屬焊墊38。
但是，圖14(a)不僅表示配置於配線37及通孔插塞39上之金屬焊墊38，而且亦表示未配置於配線37及通孔插塞39上之金屬焊墊38。後者之金屬焊墊38係為了將半導體裝置內之構成要素彼此電性地連接而未使用之虛設焊墊。
圖14(b)表示了圖4(a)所示之第1實施方式之半導體裝置之平面構造之例。圖14(b)表示了複數條配線37、及配置於該等配線37上之複數個金屬焊墊38。
圖14(b)所示之金屬焊墊38不包含如上所述之虛設焊墊。理由在於，由於本實施方式之金屬焊墊38直接形成於配線37上，故而若配置虛設焊墊，則虛設焊墊於配置配線37時成為障礙。但是，於必須配置虛設焊墊之情形時，亦可配置當配置配線37時不成為障礙之個數、配置之虛設焊墊。
圖14(b)所示之金屬焊墊38之上表面具有與圖14(b)所示之配線37之上表面大致相同之尺寸。再者，金屬焊墊38之上表面之尺寸亦可大於配線37之上表面之尺寸，亦可小於配線37之上表面之尺寸。
圖15係用以將第1實施方式之半導體裝置與其比較例之半導體裝置進行比較之其他俯視圖。
圖15(a)表示圖5(a)所示之比較例之半導體裝置之平面構造之其他例。圖15(a)表示複數條配線37、配置於該等配線37上之複數個通孔插塞39、及配置於該等通孔插塞39上之複數個金屬焊墊38。圖15(a)所示之配線37之上表面具有圖15(a)所示之金屬焊墊38之上表面之約一半之尺寸。又，圖15(a)所示之金屬焊墊38與圖14(a)所示之金屬焊墊38相同地，包含虛設焊墊。
圖15(b)表示圖4(a)所示之第1實施方式之半導體裝置之平面構造之其他例。圖15(b)表示複數條配線37、及配置於該等配線37上之複數個金屬焊墊38。又，圖15(b)所示之金屬焊墊38與圖14(b)所示之金屬焊墊38相同地，不包含虛設焊墊。
此處，圖15(b)所示之配線37之上表面具有與圖15(a)所示之配線37之上表面相同之尺寸。即，圖15(b)所示之配線37之上表面具有圖14(b)所示之配線37之上表面之約一半之尺寸。因此，於該例中，圖15(b)所示之金屬焊墊38之上表面之尺寸亦設定為圖14(b)所示之金屬焊墊38之上表面之尺寸之約一半。如此，於本實施方式中，於減少配線37之尺寸之情形時，金屬焊墊38之尺寸亦可減少。藉此，例如，能夠減少金屬焊墊38相對於配線37之偏離。
再者，於下述第2實施方式中，於配線37與金屬焊墊38之間，與上述比較例相同地配置通孔插塞。因此，第2實施方式之金屬焊墊38與本比較例之金屬焊墊38相同地，亦可包含多個虛設焊墊。
參照圖14(a)至圖15(b)所說明之內容不僅應用於電路晶片2而且亦應用於陣列晶片1。於該情形時，該說明內之配線37、通孔插塞39、及金屬焊墊38分別置換為配線42、通孔插塞48、及金屬焊墊41。
如以上般，本實施方式之金屬焊墊38包含設置於層間絕緣膜14內之阻障金屬層38a、及介隔阻障金屬層38a設置於層間絕緣膜14內且與配線37直接相接之焊墊材層38b。同樣地，本實施方式之金屬焊墊41包含設置於層間絕緣膜13內之阻障金屬層41a、及介隔阻障金屬層41a設置於層間絕緣膜13內且與配線42直接相接之焊墊材層41b。
因此，根據本實施方式，能夠形成適合於貼合之金屬焊墊38、41。例如，能夠將金屬焊墊38、41之厚度設定得較薄，且使實效性的金屬焊墊之厚度變厚。  (第2實施方式)
圖16係表示第2實施方式之半導體裝置之構造之剖視圖。
圖16(a)具備與圖4(a)相同之層間絕緣膜14、配線37、及金屬焊墊38與複數個通孔插塞61。該等通孔插塞61係第1插塞之例。本實施方式之配線37、通孔插塞61、及金屬焊墊38之厚度例如為500 μm、200 nm、及300 nm。因此，本實施方式之配線37、通孔插塞61、及金屬焊墊38之合計厚度與第1實施方式之配線37及金屬焊墊38之合計厚度相同地為1 μm。以下，對該等通孔插塞61中之任意1個之詳細情況進行說明。
通孔插塞61形成於配線37與金屬焊墊38之間。通孔插塞61包含與金屬焊墊38相同之阻障金屬層38a及焊墊材層(插塞材層)38b。此種通孔插塞61及金屬焊墊38能夠藉由雙道金屬鑲嵌法而形成。
但是，相對於上述比較例之焊墊材層38b介隔阻障金屬層38a形成於配線37上，本實施方式之焊墊材層38b直接形成於配線37上。本實施方式之此種阻障金屬層38a及焊墊材層38b例如如下所述，能夠藉由進行與圖10(a)至圖11(b)所示之步驟、圖12(a)至圖13(b)所示之步驟相同之處理而形成。再者，應注意本實施方式之阻障金屬層38a不覆蓋通孔插塞61下之配線37之上表面，但覆蓋金屬焊墊38下之層間絕緣膜14之上表面。
圖16(b)除了圖16(a)所示之構成要素以外，還表示與圖4(b)相同之層間絕緣膜13、金屬焊墊41、及配線42與複數個通孔插塞62。該等通孔插塞62係第2插塞之例。本實施方式之金屬焊墊41、通孔插塞62、及配線42之厚度例如為300 μm、200 nm、及500 nm。因此，本實施方式之金屬焊墊41、通孔插塞62、及配線42之合計厚度與第1實施方式之金屬焊墊41及配線42之合計厚度相同地為1 μm。以下，對該等通孔插塞62中之任意1個之詳細情況進行說明。
通孔插塞62形成於金屬焊墊41與配線42之間。通孔插塞62包含與金屬焊墊41相同之阻障金屬層41a及焊墊材層(插塞材層)42b。此種通孔插塞62及金屬焊墊41能夠藉由雙道金屬鑲嵌法而形成。
但是，相對於上述比較例之焊墊材層41b介隔阻障金屬層41a形成於配線42下，本實施方式之焊墊材層41b直接形成於配線42下。本實施方式之此種阻障金屬層41a及焊墊材層41b例如如下所述，能夠藉由進行與圖10(a)至圖11(b)所示之步驟、圖12(a)至圖13(b)所示之步驟相同之處理而形成。再者，應注意本實施方式之阻障金屬層41a不覆蓋通孔插塞42上之配線37之下表面，但覆蓋金屬焊墊41上之層間絕緣膜13之下表面。
以下，參照圖16(b)，對本實施方式之金屬焊墊38、41之更詳細情況進行說明。
於本實施方式中，藉由不將金屬焊墊38及通孔插塞61之阻障金屬層38a形成於配線37之上表面，而將金屬焊墊38及通孔插塞61之焊墊材層(插塞材層)38b直接形成於配線37之配線材層37b之上表面。因此，根據本實施方式，與第1實施方式相同，能夠藉由焊墊材層38b之熱膨脹與配線材層37b之熱膨脹，而減少金屬焊墊38之上表面之凹陷。換言之，根據本實施方式，關於熱膨脹，能夠使金屬焊墊38、通孔插塞61、及配線37作為實效性的金屬焊墊發揮功能。相對於金屬焊墊38之厚度為300 nm，實效性的金屬焊墊之厚度為1 μm。根據本實施方式，能夠使焊墊材層38b與配線材層37b一體化，藉此能夠利用較薄之金屬焊墊38獲得與較厚之金屬焊墊相同之效果。具體而言，能夠利用較薄之焊墊材層38b(Cu層)獲得與較厚之焊墊材層(Cu層)相同之熱膨脹量。
以上對於金屬焊墊41亦同樣地成立。於本實施方式中，藉由不將金屬焊墊41及通孔插塞62之阻障金屬層41a形成於配線42之下表面，而將金屬焊墊41及通孔插塞62之焊墊材層(插塞材層)41b直接形成於配線42之配線材層42b之下表面。因此，根據本實施方式，能夠藉由焊墊材層41b之熱膨脹與配線材層42b之熱膨脹，而減少金屬焊墊41之下表面之凹陷。
如以上般，根據本實施方式，能夠形成適合於貼合之金屬焊墊38、41。
再者，本實施方式之金屬焊墊38之上表面之凹陷於通孔插塞61之正上方之位置大幅度減少，但於通孔插塞61之正上方以外之位置未大幅度減少。理由在於，通孔插塞61之膨脹作用主要波及通孔插塞61之正上方之位置。因此，關於減少凹陷之作用，一般而言第1實施方式大於第2實施方式。另一方面，根據第2實施方式，如上所述，例如能夠配置多個虛設焊墊。以上對於金屬焊墊41亦同樣地成立。
圖17係表示第2實施方式之變化例之半導體裝置之構造之剖視圖。
於圖17(a)中，將圖16(a)之複數個較小之通孔插塞61置換為較大之通孔插塞63。同樣地，於圖17(b)中，將圖16(b)之複數個較小之通孔插塞62置換為較大之通孔插塞64。通孔插塞63、64之性質除了平面形狀之尺寸以外，與通孔插塞61、62之性質相同。通孔插塞63係第1插塞之例，通孔插塞64係第2插塞之例。
根據本變化例，與第2實施方式相同，能夠形成適合於貼合之金屬焊墊38、41。又，根據本變化例，與第2實施方式相比，能夠將減少凹陷之作用波及至通孔插塞63之正上方之較廣區域。理由在於，通孔插塞63之尺寸較大。換言之，根據本變化例，能夠享受第2實施方式之優點，且亦能夠享受第1實施方式之優點。以上對於金屬焊墊41亦同樣地成立。
圖18及圖19係表示第2實施方式之半導體裝置之製造方法之剖視圖。該等圖所示之步驟係於製造圖16(a)或圖16(b)所示之半導體裝置時進行者，於圖3所示之步驟中對電路晶圓W2進行。
首先，實施圖6(a)至圖7(b)之步驟。其結果，於未圖示之基板15之上方，形成包含阻障金屬層37a與配線材層37b之配線37(圖18(a))。其次，於基板15之上方，依次形成絕緣膜14b、絕緣膜14a、絕緣膜14b、及絕緣膜14a(圖18(a))。其次，於後者之絕緣膜14a及後者之絕緣膜14b內，藉由RIE形成開口部H3(圖18(a))。其次，於前者之絕緣膜14a及前者之絕緣膜14b內，藉由RIE形成複數個導孔H4(圖18(b))。其結果，配線37之上表面於開口部H3下之該等導孔H4內露出。
其次，於基板15之整個面，依次形成阻障金屬層38a與焊墊材層38b(圖19(a))。其結果，阻障金屬層38a形成於開口部H3之側面及底面、導孔H4之側面。進而，焊墊材層38b介隔阻障金屬層38a形成於開口部H3之側面及底面、導孔H4之側面，且直接形成於導孔H4之底面之配線37(配線材層37b)上。關於形成此種阻障金屬層38a及焊墊材層38b之方法之例將於下文敍述。其次，將焊墊材層38b及阻障金屬層38a之表面藉由CMP而平坦化(圖19(b))。其結果，將除開口部H3及導孔H4以外之阻障金屬層38a及焊墊材層38b去除，包含阻障金屬層38a與焊墊材層38b之金屬焊墊38形成於開口部H3內，包含阻障金屬層38a與焊墊材層38b之通孔插塞61形成於導孔H4內。
該等圖所示之步驟於圖3所示之步驟中對陣列晶圓W1亦同樣地進行。具體而言，該等圖所示之步驟係將基板15、層間絕緣膜14、配線37、通孔插塞61、金屬焊墊38分別置換為基板16、層間絕緣膜13、配線42、通孔插塞62、金屬焊墊41而進行。然後，於圖3所示之步驟中將陣列晶圓W1與電路晶圓W2貼合，而製造本實施方式之半導體裝置。
再者，以上之方法亦能夠應用於製造圖17(a)或圖17(b)所示之半導體裝置時。於該情形時，將與通孔插塞61、62相關之步驟置換為與通孔插塞63、64相關之步驟。例如，將複數個較小之導孔H4置換為較大之1個導孔。
圖20及圖21係表示第2實施方式之半導體裝置之製造方法之第1例之剖視圖。該等圖所示之步驟表示圖19(a)之步驟之一例。
首先，於基板15之整個面沈積阻障金屬層38a(圖20(a))。其結果，阻障金屬層38a形成於導孔H4內之配線37之上表面、導孔H4及開口部H3內之層間絕緣膜14之側面及上表面、以及除導孔H4及開口部H3以外之層間絕緣膜14之上表面。此時，藉由沈積阻障金屬層38a之步驟之特性，而導孔H4內之配線37上之阻障金屬層38a較開口部H3內之層間絕緣膜14之上表面之阻障金屬層38a變薄，開口部H3內之層間絕緣膜14之上表面之阻障金屬層38a較除導孔H4及開口部H3以外之層間絕緣膜14上之阻障金屬層38a變薄。
其次，將阻障金屬層38a藉由使用氬氣之再濺射而薄膜化(圖20(b))。藉此，可將導孔H4內之配線37上之阻障金屬層38a去除。其結果，配線37之上表面於導孔H4內再次露出。再者，由於開口部H3內之層間絕緣膜14之上表面之阻障金屬層38a、除導孔H4及開口部H3以外之層間絕緣膜14上之阻障金屬層38a，較導孔H4內之配線37上之阻障金屬層38a厚，故而未完全去除而薄膜化。又，藉由再濺射之特性，而於導孔H4及開口部H3內之層間絕緣膜14之側面亦殘存阻障金屬層38a。
於圖20(b)之步驟中，存在將配線材層37b之一部分亦去除，而於配線材層37b之上表面形成凹部之可能性。圖20(b)表示了此種凹部之例。再者，存在若將導孔H4之底面之阻障金屬層38a去除，則藉由該阻障金屬層38a之去除而產生之原子附著於導孔H4之側面之阻障金屬層38a之情形。於該情形時，導孔H4之側面之阻障金屬層38a之厚度藉由此種原子之附著而變厚。該情況對於開口部H3內之阻障金屬層38a亦相同。
其次，於基板15之整個面形成焊墊材層38b(圖21(a))。其結果，焊墊材層38b介隔阻障金屬層38a形成於開口部H3之側面及底面、導孔H4之側面，且直接形成於導孔H4之底面之配線37(配線材層37b)上。
其次，將焊墊材層38b及阻障金屬層38a之表面藉由CMP而平坦化(圖21(b))。其結果，將導孔H4及開口部H3外之阻障金屬層38a及焊墊材層38b去除，包含阻障金屬層38a與焊墊材層38b之金屬焊墊38形成於開口部H3內，包含阻障金屬層38a與焊墊材層38b之通孔插塞61形成於導孔H4內。
圖22及圖23係表示第2實施方式之半導體裝置之製造方法之第2例之剖視圖。該等圖所示之步驟表示圖19(a)之步驟之其他例。
首先，於基板15之整個面，藉由濺鍍沈積金屬層38c(圖22(a))。其結果，金屬層38c形成於導孔H4內之配線37之上表面、導孔H4及開口部H3內之層間絕緣膜14之側面及上表面、以及除導孔H4及開口部H3外之層間絕緣膜14之上表面。金屬層38c例如係CuMn晶種層。金屬層38c係第1膜之例。
其次，於基板15之整個面，藉由鍍覆法而形成金屬層38d(圖22(b))。其結果，金屬層38d介隔金屬層38c形成於導孔H4及開口部H3之側面及底面。金屬層38d例如係Cu層。金屬層38d係第2膜之例。
其次，將金屬層38c、38d等退火(圖23(a))。其結果，金屬層38c之一部分藉由層間絕緣膜14中之Si原子或O原子之影響，而變質為金屬層38c1。金屬層38c1例如係MnSiX OY 層。另一方面，金屬層38c之另一部分變質為金屬層38c2。金屬層38c2例如係Cu層。另一方面，存在金屬層38c中之Mn原子擴散至金屬層38d之上表面之情形。圖13(a)表示藉由該擴散而產生於金屬層38d內之金屬層38d1、38d2。金屬層38d1例如係Cu層，金屬層38d2例如係CuMn層。如此一來，形成包含金屬層38c1之阻障金屬層38a與包含金屬層38c2與金屬層38d1之焊墊材層38b。
再者，由於金屬層38c1藉由層間絕緣膜14中之Si原子或O原子之影響而產生，故而形成於開口部H3之側面及底面、導孔H4之側面，但不形成於導孔H4之底面。其結果，金屬層38c2介隔金屬層38c1形成於開口部H3之側面及底面、導孔H4之側面，且直接形成於導孔H4之底面之配線37(配線材層37b)上。
其次，將金屬層38d2、38d1、38c2、38c1之表面藉由CMP而平坦化(圖23(b))。其結果，將除導孔H4及開口部H3以外之金屬層38d2、38d1、38c2、38c1去除，包含金屬層38c1、38c2、38d1之金屬焊墊38形成於開口部H3內，包含金屬層38c1、38c2、38d1之通孔插塞38形成於導孔H4內。即，包含阻障金屬層38a與焊墊材層38b之金屬焊墊38形成於開口部H3內，包含阻障金屬層38a與焊墊材層38b之通孔插塞61形成於導孔H4內。
如以上般，本實施方式之金屬焊墊38及通孔插塞61(或63)包含設置於層間絕緣膜14內之阻障金屬層38a、及介隔阻障金屬層38a設置於層間絕緣膜14內且與配線37直接相接之焊墊材層38b。同樣地，本實施方式之金屬焊墊41及通孔插塞62(或64)包含設置於層間絕緣膜13內之阻障金屬層41a、及介隔阻障金屬層41a設置於層間絕緣膜13內且與配線42直接相接之焊墊材層41b。
因此，根據本實施方式，與第1實施方式相同地，能夠形成適合於貼合之金屬焊墊38、41。例如，能夠將金屬焊墊38、41之厚度設定得較薄，且使實效性的金屬焊墊之厚度變厚。
以上，對幾個實施方式進行了說明，但該等實施方式係僅作為例而提出者，並不意圖限定發明之範圍。本說明書中所說明之新穎之裝置及方法能夠以其他各種形態實施。又，可對本說明書中所說明之裝置及方法之形態，於不脫離發明主旨之範圍內，進行各種省略、置換、變更。隨附之申請專利範圍及其均等之範圍意圖包含發明之範圍、主旨中所包含之此種形態、變化例。  [相關申請案]
本申請案享有以日本專利申請案2020-29644號(申請日：2020年2月25日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。
1:陣列晶片 2:電路晶片 11:記憶胞陣列 12:絕緣膜 13:層間絕緣膜 13a:絕緣膜 13b:絕緣膜 14:層間絕緣膜 14a:絕緣膜 14b:絕緣膜 15:基板 16:基板 21:階梯構造部 22:接觸插塞 23:字元配線層 24:通孔插塞 31:電晶體 32:接觸插塞 33:配線 34:通孔插塞 35:配線 36:通孔插塞 37:配線 37a:阻障金屬層 37b:配線材層 38:金屬焊墊 38a:阻障金屬層 38b:焊墊材層(插塞材層) 38c:金屬層 38c1:金屬層 38c2:金屬層 38d1:金屬層 38d2:金屬層 39:通孔插塞 41:金屬焊墊 41a:阻障金屬層 41b:焊墊材層(插塞材層) 42:配線 42a:阻障金屬層 42b:配線材層 43:通孔插塞 44:配線 45:通孔插塞 46:金屬焊墊 47:鈍化膜 48:通孔插塞 51:絕緣層 52:區塊絕緣膜 53:電荷儲存層 54:隧道絕緣膜 55:通道半導體層 56:芯絕緣膜 61:通孔插塞 62:通孔插塞 63:通孔插塞 64:通孔插塞 BL:位元線 CL:柱狀部 GE:閘極電極 H2:開口部 H3:開口部 H4:導孔 P:開口部 S:陣列晶片1與電路晶片2之貼合面 S1:陣列晶圓W1之上表面 S2:電路晶圓W2之上表面 SL:源極線 SL1:第1層 SL2:第2層 W1:陣列晶圓 W2:電路晶圓 WL:字元線
圖1係表示第1實施方式之半導體裝置之構造之剖視圖。  圖2係表示第1實施方式之柱狀部之構造之剖視圖。  圖3係表示第1實施方式之半導體裝置之製造方法之剖視圖。  圖4(a)、(b)係表示第1實施方式之半導體裝置之構造之其他剖視圖。  圖5(a)、(b)係表示第1實施方式之比較例之半導體裝置之構造的剖視圖。  圖6(a)～圖9(b)係表示第1實施方式之半導體裝置之製造方法之剖視圖。  圖10(a)～圖11(b)係表示第1實施方式之半導體裝置之製造方法之第1例的剖視圖。  圖12(a)～圖13(b)係表示第1實施方式之半導體裝置之製造方法之第2例的剖視圖。  圖14(a)、(b)係用以將第1實施方式之半導體裝置與其比較例之半導體裝置進行比較之俯視圖。  圖15(a)、(b)係表示用以將第1實施方式之半導體裝置與其比較例之半導體裝置進行比較之其他俯視圖。  圖16(a)、(b)係表示第2實施方式之半導體裝置之構造之剖視圖。  圖17(a)、(b)係表示第2實施方式之變化例之半導體裝置之構造的剖視圖。  圖18(a)～圖19(b)係表示第2實施方式之半導體裝置之製造方法之剖視圖。  圖20(a)～圖21(b)係表示第2實施方式之半導體裝置之製造方法之第1例的剖視圖。  圖22(a)～圖23(b)係表示第2實施方式之半導體裝置之製造方法之第2例的剖視圖。
1:陣列晶片
2:電路晶片
13:層間絕緣膜
13a:絕緣膜
13b:絕緣膜
14:層間絕緣膜
14a:絕緣膜
14b:絕緣膜
37:配線
37a:阻障金屬層
37b:配線材層
38:金屬焊墊
38a:阻障金屬層
38b:焊墊材層(插塞材層)
41:金屬焊墊
41a:阻障金屬層
41b:焊墊材層(插塞材層)
42:配線
42a:阻障金屬層
42b:配線材層

Claims (20)

  1. 一種半導體裝置，其包含：  基板；  第1絕緣膜，其設置於上述基板之上方；  第1配線，其設置於上述第1絕緣膜內；  第1焊墊，其係於上述第1絕緣膜內，設置於上述第1配線上；  第2絕緣膜，其設置於上述第1絕緣膜之上；  第2焊墊，其係於上述第2絕緣膜內，設置於上述第1焊墊上；及  第2配線，其係於上述第2絕緣膜內，設置於上述第2焊墊上；  上述第1焊墊包含：第1金屬層及第2金屬層，該第1金屬層係設置於上述第1絕緣膜內，該第2金屬層係介隔上述第1金屬層設置於上述第1絕緣膜內且與上述第1配線直接相接。
  2. 如請求項1之半導體裝置，其中  上述第2焊墊包含：第3金屬層及第4金屬層，該第3金屬層係設置於上述第2絕緣膜內，該第4金屬層係介隔上述第3金屬層設置於上述第2絕緣膜內且與上述第2配線直接相接。
  3. 如請求項1之半導體裝置，其進而包含  設置於上述第1絕緣膜內之上述第1配線與上述第1焊墊之間之第1插塞，  上述第1插塞包含上述第1金屬層、及與上述第1配線直接相接之上述第2金屬層。
  4. 如請求項2之半導體裝置，其進而包含  設置於上述第2絕緣膜內之上述第2焊墊與上述第2配線之間之第2插塞，  上述第2插塞包含上述第3金屬層、及與上述第2配線直接相接之上述第4金屬層。
  5. 如請求項1之半導體裝置，其中  上述第1配線包含：第5金屬層及第6金屬層，該第5金屬層係設置於上述第1絕緣膜內，該第6金屬層係介隔上述第5金屬層設置於上述第1絕緣膜內且與上述第2金屬層直接相接。
  6. 如請求項5之半導體裝置，其中  上述第2金屬層與上述第6金屬層包含相同之金屬元素。
  7. 如請求項1之半導體裝置，其中  上述第2配線包含：第7金屬層及第8金屬層，該第7金屬層係設置於上述第2絕緣膜內，該第8金屬層係介隔上述第7金屬層設置於上述第2絕緣膜內且與上述第4金屬層直接相接。
  8. 如請求項7之半導體裝置，其中  上述第4金屬層與上述第8金屬層包含相同之金屬元素。
  9. 如請求項1之半導體裝置，其中  上述第2金屬層包含Cu。
  10. 如請求項9之半導體裝置，其中  上述第2金屬層進而包含Ti、Mn、Zn、Al、Sn、V、W中之至少一種元素。
  11. 一種半導體裝置之製造方法，其包含：  於第1基板之上方形成第1絕緣膜；  於上述第1絕緣膜內形成第1配線；  於上述第1絕緣膜內，在上述第1配線上形成第1焊墊；  於第2基板之上方形成第2絕緣膜；  於上述第2絕緣膜內形成第2配線；  於上述第2絕緣膜內，在上述第2配線上形成第2焊墊；及  藉由將上述第1焊墊與上述第2焊墊貼合，而於上述第1焊墊上配置上述第2焊墊；  上述第1焊墊包含：第1金屬層及第2金屬層，該第1金屬層係設置於上述第1絕緣膜內，該第2金屬層係介隔上述第1金屬層設置於上述第1絕緣膜內且與上述第1配線直接相接，  於上述第1焊墊之形成中：  於上述第1絕緣膜之側面及上述第1配線之上表面形成第1金屬層，  使上述第1金屬層殘存於上述第1絕緣膜之側面，且自上述第1配線之上表面去除上述第1金屬層而使上述第1配線露出，  於上述第1金屬層之側面及上述第1配線之露出面形成第2金屬層。
  12. 如請求項11之半導體裝置之製造方法，其中  上述第2焊墊包含：第3金屬層及第4金屬層，該第3金屬層係設置於上述第2絕緣膜內，該第4金屬層係介隔上述第3金屬層設置於上述第2絕緣膜內且與上述第2配線直接相接，  於上述第2焊墊之形成中，於上述第2絕緣膜之側面與上述第2配線之上表面形成上述第3金屬層，並使上述第3金屬層殘存於上述第2絕緣膜之側面，且自上述第2配線之上表面去除上述第3金屬層，於上述第3金屬層之側面與上述第2配線之上表面形成上述第4金屬層。
  13. 如請求項11之半導體裝置之製造方法，其進而包含  設置於上述第1絕緣膜內之上述第1配線與上述第1焊墊之間之第1插塞，  上述第1插塞包含上述第1金屬層、及與上述第1配線直接相接之上述第2金屬層。
  14. 如請求項12之半導體裝置之製造方法，其進而包含  設置於上述第2絕緣膜內之上述第2焊墊與上述第2配線之間之第2插塞，  上述第2插塞包含上述第3金屬層、及與上述第2配線直接相接之上述第4金屬層。
  15. 如請求項11之半導體裝置之製造方法，其中  上述第1配線包含：第5金屬層及第6金屬層，該第5金屬層係設置於上述第1絕緣膜內，該第6金屬層係介隔上述第5金屬層設置於上述第1絕緣膜內且與上述第2金屬層直接相接。
  16. 如請求項15之半導體裝置之製造方法，其中  上述第2金屬層與上述第6金屬層包含相同之金屬元素。
  17. 如請求項11之半導體裝置之製造方法，其中  上述第2配線包含：第7金屬層及第8金屬層，該第7金屬層係設置於上述第2絕緣膜內該第8金屬層係介隔上述第7金屬層設置於上述第2絕緣膜內且與上述第4金屬層直接相接。
  18. 如請求項17之半導體裝置之製造方法，其中  上述第4金屬層與上述第8金屬層包含相同之金屬元素。
  19. 一種半導體裝置之製造方法，其包含：  於第1基板之上方形成第1絕緣膜；  於上述第1絕緣膜內形成第1配線；  於上述第1絕緣膜內，在上述第1配線上形成第1焊墊；  於第2基板之上方形成第2絕緣膜；  於上述第2絕緣膜內形成第2配線；  於上述第2絕緣膜內，在上述第2配線上形成第2焊墊；及  藉由將上述第1焊墊與上述第2焊墊貼合，而於上述第1焊墊上配置上述第2焊墊；  上述第1焊墊包含：第1金屬層及第2金屬層，該第1金屬層係設置於上述第1絕緣膜內，該第2金屬層係介隔上述第1金屬層設置於上述第1絕緣膜內且與上述第1配線直接相接，  於上述第1焊墊之形成中，於上述第1絕緣膜之側面與上述第1配線之上表面依次形成第1膜及第2膜，使上述第1膜之一部分變質而形成上述第1金屬層，藉由上述第1膜之另一部分與上述第2膜而形成上述第2金屬層。
  20. 如請求項19之半導體裝置之製造方法，其中  上述第2焊墊包含：第3金屬層及第4金屬層，該第3金屬層係設置於上述第2絕緣膜內，該第4金屬層係介隔上述第3金屬層設置於上述第2絕緣膜內且與上述第2配線直接相接，  於上述第2焊墊之形成中，於上述第2絕緣膜之側面與上述第2配線之上表面依次形成第3膜及第4膜，使上述第3膜之一部分變質而形成上述第3金屬層，藉由上述第3膜之另一部分與上述第4膜而形成上述第4金屬層。
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