CN110246821A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN110246821A
CN110246821A CN201810886862.7A CN201810886862A CN110246821A CN 110246821 A CN110246821 A CN 110246821A CN 201810886862 A CN201810886862 A CN 201810886862A CN 110246821 A CN110246821 A CN 110246821A
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Prior art keywords
plug
metal gasket
weld pad
interlayer
semiconductor device
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Granted
Application number
CN201810886862.7A
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CN110246821B (zh
Inventor
田上政由
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Kioxia Corp
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Toshiba Memory Corp
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Publication of CN110246821A publication Critical patent/CN110246821A/zh
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Publication of CN110246821B publication Critical patent/CN110246821B/zh
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Abstract

实施方式提供一种能够将焊垫彼此适当地接合的半导体装置。根据一实施方式，半导体装置具备：第1芯片，具有第1插塞、及设置在所述第1插塞上的第1焊垫；及第2芯片，具有第2插塞、及设置在所述第2插塞下的第2焊垫。所述第2芯片具备：电极层，和所述第2插塞电连接；电荷蓄积层，在所述电极层的侧面介隔第1绝缘膜而设置；及半导体层，在所述电荷蓄积层的侧面介隔第2绝缘膜而设置。而且，所述第1焊垫与所述第2焊垫接合；所述第1及第2插塞是以在和所述基板的表面垂直的第1方向上，所述第1插塞和所述第2插塞至少一部分不相互重叠的方式配置。

Description

半导体装置
[相关申请]
本申请享受以日本专利申请2018-40790号(申请日：2018年3月7日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
三维存储器等半导体装置有时是通过利用贴合工序将某个晶片的金属垫和另一晶片的金属垫接合而制造。在该情况下，有因所述金属垫的对准偏离等而导致金属垫彼此未适当地接合的可能性。
发明内容
本实施方式提供一种能够将焊垫彼此适当地接合的半导体装置。
根据一实施方式，半导体装置具备：第1芯片，具有第1插塞、及设置在所述第1插塞上的第1焊垫；及第2芯片，具有第2插塞、及设置在所述第2插塞下的第2焊垫。所述第2芯片具备：电极层，和所述第2插塞电连接；电荷蓄积层，在所述电极层的侧面介隔第1绝缘膜而设置；以及半导体层，在所述电荷蓄积层的侧面介隔第2绝缘膜而设置。而且，所述第1焊垫与所述第2焊垫接合；所述第1及第2插塞是以在和所述基板的表面垂直的第1方向上，所述第1插塞和所述第2插塞至少一部分不相互重叠的方式配置。
另外，所述第1插塞的厚度理想为所述第1焊垫的厚度的2倍以上，所述第2插塞的厚度理想为所述第2焊垫的厚度的2倍以上。
此外，所述半导体装置理想为还具备：第1配线，在设置在所述第1插塞下的第1配线层内延伸，且和所述第1插塞电连接；及第2配线，在设置在所述第2插塞上的第2配线层内延伸，且和所述第2插塞电连接。
此外，所述半导体装置理想为还具备第3插塞，该第3插塞设置在所述第2焊垫上，且以和在所述第2配线层内延伸的各配线非接触的方式配置。
此外，所述第1及第3插塞理想为以在所述第1方向所述第1插塞和所述第3插塞至少一部分不相互重叠的方式配置。
此外，所述半导体装置理想为还具备第4插塞，该第4插塞设置在所述第1焊垫下，且以和在所述第1配线层内延伸的各配线非接触的方式配置。
此外，所述第2及第4插塞理想为以在所述第1方向所述第2插塞和所述第4插塞至少一部分不相互重叠的方式配置。
此外，所述第1及第2焊垫理想含有铜或镍。
此外，所述第1焊垫和所述第2焊垫理想为经由从所述第1焊垫的上表面突出的第1突出部及/或从所述第2焊垫的下表面突出的第2突出部而相互电连接。
此外，所述第1插塞理想为和设置在所述第1插塞的下方的晶体管电连接。
此外，根据一实施方式，半导体装置具备：基板；第1插塞，设置在所述基板的上方；第1焊垫，设置在所述第1插塞上；第2焊垫，设置在所述第1焊垫上，且和所述第1焊垫电连接；以及第2插塞，设置在所述第2焊垫上。所述第1及第2插塞是以在和所述基板的表面垂直的第1方向上，所述第1插塞和所述第2插塞不相互重叠的方式配置。
附图说明
图1是表示第1实施方式的半导体装置的构造的剖视图。
图2是表示第1实施方式的柱状部的构造的剖视图。
图3是表示第1实施方式的半导体装置的制造方法的剖视图。
图4～5是用于对第1实施方式的半导体装置的构造进行说明的剖视图及俯视图。
图6～8是用于对第1实施方式的比较例的半导体装置的问题进行说明的剖视图。
图9是用于对第1实施方式的变化例的半导体装置的构造进行说明的俯视图。
图10～11是用于对第2实施方式的半导体装置的构造进行说明的剖视图及俯视图。
图12是用于对第2实施方式的变化例的半导体装置的构造进行说明的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。
(第1实施方式)
图1是表示第1实施方式的半导体装置的构造的剖视图。图1的半导体装置是将阵列芯片1和电路芯片2贴合而成的三维存储器。
阵列芯片1具备：包含多个存储单元的存储单元阵列11；存储单元阵列11上的绝缘层12(例如氮化硅膜)；绝缘层12上的绝缘层13(例如氧化硅膜)；及存储单元阵列11下的层间绝缘膜14。
电路芯片2介隔绝缘层15而设置在阵列芯片1下。电路芯片2具备层间绝缘膜16、及层间绝缘膜16下的基板17。基板17例如是硅基板等半导体基板。图1中表示和基板17的表面平行且相互垂直的X方向及Y方向、以及和基板17的表面垂直的Z方向。在本说明书中，将+Z方向设为上方向，将-Z方向设为下方向，但-Z方向既可和重力方向一致也可不一致。Z方向是第1方向的一例。
阵列芯片1具备多个字线WL、背栅极BG、及选择栅极SG作为存储单元阵列11内的电极层。图1表示存储单元阵列11的阶段构造部21。如图1所示，各字线WL经由接触插塞22而和字元配线层23电连接，背栅极BG经由接触插塞24而和背栅极配线层25电连接，选择栅极SG经由接触插塞26而和选择栅极配线层27电连接。贯通字线WL、背栅极BG、及选择栅极SG的柱状部CL经由插塞28而和位线BL电连接。
电路芯片2具备多个晶体管31。各晶体管31具备：介隔栅极绝缘膜而设置在基板17上的栅极电极32；以及设置在基板17内的未图示的源极扩散层及漏极扩散层。电路芯片2还具备：设置在所述晶体管31的源极扩散层或漏极扩散层上的多个插塞33；设置在所述插塞33上且包含多个配线的配线层34；及设置在配线层34上且包含多个配线的配线层35。设置在绝缘层15内的多个金属垫36是设置在配线层35上。阵列芯片1具备设置在所述金属垫36上且包含多个配线的配线层37。本实施方式的各字线WL和配线层37电连接。
另外，配线层35、金属垫36、及配线层37的构造的详细说明将参照图4等在后文叙述。配线层35是第1配线层的例子。金属垫36是第1焊垫和第2焊垫的例。配线层37是第2配线层的例子。
阵列芯片1还具备：经由未图示的介层插塞而和配线层37电连接的焊垫41；设置在焊垫41上的外部连接电极42；以及设置在外部连接电极42上的外部连接焊垫43。外部连接焊垫43可经由焊锡球、金属凸块、接合线等而连接在安装基板或其他装置。
图2是表示第1实施方式的柱状部CL的构造的剖视图。
如图2所示，存储单元阵列11具备在层间绝缘膜14上交替层叠的多个字线WL及多个绝缘层51。各字线WL例如是W(钨)层。各绝缘层51例如是氧化硅膜。
柱状部CL具备：作为第1绝缘膜的例的阻挡绝缘膜52；电荷蓄积层53；作为第2绝缘膜的例的穿隧绝缘膜54；通道半导体层55；及核心绝缘膜56。电荷蓄积层53例如是氮化硅膜，在字线WL及绝缘层51的侧面介隔阻挡绝缘膜52而形成。通道半导体层55例如是硅层，在电荷蓄积层53的侧面介隔穿隧绝缘膜54而形成。阻挡绝缘膜52、穿隧绝缘膜54、及核心绝缘膜56的例是氧化硅膜或金属绝缘膜。
图3是表示第1实施方式的半导体装置的制造方法的剖视图。
图3中表示包含多个阵列芯片1的阵列晶片W1、及包含多个电路芯片2的电路晶片W2。图3进一步表示设置在电路晶片W2的上表面的第1绝缘层61及多个第1金属垫62、以及设置在阵列晶片W1的下表面的第2绝缘层71及多个第2金属垫72。各第1金属垫62设置在配线层35的上表面，各第2金属垫72设置在配线层37的下表面。此外，阵列晶片W1在绝缘层13上具备基板18。
另外，在图3中，是在层间绝缘膜16的上表面形成第1绝缘层61，但第1绝缘层61也可包含在层间绝缘膜16而一体化。同样地，在图3中，是在层间绝缘膜14的下表面形成第2绝缘层71，但第2绝缘层71也可包含在层间绝缘膜14而一体化。
首先，通过机械压力将阵列晶片W1和电路晶片W2贴合。由此，将第1绝缘层61和第2绝缘层71接着，形成绝缘层15。其次，以400℃的温度对阵列晶片W1及电路晶片W2进行退火。由此，将第1金属垫62和第2金属垫72接合，形成多个金属垫36。
其后，通过CMP(Chemical Mechanical Polishing，化学机械抛光)或湿式蚀刻将基板18除去，将阵列晶片W1及电路晶片W2切断成多个芯片。如此，制造图1的半导体装置。另外，外部连接电极42和外部连接焊垫43例如是在基板18的除去后形成在焊垫41上。
图4及5是用于对第1实施方式的半导体装置的构造进行说明的剖视图及俯视图。图4是表示绝缘层15、金属垫36附近的构造的俯视图，图5是沿着图4的A-A'线的剖视图。
本实施方式的半导体装置具备：设置在电路芯片2内的第1金属垫62、第1介层插塞63、第1配线64、及第1配线65、以及设置在阵列芯片1内的第2金属垫72、第2介层插塞73、及第2配线74。
符号A1表示第1金属垫62的厚度，符号B1表示第1介层插塞63的厚度。由此，A1+B1相当于第1金属垫62和第1介层插塞63的合计厚度。符号A2表示第2金属垫72的厚度，符号B2表示第2介层插塞73的厚度。由此，A2+B2相当于第2金属垫72和第2介层插塞73的合计厚度。
第1配线64、65是构成配线层35的配线，本实施方式中是在金属垫36的附近沿着Y方向延伸。配线层35例如是W层。第1配线64例如和任一晶体管31的源极扩散层或漏极扩散层电连接。
第1介层插塞63设置在第1配线64上，且和第1配线64电连接。第1介层插塞63例如是Cu(铜)插塞。本实施方式的第1介层插塞63的平面形状为圆形，但也可为其他形状。第1介层插塞63的厚度B1例如为第1金属垫62的厚度A1的2倍以上(B1≧2×A1)。
第1金属垫62设置在第1介层插塞63上，且和第1介层插塞63电连接。第1金属垫62例如是Cu焊垫。本实施方式的第1金属垫62的平面形状是具有和X方向平行的2边及和Y方向平行的2边的四边形，但也可为其他形状。
第2金属垫72设置在第1金属垫62上，且和第1金属垫62电连接。第2金属垫72例如是Cu焊垫。本实施方式的第2金属垫72的平面形状是具有和X方向平行的2边及和Y方向平行的2边的四边形，但也可为其他形状。本实施方式中，第2金属垫72的上表面及下表面的面积是设定为和第1金属垫62的上表面及下表面的面积大致相同的值。
第2介层插塞73设置在第2金属垫72上，且和第2金属垫72电连接。第2介层插塞73例如是Cu插塞。本实施方式的第2介层插塞73的平面形状为圆形，但也可为其他形状。第2介层插塞73的厚度B2例如是第2金属垫72的厚度A2的2倍以上(B2≧2×A2)。
第2配线74是构成配线层37的配线，本实施方式中是在金属垫36附近沿着X方向延伸。配线层37例如是W层。第2配线74例如和任一字线WL电连接。
另外，第1金属垫62和第2金属垫72只要能通过贴合工序接合，则也可为Cu焊垫以外的金属垫。此种金属垫的例为Ni(镍)焊垫。此外，第1及第2介层插塞63、73在本实施方式中是通过和第1及第2金属垫62、72相同的材料形成，但也可通过和第1及第2金属垫62、72不同的材料形成。
图5表示从第1金属垫62的上表面突出的突出部62a、及从第2金属垫72的下表面突出的突出部72a。第1及第2金属垫62、72在对阵列晶片W1及电路晶片W2进行退火时膨胀。依据实验，第1金属垫62容易在第1介层插塞63的上方膨胀，合计厚度A1+B1越大，则第1金属垫62的膨胀的程度越大。同样地，第2金属垫72容易在第2介层插塞73的下方膨胀，合计厚度A2+B2越大，则第2金属垫72的膨胀的程度越大。
因此，若对阵列晶片W1及电路晶片W2进行退火，则突出部62a从第1金属垫62的上表面突出，突出部72a从第2金属垫72的下表面突出。在本实施方式中，第1金属垫62的突出部62a是和第2金属垫72接合，第2金属垫72的突出部72a是和第1金属垫62接合。结果为，第1金属垫62和第2金属垫72经由突出部62a及突出部72a而相互电连接。
图4表示第1介层插塞63和第2介层插塞73的位置关系。本实施方式的第1及第2介层插塞63、73是以在Z方向上第1介层插塞63和第2介层插塞73不相互重叠的方式配置。结果为，若将突出部62a、72a不相互接触时的突出部62a、72a的面积分别以S1、S2表示，则第1金属垫62和第2金属垫72的接合面积大致为S1+S2。由此，根据本实施方式，可确保第1金属垫62和第2金属垫72的接合面积大，从而可减小第1金属垫62和第2金属垫72的接合部分的电阻。
另外，如图4所示，第2介层插塞73并非配置在第1介层插塞63的X方向或Y方向，而是相对于第1介层插塞63配置在X方向和Y方向之间的方向。此种配置具有在Z方向上容易地将第1介层插塞63及第2介层插塞73不重叠地配置的优点。
本实施方式的第1金属垫62和第2金属垫72是以在Z方向上完全重叠的方式配置。然而，因贴合阵列晶片W1和电路晶片W2时的偏离，有第1金属垫62和第2金属垫72在Z方向未完全重叠地配置的情况。在本实施方式中，设计第1及第2介层插塞63、73的布局时，无论前者的情况还是后者的情况，理想为设计成第1介层插塞63和第2介层插塞73在Z方向上不重叠。该点例如可通过在设计第1及第2介层插塞63、73的布局时，确保第1介层插塞63和第2介层插塞73的距离充分大而实现。以上的内容也能适用于第1介层插塞63及后述虚设介层插塞75。
图6～8是用于对第1实施方式的比较例的半导体装置的问题进行说明的剖视图。
图6表示通过突出部62a、72a接合的第1金属垫62及第2金属垫72。然而，应留意第1介层插塞63和第2介层插塞73的厚度薄。
图7模式性表示第1金属垫62和第2金属垫72退火时变形(凹陷)的状况。在该情况下，有第1金属垫62和第2金属垫72未接合的可能性。
图8表示产生第1金属垫62和第2金属垫72的对准偏离的状况。在该情况下，第1金属垫62和第2金属垫72未接合的可能性进一步变高。
所述问题均是由于第1及第2金属垫62、72的膨胀不足引起。为了应对所述问题，例如考虑加厚第1金属垫62或第2金属垫72。然而，若加厚第1金属垫62或第2金属垫72，则形成第1金属垫62或第2金属垫72的成本上升、多个第1金属垫62彼此或多个第2金属垫72彼此的特性不均成为问题。
因此，在本实施方式中，加厚第1介层插塞63或第2介层插塞73。具体而言，将第1介层插塞63的厚度B1设定为第1金属垫62的厚度A1的2倍以上，将第2介层插塞73的厚度B2设定为第2金属垫72的厚度A2的2倍以上。由此，可增加突出部62a、72a的厚度，在图7或图8的情况下也能将第1金属垫62和第2金属垫72接合。
此外，在本实施方式中，第1介层插塞63和第2介层插塞73是以在Z方向不重叠的方式配置。由此，可减小第1金属垫62和第2金属垫72的接合部分的电阻。另外，在本实施方式中，为了在图7或图8的情况下也将第1金属垫62和第2金属垫72接合，可使突出部62a、72a充分厚。该点如上所述可通过加厚第1介层插塞63或第2介层插塞73而实现。
图9是用于对第1实施方式的变化例的半导体装置的构造进行说明的俯视图。
图4的第1及第2介层插塞63、73是以在Z方向上第1介层插塞63和第2介层插塞73不相互重叠的方式配置。另一方面，图9的第1及第2介层插塞63、73是以在Z方向上第1介层插塞63的一部分和第2介层插塞73的一部分相互重叠的方式配置。符号R1、R2、R3分别表示第1介层插塞63的非重叠部分、第2介层插塞73的非重叠部分、第1介层插塞63和第2介层插塞73的重叠部分。
根据本变化例，即便在第1介层插塞63和第2介层插塞73重叠的情况下，也可通过减小重叠部分R3而减小第1金属垫62和第2金属垫72的接合部分的电阻。重叠部分R3的面积例如为非重叠部分R1或R2的面积的1/3以下，比佳为非重叠部分R1或R2的面积的1/4以下。
如以上般，本实施方式的第1及第2介层插塞63、73是以在Z方向上第1介层插塞63和第2介层插塞73不相互重叠的方式配置，或者以在Z方向上第1介层插塞63的一部分和第2介层插塞73的一部分相互重叠的方式配置。由此，根据本实施方式，能够将第1金属垫62と第2金属垫72适当地接合，如可减小第1金属垫62和第2金属垫72的接合部分的电阻，或可抑制第1金属垫62和第2金属垫72的接合不良等。
另外，第1金属垫62和第2金属垫72不仅可通过突出部62a、72a相互接合，也可在突出部62a、72a以外的焊垫表面相互接合。由此，可进一步减小接合部分的电阻。在该情况下，考虑在第1金属垫62和第2金属垫72之间，在除突出部62a、72a以外的区域形成空洞。例如，从Z方向观察时，当第1介层插塞63和第2介层插塞73的距离远时，考虑在突出部62a和突出部72a之间形成空洞。
(第2实施方式)
图10及11是用于对第2实施方式的半导体装置的构造进行说明的剖视图及俯视图。图10是表示绝缘层15或金属垫36附近的构造的俯视图，图11是沿着图10的A-A'线的剖视图。
本实施方式的半导体装置除了具备图4及图5所示的构成要素以外，还具备虚设介层插塞75。虚设介层插塞75是第3插塞的一例，设置在阵列芯片1内。符号C2表示虚设介层插塞75的厚度。由此，A2+C2相当于第2金属垫72和虚设介层插塞75的合计厚度。
和第2介层插塞73同样地，虚设介层插塞75设置在第2金属垫72上，且和第2金属垫72电连接。虚设介层插塞75例如通过Cu(铜)形成。本实施方式的虚设介层插塞75的平面形状为圆形，但也可为其他形状。虚设介层插塞75的厚度C2例如为第2金属垫72的厚度A2的2倍以上(C2≧2×A2)。
本实施方式的虚设介层插塞75准确而言是如图10所示般配置在第2金属垫72的上表面的左上的角部附近。然而，在图11中，为了便在观察图，应留意虚设介层插塞75是描绘在和图10不同的位置。
第2介层插塞73和在配线层37内延伸的第2配线74接触，作为第2配线74用的插塞发挥功能。另一方面，虚设介层插塞75是以和在配线层37内延伸的各配线非接触的方式配置，并不作为在配线层37内延伸的各配线用的插塞发挥功能。即，虚设介层插塞75处于并不和配线层37直接导通的浮动状态。
另外，虚设介层插塞75在本实施方式中是通过和第2金属垫72相同的材料形成，但也可通过和第2金属垫72不同的材料形成。
图11表示从第2金属垫72的下表面突出的突出部72b。对阵列晶片W1及电路晶片W2进行退火时，第2金属垫72容易在虚设介层插塞75的下方膨胀，合计厚度A2+C2越大，则第2金属垫72的膨胀的程度越大。
因此，若对阵列晶片W1及电路晶片W2进行退火，则突出部72b从第2金属垫72的下表面突出。在本实施方式中，第1金属垫62的突出部62a和第2金属垫72接合，第2金属垫72的突出部72a、72b和第1金属垫62接合。结果为，第1金属垫62和第2金属垫72经由突出部62a、突出部72a、及突出部72b而相互电连接。
图10表示第1介层插塞63、第2介层插塞73、及虚设介层插塞75的位置关系。本实施方式的第1介层插塞63和虚设介层插塞75是以在Z方向上第1介层插塞63和虚设介层插塞75不相互重叠的方式配置。结果为，若将突出部62a、72a、72b不相互接触时的突出部62a、72a、72b的面积分别设为S1、S2、S3，则第1金属垫62和第2金属垫72的接合面积大致为S1+S2+S3。由此，根据本实施方式，可确保第1金属垫62和第2金属垫72的接合面积进一步大，从而可进一步减小第1金属垫62和第2金属垫72的接合部分的电阻。
另外，第1介层插塞63和虚设介层插塞75也可和图9的情况同样地，以在Z方向上第1介层插塞63的一部分和虚设介层插塞75的一部分相互重叠的方式配置。在该情况下，可通过减小第1介层插塞63和虚设介层插塞75的重叠部分，而减小第1金属垫62和第2金属垫72的接合部分的电阻。
图12是用于对第2实施方式的变化例的半导体装置的构造进行说明的剖视图。
本变化例的半导体装置具备虚设插塞66来代替虚设介层插塞75。虚设介层插塞66是第4插塞的一例，设置在电路芯片2内。符号C1表示虚设介层插塞66的厚度。由此，A1+C1相当于第1金属垫62和虚设介层插塞66的合计厚度。
虚设介层插塞66的详细是和虚设介层插塞75的详细大致相同。和第1介层插塞63同样地，虚设介层插塞66设置在第1金属垫62下，且和第1金属垫62电连接。虚设介层插塞66的厚度C1例如为第1金属垫62的厚度A1的2倍以上(C1≧2×A1)。
第1介层插塞63和在配线层35内延伸的第1配线64接触，作为第1配线64用的插塞发挥功能。另一方面，虚设介层插塞66是和在配线层35内延伸的各配线非接触的方式配置，并不作为在配线层35内延伸的各配线用的插塞发挥功能。即，虚设介层插塞66处于不和配线层35直接导通的浮动状态。
对阵列晶片W1及电路晶片W2进行退火时，第1金属垫62容易在虚设介层插塞66的上方膨胀，合计厚度A1+C1越大，则第1金属垫62的膨胀的程度越大。因此，若对阵列晶片W1及电路晶片W2进行退火，则突出部62b从第1金属垫62的上表面突出。本变化例的第1金属垫62和第2金属垫72是经由突出部62a、突出部72a、及突出部62b而相互电连接。
本变化例的第2介层插塞73和虚设介层插塞66是以在Z方向上第2介层插塞73和虚设介层插塞66不相互重叠的方式配置。由此，根据本变化例，可确保第1金属垫62和第2金属垫72的接合面积进一步大，从而可进一步减小第1金属垫62和第2金属垫72的接合部分的电阻。本实施方式的虚设介层插塞66例如配置在第1金属垫62的下表面的右下的角部附近。
另外，第2介层插塞73和虚设介层插塞66也可和图9的情况同样地，以在Z方向上第2介层插塞73的一部分和虚设介层插塞66的一部分相互重叠的方式配置。在该情况下，可通过减小第2介层插塞73和虚设介层插塞66的重叠部分，减小第1金属垫62和第2金属垫72的接合部分的电阻。
如以上般，本实施方式的第1介层插塞63和虚设介层插塞75是以在Z方向上第1介层插塞63和虚设介层插塞75不相互重叠的方式配置，或者以在Z方向上第1介层插塞63的一部分和虚设介层插塞75的一部分相互重叠的方式配置。由此，根据本实施方式，可将第1金属垫62和第2金属垫72更适当地接合。该点对在所述变化例的第2介层插塞73及虚设介层插塞66也相同。
以上对若干实施方式进行了说明，但所述实施方式只是作为示例提示的，并不意图限定发明的范围。本说明书中说明的新颖装置也能以其他各种形态实施。此外，对于本说明书中说明的装置的形态，可在不脱离发明主旨的范围内进行各种省略、置换、变更。随附权利要求及其均等范围意图包含发明范围及主旨所含的此种形态、变化例。
[符号的说明]
1 阵列芯片
2 电路芯片
11 存储单元阵列
12 绝缘层
13 绝缘层
14 层间绝缘膜
15 绝缘层
16 层间绝缘膜
17 基板
18 基板
21 阶段构造部
22 接触插塞
23 字元配线层
24 接触插塞
25 背栅极配线层
26 接触插塞
27 选择栅极配线层
28 插塞
31 晶体管
32 栅极电极
33 插塞
34 配线层
35 配线层
36 金属垫
37 配线层
41 焊垫
42 外部连接电极
43 外部连接焊垫
51 绝缘层
52 阻挡绝缘膜
53 电荷蓄积层
54 穿隧绝缘膜
55 通道半导体层
56 核心绝缘膜
61 第1绝缘层
62 第1金属垫
62a 突出部
62b 突出部
63 第1介层插塞
64 第1配线
65 第1配线
66 虚设介层插塞
71 第2绝缘层
72 第2金属垫
72a 突出部
72b 突出部
73 第2介层插塞
74 第2配线
75 虚设介层插塞

Claims (10)

1.一种半导体装置，其特征在于具备：
第1芯片，具有第1插塞、及设置在所述第1插塞上的第1焊垫；及
第2芯片，具有第2插塞、及设置在所述第2插塞下的第2焊垫；
所述第2芯片具备：
电极层，和所述第2插塞电连接；
电荷蓄积层，在所述电极层的侧面介隔第1绝缘膜而设置；以及
半导体层，在所述电荷蓄积层的侧面介隔第2绝缘膜而设置；且
所述第1焊垫与所述第2焊垫接合；
所述第1及第2插塞是以在和所述基板的表面垂直的第1方向上，所述第1插塞和所述第2插塞至少一部分不相互重叠的方式配置。
2.根据权利要求1所述的半导体装置，其特征在于所述第1插塞的厚度为所述第1焊垫的厚度的2倍以上，所述第2插塞的厚度为所述第2焊垫的厚度的2倍以上。
3.根据权利要求1或2所述的半导体装置，其特征在于还具备：
第1配线，在设置在所述第1插塞下的第1配线层内延伸，且和所述第1插塞电连接；及
第2配线，在设置在所述第2插塞上的第2配线层内延伸，且和所述第2插塞电连接。
4.根据权利要求3所述的半导体装置，其特征在于还具备第3插塞，该第3插塞设置在所述第2焊垫上，且以和在所述第2配线层内延伸的各配线非接触的方式配置。
5.根据权利要求4所述的半导体装置，其特征在于所述第1及第3插塞是以在所述第1方向上，所述第1插塞和所述第3插塞至少一部分不相互重叠的方式配置。
6.根据权利要求3所述的半导体装置，其特征在于还具备第4插塞，该第4插塞设置在所述第1焊垫下，且以和在所述第1配线层内延伸的各配线非接触的方式配置。
7.根据权利要求6所述的半导体装置，其特征在于所述第2及第4插塞是以在所述第1方向上，所述第2插塞和所述第4插塞至少一部分不相互重叠的方式配置。
8.根据权利要求1或2所述的半导体装置，其特征在于所述第1及第2焊垫含有铜或镍。
9.根据权利要求1或2所述的半导体装置，其特征在于所述第1焊垫和所述第2焊垫是经由从所述第1焊垫的上表面突出的第1突出部及/或从所述第2焊垫的下表面突出的第2突出部而相互电连接。
10.根据权利要求1或2所述的半导体装置，其特征在于所述第1插塞和设置在所述第1插塞的下方的晶体管电连接。
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