TW202238963A - 半導體記憶裝置及半導體記憶裝置之製造方法 - Google Patents
半導體記憶裝置及半導體記憶裝置之製造方法 Download PDFInfo
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- TW202238963A TW202238963A TW110125808A TW110125808A TW202238963A TW 202238963 A TW202238963 A TW 202238963A TW 110125808 A TW110125808 A TW 110125808A TW 110125808 A TW110125808 A TW 110125808A TW 202238963 A TW202238963 A TW 202238963A
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Abstract
實施方式提供可謀求電氣特性的提升的半導體記憶裝置及半導體記憶裝置之製造方法。
實施方式的半導體記憶裝置具有第1基板、第2基板、第1層積體及第2層積體。前述第1層積體設於前述第1基板與前述第2基板之間,並包含第1佈線、連接於前述第1佈線的第1墊及第1絕緣體。前述第2層積體設於前述第1層積體與前述第2基板之間,並包含第2佈線、連接於前述第2佈線的第2墊及第2絕緣體。前述第1墊包含分別連接於前述第1佈線的複數個第1電極部。於前述複數個第1電極部之間,設有前述第1絕緣體。前述複數個第1電極部接合於前述第2墊。
Description
本發明的實施方式涉及半導體記憶裝置及半導體記憶裝置之製造方法。
[關聯案]
本案主張以日本特願2021-042688號(申請日:2021年3月16日)為基礎案的優先權。本案透過參照此基礎案從而包含基礎案的全部的內容。
已知將複數個晶圓彼此予以貼合從而製造的半導體記憶裝置。
本發明打算解決的課題在於提供可謀求電氣特性的提升的半導體記憶裝置及半導體記憶裝置之製造方法。
實施方式的半導體記憶裝置具有第1基板、第2基板、第1層積體及第2層積體。前述第2基板在為前述第1基板的厚度方向之第1方向上從前述第1基板分離。前述第1層積體設於前述第1基板與前述第2基板之間,並包含第1佈線、連接於前述第1佈線的第1墊及第1絕緣體。前述第2層積體設於前述第1層積體與前述第2基板之間,並包含第2佈線、連接於前述第2佈線的第2墊及第2絕緣體。前述第1墊包含在與前述第1方向交叉的第2方向彼此分離並分別連接於前述第1佈線的複數個第1電極部。於前述複數個第1電極部之間,設有前述第1絕緣體。前述複數個第1電極部接合於前述第2墊。
以下,就實施方式的半導體記憶裝置,參照圖式進行說明。在以下的說明,對具有相同或類似的功能的構成標注相同的符號。並且,該等構成的重複的說明有時省略。「連接」不限定於物理上連接的情況,亦包含電連接的情況。亦即,「連接」不限定於直接地相接的情況,亦包含別的構件介於之間的情況。「環狀」不限定於圓環狀,亦包含矩形狀的環狀。「平行」、「正交」、「相同」分別亦包括「大致平行」、「大致正交」、「大致相同」的情況。
首先,就X方向、Y方向、+Z方向及-Z方向進行定義。X方向及Y方向為沿著後述的第1基板10(圖1參照)的表面10a的方向。Y方向為與X方向交叉(例如正交)的方向。+Z方向及-Z方向為與X方向及Y方向交叉(例如正交)的方向,並為第1基板10的厚度方向。+Z方向為從第1基板10朝往第2基板60(圖1參照)的方向。-Z方向與+Z方向為相反方向。不區別+Z方向與-Z方向的情況下,僅稱為「Z方向」。在以下的說明,有時將「+Z方向」稱為「上」,將「-Z方向」稱為「下」。其中,此等表現僅為了方便而非界定重力方向。Z方向為「第1方向」的一例。X方向及Y方向之中的任一者為「第2方向」的一例。X方向及Y方向之中的另一者為「第3方向」的一例。
(實施方式)
<1. 半導體記憶裝置的整體構成>
首先,就實施方式的半導體記憶裝置1的整體構成進行說明。半導體記憶裝置1為非揮發性的半導體記憶裝置,並例如為NAND型快閃記憶體。
圖1為就半導體記憶裝置1的構成進行繪示的剖面圖。半導體記憶裝置1例如為電路晶片2與陣列晶片3在貼合面S被貼合的3維記憶體。電路晶片2為「第1晶片」的一例。陣列晶片3為「第2晶片」的一例。電路晶片2包含控制陣列晶片3的動作的控制電路(邏輯電路)。以下,就如此的半導體記憶裝置1詳細進行說明。
半導體記憶裝置1例如具備第1基板10、層積體20、第2基板60及絕緣層72、73。
第1基板10為含於電路晶片2中的基板。第1基板10例如為矽基板。第1基板10具有被層積層積體20的表面10a。於第1基板10,設有含於層積體20中的電晶體31(後述)的源極區域及汲極區域。
層積體20在Z方向上位於第1基板10與第2基板60之間。層積體20包含第1層積體30與第2層積體40。第1層積體30設於第1基板10上。第1層積體30在Z方向上位於第1基板10與第2層積體40之間。在本實施方式,由第1基板10與第1層積體30構成電路晶片2。第1層積體30包含複數個電晶體31(圖1中僅圖示1個)、複數個接觸插塞32、複數個佈線33、複數個墊34及第1絕緣體35。
電晶體31設於第1基板10上。電晶體31連接於接觸插塞32。電晶體31經由含於層積體20中的接觸插塞32、42、佈線33、43及墊34、44而與記憶體單元陣列41或外部連接墊71電連接。電晶體31例如控制記憶體單元陣列41。
接觸插塞32、佈線33及墊34將複數個電晶體31與第2層積體40電連接。接觸插塞32、佈線33及墊34由如銅(Cu)或鋁(Al)的導電材料形成。接觸插塞32延伸於Z方向,並為將第1層積體30內的不同的層間進行電連接的佈線。佈線33為延伸於X方向或Y方向的佈線。
墊34為設於第1層積體30的連接用的電極。墊34包含設於第1層積體30的內部的內部墊與曝露於第1層積體30的表面(貼合面S)的接合墊38。接合墊38為「第1墊」的一例。複數個佈線33的之中連接於接合墊38的佈線37為「第1佈線」的一例。接合墊38方面,細節後述之。
第1絕緣體35設於複數個接觸插塞32、複數個佈線33及複數個墊34之間,將此等要素彼此電絕緣。第1絕緣體35例如由TEOS(正矽酸乙酯(Si(OC
2H
5)
4)、矽氧化物(SiO
2)或矽氮化物(SiN)等形成。
第2層積體40設於第1層積體30上。第2層積體40在Z方向上位於第1層積體30與第2基板60之間。在本實施方式,由第2基板60與第2層積體40構成陣列晶片3。第2層積體40包含記憶體單元陣列41、複數個接觸插塞42、複數個佈線43、複數個墊44及第2絕緣體45。
記憶體單元陣列41設於第2基板60的下方。記憶體單元陣列41在製造時層積於第2基板60上(圖8參照)。記憶體單元陣列41具有複數個導電層51與複數個記憶體柱P。複數個導電層51及複數個記憶體柱P中的各者連接於接觸插塞42。
複數個導電層51例如由摻雜鎢(W)或雜質的多晶矽(Poly-Si)形成。複數個導電層51於之間夾著含於第2絕緣體45的層間絕緣膜45b(圖2參照)而層積於Z方向。複數個導電層51之中第1層積體30側(-Z方向側)的1個或2個導電層51作用為汲極側選擇閘線SGD。複數個導電層51之中第2基板60側(+Z方向側)的1個或2個導電層51作用為源極側選擇閘線SGS。複數個導電層51之中位於汲極側選擇閘線SGD與源極側選擇閘線SGS之間的其餘的導電層51作用為複數個字線WL。
複數個記憶體柱P延伸於Z方向,並貫通汲極側選擇閘線SGD、複數個字線WL及源極側選擇閘線SGS。於複數個字線WL與複數個記憶體柱P的交叉部分中的各者,形成有記憶體單元MC。據此,複數個記憶體單元MC被於X方向、Y方向及Z方向上隔著間隔而3維狀地配置。記憶體單元MC方面,細節後述之。
接觸插塞42、佈線43及墊44將記憶體單元陣列41或後述的外部連接墊71與第1層積體30電連接。接觸插塞42、佈線43及墊44由如銅或鋁的導電材料形成。接觸插塞42延伸於Z方向,並為將第2層積體40內的不同的層間電連接的佈線。佈線43為延伸於X方向或Y方向的佈線。
墊44為設於第2層積體40的連接用的電極。墊44包含設於第2層積體40的內部的內部墊與曝露於第2層積體40的表面(貼合面S)的接合墊48。在第1層積體30與第2層積體40被層積的狀態下,第2層積體40的接合墊48設於第1層積體30的接合墊38上,並與第1層積體30的接合墊38接合。接合墊48為「第2墊」的一例。複數個佈線43的之中連接於接合墊48的佈線47為「第2佈線」的一例。接合墊48方面,細節後述之。
第2絕緣體45設於複數個接觸插塞42、複數個佈線43及複數個墊44之間,將此等要素彼此電絕緣。第2絕緣體45例如由TEOS、矽氧化物或矽氮化物等形成。
第2基板60設於第2層積體40之上方。第2基板60位於在Z方向上與第1基板10分離的位置。第2基板60為含於陣列晶片3中的基板。第2基板60例如為矽基板。於第2基板60,設有作用為記憶體單元陣列41的源極線的導電區域。第2基板60具有面向記憶體單元陣列41的第1面60a與位於與第1面60a相反側的第2面60b。於第2面60b,設有外部連接墊71。外部連接墊71設有未圖示的外部連接端子(例如焊球),並經由該外部連接端子而與半導體記憶裝置1的外部電連接。
絕緣層72設於第2基板60上。絕緣層73設於絕緣層72上。絕緣層72、73為保護層積體20的鈍化膜。絕緣層72例如為矽氧化膜。絕緣層73例如為聚醯亞胺膜。
圖2為就記憶體單元陣列41的記憶體柱P的附近進行繪示的剖面圖。如示於圖2,複數個字線WL於之間夾著層間絕緣膜45b而層積於Z方向。複數個字線WL延伸於X方向。記憶體單元陣列41具有被設置記憶體柱P的記憶體孔MH。記憶體柱P在記憶體孔MH的內部延伸於Z方向,貫通複數個字線WL。
記憶體柱P在從Z方向觀看的情況下為例如圓狀或橢圓狀。記憶體柱P從內側依序具有核心絕緣體52、半導體本體53及記憶體膜54。
核心絕緣體52為延伸於Z方向的柱狀體。核心絕緣體52例如包含矽氧化物。核心絕緣體52位於半導體本體53的內側。
半導體本體53延伸於Z方向並作用為通道。半導體本體53連接於作用為第2基板60的源極線的導電區域。半導體本體53覆蓋核心絕緣體52的外周面。半導體本體53包含例如矽。矽例如為使非晶矽結晶化的多晶矽。
記憶體膜54延伸於Z方向。記憶體膜54覆蓋半導體本體53的外周面。記憶體膜54位於記憶體孔MH的內面與半導體本體53的外側面之間。記憶體膜54例如包含通道絕緣膜55與電荷儲存膜56。
通道絕緣膜55位於電荷儲存膜56與半導體本體53之間。通道絕緣膜55例如包含矽氧化物或矽氧化物與矽氮化物。通道絕緣膜55為半導體本體53與電荷儲存膜56之間的電位障壁。
電荷儲存膜56設於字線WL及層間絕緣膜45b中的各者與通道絕緣膜55之間。電荷儲存膜56包含例如矽氮化物。電荷儲存膜56與字線WL的交叉部分作用為記憶體單元MC。記憶體單元MC透過電荷儲存膜56與字線WL的交叉部分(電荷儲存部)內的電荷的有無或累積的電荷量從而保存資料。電荷儲存部位於字線WL與半導體本體53之間,並使周圍被以絕緣材料而包圍。
在字線WL與層間絕緣膜45b之間及字線WL與記憶體膜54之間亦可設有區塊絕緣膜57及屏障膜58。區塊絕緣膜57為抑制反向隧道效應的絕緣膜。反向隧道效應為從字線WL往記憶體膜54的電荷返回的現象。區塊絕緣膜57例如為矽氧化膜、金屬氧化物膜或被層積複數個絕緣膜的層積構造膜。金屬氧化物的一例為鋁氧化物。屏障膜58例如為氮化鈦膜或氮化鈦與鈦的層積構造膜。
於層間絕緣膜45b與電荷儲存膜56之間亦可設有覆蓋絕緣膜59。覆蓋絕緣膜59包含例如矽氧化物。覆蓋絕緣膜59在加工時保護電荷儲存膜56受到蝕刻。覆蓋絕緣膜59可無亦可一部分留於導電層51與電荷儲存膜56之間而用作為區塊絕緣膜。
<2. 接合墊的構成>
接著,就接合墊38、48的構成進行說明。
圖3為就複數個接合墊38、48進行繪示的剖面圖。如示於圖3,第1層積體30的佈線37包含彼此電獨立的佈線37A、37B、37C。於X方向及Y方向,在佈線37A、37B、37C之間設有第1絕緣體35。據此,佈線37A、37B、37C彼此被電絕緣。佈線37A、37B、37C可成為彼此不同的電位。在以下,不將佈線37A、37B、37C彼此區別的情況下,稱為「佈線37」。
第1層積體30的接合墊38包含連接於佈線37A的接合墊38B、連接於佈線37B的接合墊38B及連接於佈線37C的接合墊38C。於X方向及Y方向,在接合墊38A、38B、38C之間設有第1絕緣體35。接合墊38A、38B、38C可成為彼此不同的電位。在以下,不將接合墊38A、38B、38C彼此區別的情況下,稱為「接合墊38」。
在本實施方式,接合墊38A、38B、38C中的各者具有在X方向與Y方向之中的至少一者上彼此分離的複數個電極部81。在此處說明的一例方面,接合墊38A、38B、38C中的各者具有在X方向及Y方向中的各者上彼此分離的複數個電極部81(圖4參照)。於X方向及Y方向,在複數個電極部81之間設有第1絕緣體35。換言之,在Z方向上觀看的情況下,於貼合面S在複數個電極部81之間設有第1絕緣體35。電極部81為「第1電極部」的一例。
複數個電極部81彼此獨立而分別連接於佈線37。亦即,含於相同的接合墊38中的複數個電極部81連接於相同的佈線37。含於相同的接合墊38中的複數個電極部81成為相同的電位。在示於圖3之例,含於接合墊38A中的複數個電極部81連接於佈線37A。含於接合墊38B中的複數個電極部81連接於佈線37B。含於接合墊38C中的複數個電極部81連接於佈線37C。
同樣地,第2層積體40的佈線47包含彼此電獨立的佈線47A、47B、47C。於X方向及Y方向,在佈線47A、47B、47C之間設有第2絕緣體45。據此,佈線47A、47B、47C彼此電絕緣。佈線47A、47B、47C可成為彼此不同的電位。在以下,不將佈線47A、47B、47C彼此區別的情況下,稱為「佈線47」。
第2層積體40的接合墊48包含連接於佈線47A的接合墊48A、連接於佈線47B的接合墊48B及連接於佈線47C的接合墊48C。於X方向及Y方向,在接合墊48A、48B、48C之間設有第2絕緣體45。接合墊48A、48B、48C可成為彼此不同的電位。在以下,不將接合墊48A、48B、48C彼此區別的情況下,稱為「接合墊48」。
在本實施方式,接合墊48A、48B、48C中的各者方面,與第1層積體30的接合墊38A、38B、38C同樣地,具有在X方向與Y方向之中的至少一者上彼此分離的複數個電極部82。在此處說明的一例,接合墊48A、48B、48C中的各者具有在X方向及Y方向中的各者上彼此分離的複數個電極部82。於X方向及Y方向,在複數個電極部82之間設有第2絕緣體45。換言之,在Z方向上觀看的情況下,於貼合面S在複數個電極部82之間設有第2絕緣體45。電極部82為「第2電極部」的一例。
複數個電極部82彼此獨立而分別連接於佈線47。亦即,含於相同的接合墊48中的複數個電極部82連接於相同的佈線47。含於相同的接合墊48中的複數個電極部82成為相同的電位。在示於圖3之例,含於接合墊48A中的複數個電極部82連接於佈線47A。含於接合墊48B中的複數個電極部82連接於佈線47B。含於接合墊48C中的複數個電極部82連接於佈線47C。
第1層積體30的接合墊38的複數個電極部81及第2層積體40的接合墊48的複數個電極部82在貼合面S彼此被接合。據此,第1層積體30的接合墊38與第2層積體40的接合墊48彼此被接合。在示於圖3之例,第1層積體30的接合墊38的複數個電極部81與第2層積體40的接合墊48的複數個電極部82彼此被以相同的態樣而設。「態樣相同」表示複數個電極部81、82的形狀為相同。此情況下,第1層積體30的接合墊38的複數個電極部81及第2層積體40的接合墊48的複數個電極部82以1對1的對應關係而彼此被接合。
在本實施方式,第1層積體30的接合墊38A的複數個電極部81與第2層積體40的接合墊48A的複數個電極部82彼此被接合,使得佈線37A與佈線47A被電連接。同樣地,第1層積體30的接合墊38B的複數個電極部81與第2層積體40的接合墊48B的複數個電極部82彼此被接合,使得佈線37B與佈線47B被電連接。第1層積體30的接合墊38C的複數個電極部81與第2層積體40的接合墊48C的複數個電極部82彼此被接合,使得佈線37C與佈線47C被電連接。
在本實施方式,接合墊38A、38B、38C、48A、48B、48C彼此具有相同的形狀。為此,在以下,就第1層積體30的1個接合墊38詳細進行說明。第2層積體40的接合墊48亦具有與在以下說明的構造相同的構造。
圖4為就接合墊38進行繪示的圖。圖4示出第1層積體30與第2層積體40被貼合前的狀態的接合墊38。在本實施方式,複數個電極部81例如包含在X方向及Y方向上分開的被配置為3×3的矩陣狀的9個電極部81。亦即,複數個電極部81包含在X方向上彼此被分離且被以等間隔而配置的複數個電極部81。同樣地,複數個電極部81包含在Y方向上彼此被分離且被以等間隔而配置的複數個電極部81。其中,電極部81的個數及配置不限定於上述例。
電極部81例如為沿X方向及Y方向的四角狀。在示於圖4之例,X方向上的電極部81的寬W1與在X方向上相鄰的2個電極部81之間的距離L1為相同。同樣地,Y方向上的電極部81的寬W2與在Y方向上相鄰的2個電極部81之間的距離L2為相同。相鄰的2個電極部81之間的距離L1、L2比相鄰的2個接合墊38之間的距離L3(圖3參照)小。
從Z方向觀看時,將沿著含於1個接合墊38中的複數個電極部81之中相對於接合墊38之中央部位於最外部的複數個電極部81A的邊緣而一體地包圍複數個電極部81的假想線IL的內側區域定義為「墊區域R」的情況下,墊區域R中的複數個電極部81的面積的合計比墊區域R中的第1絕緣體35的面積小。換言之,複數個電極部81被以相對大的間距彼此分離而配置。
在本實施方式,各電極部81具有電極主體91與連接部92。電極主體91曝露於貼合面S(圖3參照),接合於第2層積體40的接合墊48。連接部92位於電極主體91與佈線37之間,並將電極主體91與佈線37連接。連接部92比電極主體91細。例如,X方向上的連接部92的寬W4比X方向上的電極主體91的寬W3小。同樣地,Y方向上的連接部92的寬比Y方向上的電極主體91的寬小。各電極部81的電極主體91經由對應的連接部92而連接於佈線37。
在別的觀點下,各電極部81具有導電部主體95與屏障金屬層96。導電部主體95形成各電極部81的主部。屏障金屬層96於X方向及Y方向上設於導電部主體95與第1絕緣體35之間。屏障金屬層96為抑制含於導電部主體95中的導電材料(例如銅或鋁)擴散至第1絕緣體35的情形的金屬層。導電部主體95及屏障金屬層96中的各者設於電極主體91及連接部92雙方。
如示於圖4,各電極部81的端部E在第1層積體30與第2層積體40被貼合前的狀態下相對於第1絕緣體35的+Z方向側的表面35a而突出於+Z方向。各電極部81的端部E具有往-Z方向碗狀地凹陷的凹部RS。
以上,就第1層積體30的接合墊38進行了說明。第2層積體40的接合墊48方面,於上述說明,將「接合墊38」改讀為「接合墊48」、將「佈線37」改讀為「佈線47」、將「+Z方向」改讀為「-Z方向」、將「-Z方向」改讀為「+Z方向」即可。
圖5為就在第1層積體30與第2層積體40的貼合時之第1層積體30的電極部81及第2層積體40的電極部82的狀態進行繪示的剖面圖。在本實施方式,在將第1層積體30與第2層積體40予以貼合之際,第1層積體30及第2層積體40被加熱,同時第2層積體40被朝第1層積體30按壓。亦即,在第1層積體30的電極部81與第2層積體40的電極部82彼此抵接的狀態下,第2層積體40被朝第1層積體30按壓。
據此,第1層積體30的電極部81及第2層積體40的電極部82分別變形。亦即,第1層積體30的電極部81變形為不從第1絕緣體35的表面35a突出的狀態。再者,第1層積體30的電極部81的端部E的凹部RS被填埋而消失(或變小)。同樣地,第2層積體40的電極部82變形為不從第2絕緣體45的表面45a突出的狀態。再者,第2層積體40的電極部82的端部的凹部RS被填埋而消失(或變小)。
<3. 半導體記憶裝置之製造方法>
接著,就半導體記憶裝置1的製造方法進行說明。
圖6至圖9為就半導體記憶裝置1的製造方法進行繪示的剖面圖。
圖6示出電路晶片2的製造階段。電路晶片2被作為電路晶圓CW的一部分而製造。電路晶圓CW包含複數個電路晶片2。電路晶圓CW被透過在第1基板10上形成第1層積體30從而獲得。第1層積體30包含電晶體31、接觸插塞32、佈線33、墊34及第1絕緣體35。此等被按階層而形成。電路晶圓CW透過重複此等之各層的利用成膜、光刻等的加工從而被形成。接合墊38以外的成膜方法及加工方法可使用周知的方法。於電路晶圓CW的與第1基板10相反側的貼合面S1,複數個接合墊38曝露。據此,完成電路晶圓CW。
此處,就接合墊38的形成方法詳細進行說明。
圖7示出接合墊38的製造階段的細節。首先,如示於圖7中的(a),在佈線37上設置第1絕緣體35的一部分。設於佈線37上的第1絕緣體35例如由矽氧化物(SiO
2)形成。
接著,在第1絕緣體35上設置保護層101。保護層101被以與第1絕緣體35不同的材料而形成。保護層101例如由矽氮化物(SiN)形成。保護層101的厚度T1例如被設定為比因化學機械研磨的凹陷(dishing)而得之凹部RS的凹陷量K(圖7中的(c)參照)大。例如,保護層101的厚度T1(例如Z方向的厚度)比屏障金屬層96的厚度T2(例如X方向的厚度)大。
接著,如示於圖7中的(b),透過攝影雕刻法程序(Photo Engraving Process:PEP)形成抗蝕層圖案,透過反應性離子蝕刻(Reactive Ion Etching:RIE)蝕刻保護層101及第1絕緣體35。據此,在複數個電極部81被在後程序設置的位置形成複數個孔102。
接著,如示於圖7中的(c),在孔102的內面形成成為屏障金屬層96的基礎的導電層103a。之後,在孔102的內部嵌入導電材料(例如如銅或鋁的金屬材料)從而形成成為導電部主體95的基礎的導電部103b。據此,形成將孔102填埋的導電部103。導電部103為成為複數個電極部81的基礎的導電部。
接著,將保護層101作為停止層透過化學機械研磨(Chemical Mechanical. Polisher:CMP)進行導電部103的平坦化。CMP例如透過以檢測出保護層101的表面而使研磨結束的終點模式從而進行。據此,從導電部103形成複數個電極部81。此時,於各電極部81之上端部的表面,形成因凹陷(Dishing)而得之凹部RS。
接著,如示於圖7中的(d),保護層101被除去。保護層101為矽氮化物的情況下,保護層101的除去方面例如透過使用磷酸從而進行。據此,第1絕緣體35的表面35a曝露。第1絕緣體35的表面35a形成貼合於陣列晶片3的貼合面S1。係各電極部81之上端部的端部E從第1絕緣體35的表面35a(貼合面S1)朝上方突出。據此,完成接合墊38。
圖8示出陣列晶片3的製造階段。陣列晶片3被作為陣列晶圓AW的一部分而製造。陣列晶圓AW包含複數個陣列晶片3。示於圖8的陣列晶圓AW為將電路晶圓CW予以貼合前的狀態,且相對於示於圖1的陣列晶片3而上下反轉。
陣列晶圓AW透過在第2基板60上形成第2層積體40從而獲得。第2層積體40包含記憶體單元陣列41、接觸插塞42、佈線43、墊44及第2絕緣體45。此等被按階層而形成。陣列晶圓AW透過重複此等之各層的利用成膜、光刻等的加工從而被形成。接合墊48以外的成膜方法及加工方法可使用周知的方法。於陣列晶圓AW的與第2基板60相反側的貼合面S2,複數個接合墊48曝露。接合墊48的形成方法例如與參照圖7而說明的接合墊38的形成方法相同。據此,完成電路晶圓CW。
圖9示出電路晶圓CW與陣列晶圓AW的貼合階段。具體而言,將電路晶圓CW及陣列晶圓AW加熱,同時使電路晶圓CW的貼合面S1與陣列晶圓AW的貼合面S2相向(亦即,使第1層積體30的接合墊38與第2層積體40的接合墊48為相向)而透過機械壓力使電路晶圓CW與陣列晶圓AW貼合。據此第1絕緣體35與第2絕緣體45被黏合。
此時,如參照圖5上述般,電路晶圓CW的接合墊38與陣列晶圓AW的接合墊48方面,在接合墊38的電極部81的端部E從第1絕緣體35的表面35a突出且接合墊48的電極部82的端部E從第2絕緣體45的表面45a突出的狀態下,彼此抵接。並且,透過機械壓力,彼此抵接的接合墊38的電極部81及接合墊48的電極部82發生變形,在前程序因凹陷而形成於電極部81、82的凹部RS被填埋而消失(或變小)。
接著,陣列晶圓AW及電路晶圓CW被以400℃退火。據此接合墊38的電極部81與接合墊48的電極部82被接合。據此,形成電路晶圓CW與陣列晶圓AW被貼合的貼合體111。
接著,第2基板60被薄型化。第2基板60的薄型化例如透過CMP從而進行。接著,透過周知的方法,對於第2基板60設置外部連接墊71及絕緣層72、73。並且,貼合體111沿著未圖示的切割線被切斷。據此,貼合體111被分斷為複數個晶片(半導體記憶裝置1)。據此,獲得半導體記憶裝置1。
<4. 優點>
為供比較,思考有關接合墊由相對大的1個電極部構成的情況。在如此的比較例的構成,因CMP或別的理由於接合墊的端部產生大的凹陷時,有時在被貼合的2個接合墊之間殘留空間。此情況下,於2個接合墊的接合面形成空隙(Void)。此情況下,接合墊的電阻變高。
再者,此空隙有時因室溫導致的應力遷移而移動(凝聚)至接合墊與佈線的連接部。此情況下,接合墊與佈線之間有可能成為斷線狀態。在另一方面,為了更確實地接合2個接合墊,使退火溫度上升而增加熱脹時,含於屏障金屬層的金屬擴散至絕緣體的內部,基於屏障金屬層的屏障性可能降低。
在另一方面,在本實施方式,接合墊38包含在X方向上彼此分離並分別連接於佈線37的複數個電極部81。於複數個電極部81之間,設有第1絕緣體35。依如此的構成時,接合墊38分為複數個小的電極部81,故難以在各電極部81產生大的凹陷,凹部RS的凹陷量K變小。為此,在被貼合的2個接合墊38、48之間不易殘留空間,在2個接合墊的接合面變得不易產生空隙。其結果,接合墊38、48的電阻不易變高。據此,可謀求半導體記憶裝置1的電氣特性的提升。
此外在本實施方式,複數個電極部81彼此獨立而分別連接於佈線37。依如此的構成時,可將作用於接合墊38的應力以複數個電極部81予以分散。據此,可使應力遷移導致的斷線的機率減少。
在本實施方式,在半導體記憶裝置1的製造時,在第1絕緣體35上設置保護層101。之後,使保護層101為停止層而進行化學機械研磨從而形成複數個電極部81。之後,保護層101被除去。據此,使複數個電極部81的端部E從第1絕緣體35突出。並且,複數個電極部81的端部E從第1絕緣體35突出的狀態下,可使接合墊38的複數個電極部81抵接於接合墊48。依如此的構成時,2個接合墊38、48在電極部81的端部E從第1絕緣體35突出的狀態下被接合,故由於從第1絕緣體35突出的電極部81的端部E使得因凹陷而形成的凹部RS被填埋。為此,在被貼合的2個接合墊38、48之間不易殘留空間,在2個接合墊38、48的接合面不易產生空隙。據此,可謀求半導體記憶裝置1的電氣特性的提升。
再者,使保護層101為停止層而進行化學機械研磨的情況下,比起未設置保護層101的情況,在相對於第1絕緣體35的表面35a高的位置形成因凹陷而得的凹部RS。亦即,形成凹陷的界面被提高的狀態下形成複數個電極部81。為此,以第1絕緣體35的表面35a為基準觀看的情況下,在電極部81難以產生大的凹陷,凹部RS的凹陷量K變小。基於如此的理由,亦在被貼合的2個接合墊38、48之間難以殘留空間,難以在2個接合墊38、48的接合面產生空隙。據此,可謀求半導體記憶裝置1的電氣特性的提升。
在本實施方式,從Z方向觀看時,將沿著複數個電極部81之中相對於接合墊38之中央部位於最外部的複數個電極部81A的邊緣而一體地包圍複數個電極部81的區域定義為墊區域R的情況下,墊區域R中的複數個電極部81的面積的合計比墊區域R中的第1絕緣體35的面積小。依如此的構成時,接合墊38分為複數個更小的電極部81,故在各電極部81難以進一步產生大的凹陷。據此,可謀求半導體記憶裝置1的電氣特性的提升。
在本實施方式,複數個電極部81包含在X方向上分離的複數個電極部81與在Y方向上分離的複數個電極部81。依如此的構成時,接合墊38在複數個方向上分為小的電極部81,故在各電極部81難以進一步產生大的凹陷。據此,可謀求半導體記憶裝置1的電氣特性的提升。
在本實施方式,複數個電極部81中的各者具有電極主體91與位於電極主體91與佈線37之間的連接部92。X方向上的連接部92的寬W4比X方向上的電極主體91的寬W3小。依如此的構成時,即使為連接部92變細使得容易發生應力遷移導致的斷線的構成,複數個電極部81彼此獨立而分別連接於佈線37,故仍可使應力遷移導致的斷線的機率減少。
<5. 變形例>
以下,就變形例進行說明。本變形例中在以下說明的以外的構成與上述的實施方式的構成相同。
圖10為就變形例的半導體記憶裝置1進行繪示的剖面圖。圖11為將由示於圖10的F11線包圍的區域放大而顯示的剖面圖。在本變形例,X方向上的第1層積體30的接合墊38的各電極部81的寬W1A比X方向上的第2層積體40的接合墊48的相鄰的2個電極部82之間的距離L1B大。同樣地,X方向上的第2層積體40的接合墊48的各電極部82的寬W1B比X方向上的第1層積體30的接合墊38的相鄰的2個電極部81之間的距離L1A大。此在Y方向上亦同。
在本變形例,即使在第2層積體40的接合墊48相對於第1層積體30的接合墊38偏位的情況下,接合墊38的電極部81的一部分與接合墊48的電極部82的一部分在Z方向上確實地相向,接合墊38的電極部81與接合墊48的電極部82被確實地連接。據此,可謀求半導體記憶裝置1的電氣特性的提升。
<6. 實施例>
以下,說明關於接合墊38、48的電極部81、82的形狀的若干實施例。在以下,以第1層積體30的接合墊38的電極部81的形狀為代表進行說明。第2層積體40的接合墊48的電極部82的形狀亦同。另外,電極部81、82的形狀不限定於在以下說明的實施例的內容。
<6.1 第1實施例>
圖12為就第1實施例的複數個電極部81的形狀進行繪示的剖面圖。在第1實施例,複數個電極部81被在X方向及Y方向上分別分離的矩陣狀地配置。在示於圖12之例,設有8×8的64個電極部81。
<6.2 第2實施例>
圖13為就第2實施例的複數個電極部81的形狀進行繪示的剖面圖。在第2實施例,接合墊38包含框部121、複數個第1直線部122及複數個第2直線部123。複數個第1直線部122及複數個第2直線部123設於框部121的內側。複數個第1直線部122在X方向上彼此分離,並分別延伸於Y方向。X方向上,在複數個第1直線部122之間,設有第1絕緣體35。在另一方面,複數個第2直線部123在Y方向彼此分離並分別延伸於X方向。Y方向上,在複數個第2直線部123之間,設有第1絕緣體35。複數個第1直線部122與複數個第2直線部123彼此交叉。
在本實施例,由複數個第1直線部122形成在X方向彼此分離的複數個電極部81。同樣地,由複數個第2直線部123形成在Y方向上彼此分離的複數個電極部81。在本說明書中「彼此分離」不限定於如第1實施例般完全獨立的情況,亦包含經由別的部分(例如框部121)而彼此連接的情況。
在第2實施例,第1直線部122在該第1直線部122的延伸方向(Y方向)上具有遍及(跨)複數個第2直線部123之中至少2個以上的第2直線部123的長度。依如此的構成時,即使在接合墊38與接合墊48之間發生Y方向的偏位的情況下,接合墊38與接合墊48仍可被更確實地連接。同樣地,第2直線部123在該第2直線部123的延伸方向(X方向)上具有遍及(跨)複數個第1直線部122之中至少2個以上的第1直線部122的長度。依如此的構成時,即使在接合墊38與接合墊48之間發生X方向的偏位的情況下,接合墊38與接合墊48仍可被更確實地連接。
<6.3 第3實施例>
圖14為就第3實施例的複數個電極部81的形狀進行繪示的剖面圖。在第3實施例,接合墊38包含複數個直線部131。複數個直線部131在Y方向彼此分離,並分別延伸於X方向。Y方向上,在複數個直線部131之間,設有第1絕緣體35。在本實施例,由複數個直線部131形成在Y方向上彼此分離的複數個電極部81。依如此的構成時,即使在接合墊38與接合墊48之間發生X方向的偏位的情況下,接合墊38與接合墊48仍容易被更確實地連接。
<6.4 第4實施例>
圖15為就第4實施例的複數個電極部81的形狀進行繪示的剖面圖。在第3實施例,接合墊38包含複數個直線部141。複數個直線部141在X方向彼此分離,並分別延伸於Y方向。X方向上,在複數個直線部141之間,設有第1絕緣體35。在本實施例,由複數個直線部141形成在X方向上彼此分離的複數個電極部81。依如此的構成時,即使在接合墊38與接合墊48之間發生Y方向的偏位的情況下,接合墊38與接合墊48仍可容易被更確實地連接。
<6.5 第5實施例>
圖16為就第5實施例的複數個電極部81的形狀進行繪示的剖面圖。在第5實施例,接合墊38包含框部151及複數個直線部152。複數個直線部152設於框部151的內側。複數個直線部152在Y方向彼此分離,並分別延伸於X方向。Y方向上,在複數個直線部152之間,設有第1絕緣體35。在本實施例,由複數個直線部152形成在Y方向上彼此分離的複數個電極部81。
<6.6 第6實施例>
圖17為就第6實施例的複數個電極部81的形狀進行繪示的剖面圖。在第6實施例,接合墊38包含框部161及複數個直線部162。複數個直線部162設於框部161的內側。複數個直線部162在X方向彼此分離,並分別延伸於Y方向。X方向上,在複數個直線部162之間,設有第1絕緣體35。在本實施例,由複數個直線部162形成在X方向上彼此分離的複數個電極部81。
<6.7 第7實施例>
圖18為就第7實施例的複數個電極部81的形狀進行繪示的剖面圖。在第7實施例,接合墊38包含複數個框部171。複數個框部171為彼此大小不同的相似形的環狀,並被同心狀地配置。於X方向及Y方向,在複數個框部171之間設有第1絕緣體35。在本實施例,由複數個框部171分別形成環狀的複數個電極部81。從別的觀點觀之,由含於複數個框部171的沿著Y方向的線狀部171a形成在X方向上彼此分離的複數個電極部81。同樣地,由含於複數個框部171的沿著X方向的線狀部171b形成在Y方向上彼此分離的複數個電極部81。接合墊38包含延伸於Y方向的部分與延伸於X方向的部分雙方時,即使在接合墊38與接合墊48之間發生X方向及Y方向中的任一個方向上的偏位的情況下,接合墊38與接合墊48仍容易被更確實地連接。
<6.8 第8實施例>
圖19為就第8實施例的複數個電極部81、82的形狀進行繪示的剖面圖。圖19中的(a)示出第1層積體30的接合墊38的複數個電極部81。圖19中的(b)示出第2層積體40的接合墊48的複數個電極部82。
在本實施例,第1層積體30的接合墊38的複數個電極部81被以第1態樣而設。本實施例的第1態樣例如為與第3實施例(圖14)相同的態樣。在另一方面,第2層積體40的接合墊48的複數個電極部82被以與上述第1態樣不同的第2態樣而設。「態樣不同」表示複數個電極部81、82的形狀不同。本實施例的第2態樣例如為與第4實施例(圖15)相同的態樣。
圖19中的(c)示出接合墊38的複數個電極部81與接合墊48的複數個電極部82被重疊(貼合)的狀態。在示於圖19之例,接合墊38的複數個電極部81彼此分離的方向(Y方向)與接合墊48的複數個電極部82彼此分離的方向(X方向)不同。
接合墊38的各電極部81的至少一部分在接合墊48的複數個電極部82彼此分離的方向(X方向)上遍及(跨)2個以上的電極部82的直線狀地延伸。在另一方面,接合墊48的各電極部82的至少一部分在接合墊38的複數個電極部81彼此分離的方向(Y方向)上遍及(跨)2個以上的電極部81的直線狀地延伸。依如此的構成時,即使在接合墊38與接合墊48之間在X方向及Y方向的任一個方向上發生偏位的情況下,接合墊38與接合墊48仍被更確實地連接。
<6.9 第9實施例>
圖20為就第9實施例的複數個電極部81、82的形狀進行繪示的剖面圖。圖20中的(a)示出第1層積體30的接合墊38的複數個電極部81。圖20中的(b)示出第2層積體40的接合墊48的複數個電極部82。
在本實施例,第1層積體30的接合墊38的複數個電極部81被以第1態樣而設。本實施例的第1態樣例如為與第1實施例(圖12)相同的態樣。在另一方面,第2層積體40的接合墊48的複數個電極部82被以與上述第1態樣不同的第2態樣而設。本實施例的第2態樣例如為與第7實施例(圖18)相同的態樣。
圖20中的(c)示出接合墊38的複數個電極部81與接合墊48的複數個電極部82被重疊(貼合)的狀態。在示於圖20之例,接合墊38的複數個電極部81在X方向及Y方向上彼此分離。在另一方面,接合墊48的各電極部82的至少一部分(例如線狀部171b)在接合墊38的複數個電極部81彼此分離的方向(X方向)上遍及(跨)2個以上的電極部81的直線狀地延伸。接合墊48的各電極部82的至少一部分(例如線狀部171a)在接合墊38的複數個電極部81彼此分離的方向(Y方向)上遍及(跨)2個以上的電極部81的直線狀地延伸。依如此的構成時,即使在接合墊38與接合墊48之間在X方向及Y方向的任一個方向上發生偏位的情況下,接合墊38與接合墊48仍可被更確實地連接。
以上,就實施方式、變形例及若干實施例進行了說明。其中,實施方式、變形例、實施例不限定於上述之例。例如,上述第1至第7實施例之中任意一個實施例的接合墊38的電極部81與上述第1至第7的實施例之中任意別的一個實施例的接合墊48的電極部82被接合亦可。於上述的全部的說明,接合墊38及接合墊48的形狀亦可為相反。在上述的實施方式,接合墊38分為複數個電極部81,同時接合墊48分為複數個電極部82。代替地,亦可為接合墊38分為複數個電極部81,同時接合墊48為1個大的墊,亦可為接合墊48分為複數個電極部82,同時接合墊38為1個大的墊。
依以上說明的至少一個實施方式時,半導體記憶裝置具有第1層積體與第2層積體。第1層積體包含第1佈線、連接於第1佈線的第1墊及第1絕緣體。第2層積體包含第2佈線、連接於第2佈線的第2墊及第2絕緣體。第1墊包含彼此分離且分別連接於第1佈線的複數個第1電極部。於複數個第1電極部之間,設有第1絕緣體。複數個第1電極部接合於第2墊。依如此的構成時,提供可謀求電氣特性的提升的半導體記憶裝置及半導體記憶裝置之製造方法。
雖就本發明之數個實施方式進行說明,惟此等實施方式是作為例示而提示者,並未意圖限定發明之範圍。此等實施方式能以其他各種方式實施,在不脫離發明之要旨的範圍下,可進行各種的省略、置換、變更。此等實施方式、其變形如同包含於發明之範圍、要旨,亦包含於申請專利範圍之發明與其均等之範圍。
1:半導體記憶裝置
10:第1基板
30:第1層積體
35:第1絕緣體
37:佈線(第1佈線)
38:接合墊(第1墊)
40:第2層積體
45:第2絕緣體
47:佈線(第2佈線)
48:接合墊(第2墊)
81:電極部(第1電極部)
82:電極部(第2電極部)
101:保護層
R:墊區域
[圖1]就實施方式的半導體記憶裝置的構成進行繪示的剖面圖。
[圖2]就實施方式的記憶體單元陣列的記憶體柱的附近進行繪示的剖面圖。
[圖3]就實施方式的複數個接合墊進行繪示的剖面圖。
[圖4]就實施方式的接合墊進行繪示的圖。
[圖5]就實施方式的將第1層積體與第2層積體的貼合時的第1層積體的電極部及第2層積體的電極部的狀態進行繪示的剖面圖。
[圖6]就實施方式的半導體記憶裝置之製造方法進行繪示的剖面圖。
[圖7]就實施方式的半導體記憶裝置之製造方法進行繪示的剖面圖。
[圖8]就實施方式的半導體記憶裝置之製造方法進行繪示的剖面圖。
[圖9]就實施方式的半導體記憶裝置之製造方法進行繪示的剖面圖。
[圖10]就實施方式的變形例的半導體記憶裝置進行繪示的剖面圖。
[圖11]將由示於圖10的F11線包圍的區域放大而顯示的剖面圖。
[圖12]就實施方式的第1實施例的複數個電極部的形狀進行繪示的剖面圖。
[圖13]就實施方式的第2實施例的複數個電極部的形狀進行繪示的剖面圖。
[圖14]就實施方式的第3實施例的複數個電極部的形狀進行繪示的剖面圖。
[圖15]就實施方式的第4實施例的複數個電極部的形狀進行繪示的剖面圖。
[圖16]就實施方式的第5實施例的複數個電極部的形狀進行繪示的剖面圖。
[圖17]就實施方式的第6實施例的複數個電極部的形狀進行繪示的剖面圖。
[圖18]就實施方式的第7實施例的複數個電極部的形狀進行繪示的剖面圖。
[圖19]就實施方式的第8實施例的複數個電極部的形狀進行繪示的剖面圖。
[圖20]就實施方式的第9實施例的複數個電極部的形狀進行繪示的剖面圖。
30:第1層積體
35:第1絕緣體
37:佈線(第1佈線)
38:接合墊(第1墊)
40:第2層積體
45:第2絕緣體
47:佈線(第2佈線)
48:接合墊(第2墊)
81:電極部(第1電極部)
82:電極部(第2電極部)
37A,37B,37C,47A,47B,47C:佈線
38A,38B,38C,48A,48B,48C:接合墊
Claims (10)
- 一種半導體記憶裝置,其具備: 第1基板; 第2基板,其在為前述第1基板的厚度方向的第1方向上從前述第1基板分離; 第1層積體,其設於前述第1基板與前述第2基板之間,並包含第1佈線、連接於前述第1佈線的第1墊及第1絕緣體;以及 第2層積體,其設於前述第1層積體與前述第2基板之間,並包含第2佈線、連接於前述第2佈線的第2墊及第2絕緣體; 前述第1墊包含在與前述第1方向交叉的第2方向彼此分離並分別連接於前述第1佈線的複數個第1電極部, 於前述複數個第1電極部之間,設有前述第1絕緣體, 前述複數個第1電極部接合於前述第2墊。
- 如請求項1的半導體記憶裝置,其中, 前述第2墊包含在前述第2方向或在與前述第1方向及前述第2方向交叉的第3方向上彼此分離並分別連接於前述第2佈線的複數個第2電極部, 於前述複數個第2電極部之間,設有前述第2絕緣體, 前述複數個第2電極部接合於前述複數個第1電極部。
- 如請求項2的半導體記憶裝置,其中,從前述第1方向觀看時,將沿著前述複數個第1電極部之中相對於前述第1墊之中央部位於最外部的複數個電極部的邊緣而一體地包圍前述複數個第1電極部的區域定義為墊區域的情況下,在前述墊區域之前述複數個第1電極部的面積的合計比在前述墊區域之前述第1絕緣體的面積小。
- 如請求項3的半導體記憶裝置,其中,前述複數個第1電極部中的各者包含接合於前述第2墊的電極主體及位前述電極主體與前述第1佈線之間而將前述電極主體與前述第1佈線連接且前述第2方向的寬比前述電極主體小的連接部。
- 如請求項1~4中任一項的半導體記憶裝置,其中,前述複數個第1電極部包含在前述第2方向上分離的複數個電極部及在與前述第1方向及前述第2方向不同的第3方向上分離的複數個電極部。
- 如請求項1~4中任一項的半導體記憶裝置,其中, 前述複數個第1電極部包含在前述第2方向上分離的複數個電極部, 前述複數個電極部中的各者直線狀地延伸於與前述第1方向及前述第2方向不同的第3方向。
- 如請求項1~4中任一項的半導體記憶裝置,其中,前述複數個第1電極部包含為同心狀的環狀的複數個電極部。
- 如請求項2的半導體記憶裝置,其中, 前述複數個第1電極部包含以第1態樣分離的複數個電極部, 前述複數個第2電極部包含以與前述第1態樣不同的第2態樣分離的複數個電極部。
- 一種半導體記憶裝置之製造方法, 在第1基板上形成包含第1佈線、連接於前述第1佈線的第1墊及第1絕緣體的第1層積體,前述第1墊包含在與為前述第1基板的厚度方向的第1方向交叉的第2方向上彼此分離並分別連接於前述第1佈線的複數個第1電極部,在前述複數個第1電極部之間設有前述第1絕緣體, 在第2基板上形成包含第2佈線、連接於前述第2佈線的第2墊及第2絕緣體的第2層積體, 使前述第1墊與前述第2墊相向而將前述第1層積體與前述第2層積體予以貼合,將前述複數個第1電極部與前述第2墊接合。
- 如請求項9的半導體記憶裝置之製造方法,其中, 形成前述第1層積體的程序包含: 在前述第1佈線上設置前述第1絕緣體; 在前述第1絕緣體上設置保護層; 在前述第1絕緣體及前述保護層形成複數個孔; 形成填埋前述複數個孔的導電部,使前述保護層為停止層而進行化學機械研磨,從而從前述導電部形成前述複數個第1電極部;以及 除去前述保護層,從而使前述複數個第1電極部的端部從前述第1絕緣體突出; 將前述第1層積體與前述第2層積體予以貼合的程序包含: 在前述複數個第1電極部的端部從前述第1絕緣體突出的狀態下使前述複數個第1電極部抵接於前述第2墊。
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