TWI713195B - 三維ｎｏｒ記憶電路製程中之晶圓接合及其形成之積體電路 - Google Patents

三維ｎｏｒ記憶電路製程中之晶圓接合及其形成之積體電路 Download PDF

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TWI713195B
TWI713195B TW108133758A TW108133758A TWI713195B TW I713195 B TWI713195 B TW I713195B TW 108133758 A TW108133758 A TW 108133758A TW 108133758 A TW108133758 A TW 108133758A TW I713195 B TWI713195 B TW I713195B
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connection layer
memory
wafer bonding
integrated circuit
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伊萊 哈拉利
史考特布萊德 海納
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美商森恩萊斯記憶體公司
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Abstract

利用如黏合與陽極接合等的晶圓接合技術，提供在同一積體電路中由一連接層之導體所連接的一記憶體陣列與單晶電路。可以利用晶圓接合加上額外的電路或記憶體陣列，其電性連接到在晶圓接合介面上的連接層。該記憶體陣列可包含存儲或記憶體電晶體，其具有單晶磊晶矽通道材料。

Description

三維NOR記憶電路製程中之晶圓接合及其形成之積體電路
本發明係關於在積體電路製程中的晶圓接合技術，特別係關於高密度三維記憶體電路的晶圓接合技術。
以下敘述與本發明相關的專利申請案件：本發明主張於2018年9月24日提出申請之美國臨時專利申請案(後稱第一臨時申請案)62/735,678號「三維NOR記憶體電路製程中之晶圓接合」的優先權。
本發明也與於2018年6月19日提出申請之美國專利申請案(後稱共同在審申請案)16/012,731號有關，其專利名稱為「三維NOR記憶體陣列架構與其製造方法」。本發明也與同日提出申請之美國臨時專利申請案(後稱第二臨時申請案)63/735,622號有關，其專利名稱為「在三維記憶體結構中之存儲電晶體的磊晶單晶體通道與其形成方法」。前述共同在審申請案及前述第一、第二臨時申請案，其內容整體係併入本申請案中做為參考。
晶圓接合是許多半導體裝置製造時所使用的技術。晶圓接合技術用於連接兩個相同或接近相同面積的晶圓。舉例來說，可以用熱壓 (thermocompression)、黏合(adhensive)、陽極(anodic)接合或是熱(thermal)接合技術。一般來說，在晶圓接合之後，全部或實質地消除了一或兩片晶圓的基板。
前述共同在審申請案揭露了三維記憶體結構，其形成在單晶半導體基板上，包含了NOR(反或閘)記憶體串(string)的陣列。在本申請當中，「NOR記憶體串」指的是一群薄膜存儲電晶體，其共用源極與汲極區域。圖1顯示了記憶體結構30的剖面，包含了上述NOR記憶體串的陣列，其形成在半導體基板上的CMOS(互補式金屬氧化物半導體)電路與連接層之上。如圖1所示，記憶體結構30形成在基板150之上。舉例來說，可以使用本領域普通技術人員已知用於製作電子電路的半導體晶圓作為適合的基板。也可以採用非半導體基板，如二氧化矽。
可以在半導體基板150的上方或中間製作各式電路元件(如圖1所示的CMOS電晶體所表示的CMOS電路10)，其經由傳統連接層的導體22(例如銅)透過接觸或穿孔16互相連接。在形成記憶體結構30之前，先使用傳統的技術將這些電路元件製作在半導體基板之上。在此統稱為連接層20的電路通常會嵌入在一絕緣層當中，可以包含導體用來支持記憶體結構30當中之記憶體陣列的運作。記憶體結構30會形成於連接層20之上。舉例來說，連接層20提供導體24(全域字線global word lines)來連接在記憶體結構30中各存儲電晶體定址用的導體32(例如重參雜多晶矽heavily-doped polysilicon)。在本說明中稱導體32為局部字線(local word line)。
如圖1所示，記憶體結構30包含多個主動條帶(active strip)的堆疊(如主動堆疊101a、101b與101c)。舉例來說，圖1顯示了三個主動堆疊 101a、101b與101c，每一個主動堆疊包含了四個主動條帶，主動堆疊之間藉由絕緣層107互相絕緣。圖1顯示主動條帶的剖面，它會向剖面的上下延伸。在本發明當中，一主動條帶包含汲極層104、源極層103、基極(body)層102與通道層108。(藉由基極層102的兩端來提供通道層108)。在某些實作當中，汲極層104與源極層103兩者均為n+多晶矽，而通道層108為p-多晶矽，基極層102為p+多晶矽。在某些實作當中，可以使用一絕緣層來替代基極層102。如圖1所示的主動條帶還包含導體層105t與105b，其分別相鄰於源極層103和汲極層104，用於減少沿著源極層103和汲極層104長度方向的電阻。沿著主動條帶的主動堆疊的每一邊(也就是每個主動條帶的每邊)，具有一電荷捕捉(charge-trapping)層107與多條局部字線32。在圖1當中，局部字線32是沿著一主動條帶之堆疊兩側的導電欄。可以藉由一局部字線、一部分的通道層108、部分的電荷捕捉層107之間的結構，以及源極層103和汲極層104來形成一存儲電晶體。沿著一主動條帶所組成的多個存儲電晶體分享共同的汲極層104和源極層103。沿著一主動條帶而共用源極和汲極層的相鄰存儲電晶體形成一NOR記憶體串。(開啟在該NOR記憶體串當中的任何存儲電晶體將導致在共同的源極層和汲極層之間形成一股導通的電晶體電流。)
製程的順序對CMOS裝置、連接層與記憶體裝置造成限制。舉例來說，因為需要利用低壓化學氣相沉積(LPCVD)形成ONO(oxide-nitride-oxide氧化層-氮矽化合物-氧化層)多層結構或堆疊，記憶體裝置通常需要在製程當中使用數個小時達至少攝氏750度的熱積存(thermal budget)。在ONO多層結構當中，所需的氧化層與氮矽化合物層可以分別是高溫氧化物(HTO；或二氧化矽)與氮化矽(SiN)。此外，還可能需要 一層氧化鋁(Al2O3)作為ONO堆疊中的阻擋氧化物(blocking oxide)。然而，從電氣性質來看，產生晶體化的氧化鋁(Al2O3)至少需要攝氏九百度以上的退火(anneal)溫度。然而，超過攝氏350度的製造溫度將使得銅無法嵌入在低介電常數絕緣薄膜中的絕緣層水平連接層20內，甚至是當鎢用在垂直連接的穿孔16當中以連接銅水平連接層時也一樣。類似地，超過攝氏500度的製造溫度將排除使用鋁連接層的可能。當製造溫度超過攝氏500時，鎢可以是連接層材料的選項之一。然而，鎢具有較高的電阻，如底下的表1所示。在連接層的電阻升高意味著信號的延遲，此特性將嚴重地影響記憶體裝置的性能表現。
Figure 108133758-A0305-02-0006-1
記憶體裝置的熱積存過程至少在兩個方面限制了底下的COMS電路(例如CMOS電晶體10)。首先，必須選用矽化鈷或其他高溫接觸材料，例如鎢或矽化鎢作為CMOS電晶體10當中的閘極、源極/汲極的金屬化材料12，據此，能夠讓製造溫度的最高值提高到攝氏750度。雖然和矽相比，矽化鈷具有相對較低的薄板和接觸電阻值，但因為在矽化步驟中需要消耗較多的矽，以及在矽化鈷與矽之間介面粗糙度之故，需要在矽材料當中採用較深的參雜節點。相反地，短通道長度的電晶體需要較淺的參雜節點，以便減少漏電流。雖然矽化鎳通常被用在小型電晶體的源極與汲極接 觸點上以產生電流，但由於矽化鎳無法承受攝氏450度以上的溫度，所以優選矽化鈷，而不選矽化鎳。在超過攝氏450度以上時，一層矽化鎳薄膜會凝聚在矽表面上，使得矽化鎳薄膜原有的低薄板阻抗與低接觸阻抗的特性消失。
再者，對於淺節點與窄通道裝置而言，在節點形成之後，必須避免溫度升高到攝氏600度以上，以避免在源極與汲極間節點的參雜擴散。
據此，亟需一種製造方法，其可以讓CMOS裝置與連接層和三維NOR記憶體結構(例如圖1所示的記憶體結構30)最佳地整合在一起，而不會因為記憶體的熱積存來限制CMOS裝置與連接層的設計選項。
根據本發明的一實施例，利用如黏合與陽極接合等的晶圓接合技術，提供在同一積體電路中由一連接層之導體所連接的一記憶體陣列與單晶電路。
可以利用晶圓接合加上額外的電路或記憶體陣列，其電性連接到在晶圓接合介面上的連接層。
根據本發明的一實施例，該記憶體陣列可包含存儲或記憶體電晶體，其具有單晶磊晶矽通道材料。
通過考慮下列的詳細說明與所附圖示，可以更佳地理解本發明。
10:CMOS電路或電晶體
12:金屬化材料
16:穿孔
20:連接層
22:導體
24:全域字線或導體
30:記憶體結構
32:局部字線或導體
40:連接層
100:基板
101a、101b、101c:主動堆疊
102:基極層
103:源極層
104:汲極層
105b、105c:導體層
107:絕緣層
108:通道層
110:基板
120:絕緣氧化物
130:基板
140:記憶體陣列
150:連接層
200:基板
210:CMOS電晶體
220:連接層
260:基板
270:二氧化矽層
280:矽層
290:CMOS電晶體
300:基板
310:記憶體區塊
350:基板
360:記憶體區塊
370:連接層
400:基板
402:表面
420:源極與汲極層
430:磊晶矽
440:磊晶矽通道
450:基板
810:記憶體區塊
圖1顯示了記憶體結構30的剖面，該記憶體結構包含了NOR記憶體串的陣列，其形成在半導體基板上的CMOS電路與連接層之上。
圖2A顯示CMOS裝置與連接層所放置的一半導體基板100，其用於支持製造的三維NOR記憶體結構。
圖2B顯示一三維NOR記憶體結構(亦即記憶體結構30)，其單獨地製造在半導體基板110的一絕緣氧化物(如二氧化矽)層120之上。
圖3A顯示將要進行晶圓接合的兩個裝置A’與B’，其分別在晶圓基板A與B上製造。
圖3B顯示裝置A’與B’已經完美地對齊，且在晶圓接合後兩者電性連接。
圖3C顯示在晶圓接合後電性連接的裝置A’與B’，其具有250奈米寬的誤差。
圖3D顯示使用黏合金屬C來促進基板A與B在裝置A’與B’的接合(亦即在互相接觸點進行接合)。
圖4顯示在如圖2A與2B的實施例當中，記憶體結構30的基板110可以被消除。
圖5顯示在記憶體結構30之上形成連接層40。
圖6A、6B、6C、6D、6E、6F顯示使用晶圓接合技術來製作CuA和CoA電路的步驟流程。
圖7A、7B、7C描繪利用基板300與350來進行晶圓接合記憶體區塊310與360。
圖8A、8B、8C、8D、8E描繪根據本發明一實施例的一製程，其CuA型態的CMOS電晶體被放置在一記憶體區塊之下，該記憶體區塊的單元中具有磊晶單晶矽通道。
為了讓圖示更加清楚以及能在圖示之間互相交互參考，圖示當中類似的元件被賦予相似的符號。
根據本發明的一實施例，並不把CMOS裝置(如CMOS電晶體10)和連接層(如連接層20)做在記憶體結構30的同一矽基板上，上述的CMOS裝置與連接層是製作在一獨立的半導體基板上。圖2A顯示CMOS裝置100與連接層20所放置的一半導體基板100，用於支持製造的三維NOR記憶體結構。該三維NOR記憶體結構(即記憶體結構30)係獨立地製作在基板110上的一絕緣氧化物(例如二氧化矽)層120之上，如圖2B所示。如本領域的普通技術人員所知，基板100與110可以是矽晶圓。
當在兩個基板100與110上所需的製作步驟已經執行後，可以利用覆晶(flip chip)技術把晶圓接合在一起，其中具有連接層20的該半導體基板100的表面被接合到具有半導體結構30的半導體基板110的表面。以這種方式，連接層20與CMOS裝置10的製程將不會受限於製作記憶體結構30所需的較高溫度。
晶圓結合的方式是連接層20的接觸點電性連接到記憶體結構30的相應接觸點。在每一個基板上的相對應光蝕刻對位符號使得接合點能夠以最小的誤差進行對齊。圖3A-3D示出基板A與基板B在指定的晶圓接合點進行晶圓接合。圖3A顯示分別在晶圓A與B上製作的兩個裝置A’與B’，用於稍後的晶圓接合製程。裝置A’與B’可以例如是一互聯系統中的300奈米(nm)寬的導體。圖3B顯示裝置A’與B’已經完美地對準並且在晶圓接合後電性連接。圖3C顯示裝置A’與B’在晶圓接合之後電性連接，但有250奈米寬的誤差。(現代晶圓接合技術可以達成對齊準確度在正負250奈米內。)可以利用任何適合的晶圓接合技術來接合基板A與B，諸如熱壓、陽極接合、電漿 活化(plasma activated)接合、共晶(eutectic)接合或是表面活化(surface activated)晶圓接合技術。在上述的技術當中，優選的是陽極接合。利用陽極接合技術，施加電場在互相接觸的兩片晶圓基板，使得此裝置得以物理與電性連接。
根據本發明一實施例，如圖3D所示，黏合金屬C可以特別用來在它們的接觸點(亦即裝置A’與B’)接合晶圓A與B。黏合金屬C可以是鉻、鈦、銦或其合金、或任何適合的材料。本領域普通技術人員可以理解到晶圓接合的要件與機制，因此在本說明中略過細節的討論。
在接合之後，可以消除一個基板。圖4顯示在如圖2A與2B的實施例當中，記憶體結構30的基板110可以被消除。可以使用任何適用的晶圓薄化(wafer thinning)技術來消除基板110，例如雷射剝離(laser lift-off)、機械拋光(mechanical polishing)、或是化學蝕刻。在一實施例中，相較於單獨使用機械拋光和化學蝕刻，混合利用這兩種技術可以用較便宜且較精準的方式來消除基板110(亦即不會損害記憶體結構30)。例如，假設基板110的厚度是500微米。接著，可以先使用機械拋光來削除480微米厚的基板，接著讓化學蝕刻來移除剩下來的20微米厚基板110。
在機械拋光的晶圓薄化技術當中，晶圓會圍繞其中心在一磨面上旋轉。當磨完的表面是粗糙時，透過機械力來薄化晶圓有時候稱之為研磨(grinding)，當磨完的表面是光滑時，稱之為拋光(polishing)。可以使用研磨或拋光兩者之一或其組合來進行晶圓薄化。當完成機械研磨或拋光步驟之後，化學蝕刻可以用來消除記憶體結構30所剩的20微米。
對於基板110的化學蝕刻可以使用任何適合的化學藥品。適 合矽基板的化學蝕刻藥劑如氫氧化鉀(potassium hydroxide)、氫氧化四甲銨(TMAH,Tetramethylammonium)、氫氟酸(HF+)、硝酸(HNO3)、或氫氟酸與氟化銨(NH4F)。在矽基板110與記憶體結構之間的一氧化層可以作為蝕刻阻擋層。如圖4所示，蝕刻阻擋層120確保記憶體結構不變，不會受損於基板110的化學蝕刻。當該氧化層(例如二氧化矽)作為蝕刻阻擋層時，可以用氫氧化鉀(KOH)來蝕刻矽，因為它侵蝕矽的速度比侵蝕二氧化矽的速度快五百倍。因此二氧化矽層可以做為矽蝕刻的有效蝕刻阻擋層。
當基板110被消除之後，可以對接合後的晶圓做進一步的製造。例如，圖5顯示在記憶體結構30之上形成連接層40。當記憶體結構30的形成和連接層40的形成無關時，可以選用鋁或銅做為連接層40。這樣的連接層可以在較低的溫度形成(例如攝氏450度或更低)。
根據本發明另一實施例，晶圓接合可以用來在記憶體陣列下製造單晶電晶體，其稱之為陣列下的CMOS(CuA,CMOS under the Array)以及陣列上的CMOS(CoA,CMOS over the Array)。圖6A~6F顯示使用晶圓接合技術來製作CuA和CoA電路的步驟流程。
如圖6A所示，在基板200之上製作CMOS電晶體210，而記憶體陣列140是製作在基板130之上。接著，將基板130翻過來，利用晶圓接合技術接合到基板200。據此，如圖6B所示，記憶體陣列140係透過連接層220電性連接至基板200之上的CMOS電晶體210。接著，如圖6C所示，基板200被消除，記憶體陣列140被暴露出來。然後，在記憶體陣列140的暴露面上製作連接層150。
如圖6D所示，在基板260之上製作第二群CMOS電晶體 290。優選的基板260是絕緣層上矽(silicon-on-insulator,SOI)晶圓，其包含在一層氧化層(如二氧化矽層)的正反兩面之外包上兩層單晶矽。如圖6D所示，CMOS電晶體290與其上的連接層300形成於矽層280之上。矽層280與基板260之間隔了一層二氧化矽層270。接著，基板260被翻過來經過晶圓接合之後，使得CMOS電晶體290通過連接層150電性連接到記憶體陣列140，如圖6E所示。
接著，如圖6F所示，基板260被消除以便暴露二氧化矽層270，並且連接層310被製作在其上以便電性連接CMOS電晶體290。其製作結果包含了在單晶矽基板200上的CuA型態的CMOS電晶體210、記憶體陣列140與至少部分重疊的CMOS電晶體210，CoA型態的CMOS電晶體290與至少部分重疊的記憶體陣列140，以及在記憶體陣列140之上或之下的多重連接層150、220與310。藉由提供穿過矽層310的穿孔，可以提供額外之電性連接至半導體基板的相對表面。透過在記憶體陣列之下和之上提供CMOS電晶體，如圖6A至6F所示，可以得到一組高效率的記憶體陣列。所謂的高效率的記憶體陣列指的是在半導體晶圓上製造的記憶體陣列，實質上其所有的面積均被記憶體單元(cell)所佔用。例如，在圖6A~6F當中，在記憶體陣列140下方的CMOS電晶體210可以是高電壓或類比電晶體，而在記憶體陣列140上方的CMOS電晶體290可以是低壓、短通道的高性能邏輯CMOS電晶體，其所欲之位置係為距離晶片輸出入墊的盡可能接近之處。
根據本發明的另一實施例，可以使用晶圓接合技術將一記憶體區塊接合到另一記憶體區塊。當這樣做時，可以透過最小化記憶體結構之長寬比來簡化製程，使得在單一晶片上做到高面積密度的記憶體結構。 圖7A~7C描繪利用基板300與350來進行晶圓接合記憶體區塊310與360。如圖7A所示，CMOS電晶體210、連接層220與記憶體區塊310製作在基板300之上。此外，記憶體區塊360製作在基板350之上。如圖7B所示，翻轉基板350，並且與基板360進行晶圓接合，使得記憶體區塊310與350電性連接。如圖7C所示，接著消除基板350，並且製作連接層370。
根據本發明的另一實施例，可以在一單晶基板之上沉積一磊晶的矽層來組成記憶體單元電晶體的單晶矽通道。對於具有CuA型態的CMOS電晶體的記憶體區塊而言，這樣的製程是困難的，因為可能不存在從基板到源極與汲極的「乾淨」路徑。在薄膜存儲電晶體上形成單晶磊晶矽層的範例已經被揭露，例如，在第二臨時申請案當中。特別地說，第二臨時申請案揭露在其它形式的薄膜存儲電晶體當中，有一類稱為準揮發記憶體電路(QVM,quasi-volatile memory)的薄膜存儲電晶體，其資料留存時間(例如100毫秒(millisecond)至一年之間)大於傳統的動態隨機存取記憶體電路，但小於傳統的非揮發記憶體電路。舉例來說，QVM電路的組織結構可以是NOR記憶體串的三維陣列。當一矽基板上只有記憶體區塊(亦即下面沒有CuA型態的CMOS電晶體時)，可以提供一條乾淨的路徑給磊晶矽層的沉積。所得記憶體區塊的基板會接著被晶圓接合到另一塊已經製作好CMOS電晶體的基板。圖8A~8E描繪根據本發明一實施例的一製程，其CuA型態的CMOS電晶體被放置在一記憶體區塊之下，該記憶體區塊的單元中具有磊晶單晶矽通道。
如圖8A所示，主動條帶的堆疊首先形成在基板400之上，每個主動條帶包含源極與汲極層420，其分別鄰近主動條帶之堆疊的溝槽一直 延伸到基板400。在矽基板400上的磊晶矽430接著從基板400的表面402上長出，如圖8B所示。然後如圖8C所示，利用非等向蝕刻(anisotropic etch)來移除溝槽中的所有磊晶矽，除了在主動條帶的源極層與汲極層之間的凹陷區域所留下的磊晶矽通道440以外。如圖8D所示，繼續製作記憶體區塊810直到完成為止。(製作過程的實施例已經被揭露，例如共同在審申請案已經揭露。)在圖8D-8E當中，基板400接著被翻轉並且晶圓接合到基板450，其包含了在上形成的CMOS電晶體210與連接層220。可以消除基板400，然後以先前敘述的方式在記憶體區塊之上製造連接層。
上述的詳細描述係用於描述本發明的特定實施例，而非用於限制本發明的範圍。可以在符合本發明的範圍中進行許多變化與修改。本發明的範圍定義在以下的申請專利範圍。
370:連接層

Claims (10)

  1. 一種積體電路，包含：一單晶半導體基板；一第一電路集合，其更包含形成於該單晶半導體基板之上的單晶電晶體；一第一連接層，其更包含形成在該第一電路集合上的一些導體；一第一記憶體區塊，其透過該第一連接層的該些導體與該第一電路集合電性連接，其中該第一連接層的該些導體與該第一記憶體區塊是透過晶圓接合技術而連接；一第二連接層，形成在該第一記憶體區塊之上，其中該第二連接層包含一些導體，以及其中該第一連接層與該第二連接層係位於該第一記憶體區塊的兩個相對面；以及一第二電路集合，其中該第二電路集合包含單晶電晶體，其中該第二電路集合係透過該第二連接層的該些導體連接至該第一記憶體區塊，以及其中該第二電路集合與該第二連接層的該些導體是透過晶圓接合技術而連接。
  2. 如申請專利範圍第1項的積體電路，其中該晶圓接合技術為下列其中之一；熱壓晶圓接合技術、黏合晶圓接合技術、陽極晶圓接合技術與熱晶圓接合技術。
  3. 如申請專利範圍第1項的積體電路，其中該第二電路集合係形成於一矽層當中，且該矽層係位於一絕緣層上矽晶圓的一絕緣層之上。
  4. 如申請專利範圍第3項的積體電路，更包含一第三連接層，其中該第三連接層包含一些導體，且該第三連接層位於該絕緣層的一面，其反面為該第二電路集合所形成之該矽層。
  5. 如申請專利範圍第1項的積體電路，其中該第一電路集合包含高壓或類比電晶體。
  6. 如申請專利範圍第1項的積體電路，其中該第二電路集合係由低壓、短通道的高性能邏輯互補式金屬氧化物半導體電晶體所組成。
  7. 如申請專利範圍第1項的積體電路，其中該第一記憶體區塊包含具有單晶矽通道材料的記憶體單元。
  8. 如申請專利範圍第1項的積體電路，其中該第一記憶體區塊包含下列其中之一或更多：一非揮發性記憶體串陣列與一準揮發記憶體串陣列。
  9. 如申請專利範圍第8項的積體電路，其中該第一記憶體區塊係組織為三維記憶體陣列。
  10. 如申請專利範圍第9項的積體電路，其中該三維記憶體陣列包含非或閘型的記憶體串。
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