FR3082638B1 - Conception d'un circuit 3d comprenant des macros - Google Patents
Conception d'un circuit 3d comprenant des macros Download PDFInfo
- Publication number
- FR3082638B1 FR3082638B1 FR1855326A FR1855326A FR3082638B1 FR 3082638 B1 FR3082638 B1 FR 3082638B1 FR 1855326 A FR1855326 A FR 1855326A FR 1855326 A FR1855326 A FR 1855326A FR 3082638 B1 FR3082638 B1 FR 3082638B1
- Authority
- FR
- France
- Prior art keywords
- macros
- circuit
- design
- circuit design
- trace
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/18—Manufacturability analysis or optimisation for manufacturability
Abstract
L'invention concerne un procédé de conception de circuit 3D comprenant : fournir des fichiers de conception de circuit (410) représentant une conception de circuit 3D comprenant un ou plusieurs macros comportant chacun une propriété permettant que d'autres éléments de circuit lui soient superposés ; réaliser, par l'outil de conception de circuit (402, 404), un placement et un routage comprenant au moins partiellement la superposition d'une ou plusieurs cellules logiques sur lesdits un ou plusieurs macros et le routage de connexions entre lesdites une ou plusieurs cellules logiques et des plots d'interconnexion 3D définis sur des faces desdits un ou plusieurs macros ; et générer un tracé de circuit 3D final en extrayant, à partir du tracé de circuit 3D, un premier tracé de circuit d'un premier niveau comprenant lesdites une ou plusieurs cellules logiques et un deuxième tracé de circuit d'un deuxième niveau comprenant lesdits un ou plusieurs macros.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1855326A FR3082638B1 (fr) | 2018-06-18 | 2018-06-18 | Conception d'un circuit 3d comprenant des macros |
EP19180684.3A EP3584724A1 (fr) | 2018-06-18 | 2019-06-17 | Conception d'un circuit en 3d comprenant des macros |
US16/443,509 US10997346B2 (en) | 2018-06-18 | 2019-06-17 | Conception of a 3D circuit comprising macros |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1855326A FR3082638B1 (fr) | 2018-06-18 | 2018-06-18 | Conception d'un circuit 3d comprenant des macros |
FR1855326 | 2018-06-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3082638A1 FR3082638A1 (fr) | 2019-12-20 |
FR3082638B1 true FR3082638B1 (fr) | 2021-07-02 |
Family
ID=63684026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1855326A Active FR3082638B1 (fr) | 2018-06-18 | 2018-06-18 | Conception d'un circuit 3d comprenant des macros |
Country Status (3)
Country | Link |
---|---|
US (1) | US10997346B2 (fr) |
EP (1) | EP3584724A1 (fr) |
FR (1) | FR3082638B1 (fr) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11720736B2 (en) * | 2013-04-15 | 2023-08-08 | Monolithic 3D Inc. | Automation methods for 3D integrated circuits and devices |
US11615228B1 (en) * | 2013-04-15 | 2023-03-28 | Monolithic 3D Inc. | Automation methods for 3D integrated circuits and devices |
US11120884B2 (en) | 2015-09-30 | 2021-09-14 | Sunrise Memory Corporation | Implementing logic function and generating analog signals using NOR memory strings |
TWI713195B (zh) | 2018-09-24 | 2020-12-11 | 美商森恩萊斯記憶體公司 | 三維nor記憶電路製程中之晶圓接合及其形成之積體電路 |
CN113383415A (zh) * | 2019-01-30 | 2021-09-10 | 日升存储公司 | 使用晶片键合的具有嵌入式高带宽、高容量存储器的设备 |
US10868538B1 (en) * | 2019-07-29 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company Ltd. | Logic cell structure and integrated circuit with the logic cell structure |
WO2021127218A1 (fr) | 2019-12-19 | 2021-06-24 | Sunrise Memory Corporation | Procédé de préparation d'une zone de canal d'un transistor à couches minces |
US11699662B2 (en) | 2020-01-23 | 2023-07-11 | Nvidia Corporation | Face-to-face dies with probe pads for pre-assembly testing |
US11616023B2 (en) | 2020-01-23 | 2023-03-28 | Nvidia Corporation | Face-to-face dies with a void for enhanced inductor performance |
WO2021159028A1 (fr) | 2020-02-07 | 2021-08-12 | Sunrise Memory Corporation | Circuit de mémoire à haute capacité à faible latence efficace |
US11507301B2 (en) | 2020-02-24 | 2022-11-22 | Sunrise Memory Corporation | Memory module implementing memory centric architecture |
CN111710644B (zh) * | 2020-05-20 | 2022-01-04 | 西南科技大学 | 一种基于硅通孔的三维集成电路布局方法 |
US11569219B2 (en) * | 2020-10-22 | 2023-01-31 | Arm Limited | TSV coupled integrated circuits and methods |
US11455454B2 (en) * | 2020-11-24 | 2022-09-27 | Arm Limited | Methods and apparatuses for concurrent coupling of inter-tier connections |
WO2022173700A1 (fr) | 2021-02-10 | 2022-08-18 | Sunrise Memory Corporation | Interface de mémoire dotée de voies de données en série à grande vitesse configurables pour mémoire à grande largeur de bande |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7526739B2 (en) * | 2005-07-26 | 2009-04-28 | R3 Logic, Inc. | Methods and systems for computer aided design of 3D integrated circuits |
US8060843B2 (en) * | 2008-06-18 | 2011-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Verification of 3D integrated circuits |
US9021414B1 (en) * | 2013-04-15 | 2015-04-28 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US20150199464A1 (en) * | 2014-01-10 | 2015-07-16 | Nvidia Corporation | Floorplan anneal using perturbation of selected automated macro placement results |
US20160042110A1 (en) * | 2014-08-10 | 2016-02-11 | Qualcomm Incorporated | High quality physical design for monolithic three-dimensional integrated circuits (3d ic) using two-dimensional integrated circuit (2d ic) design tools |
-
2018
- 2018-06-18 FR FR1855326A patent/FR3082638B1/fr active Active
-
2019
- 2019-06-17 EP EP19180684.3A patent/EP3584724A1/fr active Pending
- 2019-06-17 US US16/443,509 patent/US10997346B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US10997346B2 (en) | 2021-05-04 |
FR3082638A1 (fr) | 2019-12-20 |
EP3584724A1 (fr) | 2019-12-25 |
US20190384884A1 (en) | 2019-12-19 |
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Year of fee payment: 2 |
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PLSC | Publication of the preliminary search report |
Effective date: 20191220 |
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