JP7335309B2 - 3次元メモリデバイスのハイブリッドボンディングコンタクト構造 - Google Patents
3次元メモリデバイスのハイブリッドボンディングコンタクト構造 Download PDFInfo
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Description
本出願は、参照によりその全体が本明細書に組み込まれる、2017年3月8日に出願した中国特許出願第201710135655.3号の優先権を主張する。
110 メモリプレーン
115 メモリブロック
120 コンタクトパッド
130 領域
140 領域
150 領域
160 ビット線(BL)TAC領域、BL TAC領域
170 ワード線(WL)TAC領域
172 WL TAC領域
180 階段構造(SS)TAC領域
200 領域
210 チャネル構造領域
212 チャネル構造
214 スリット構造
222 ダミーチャネル構造
224 バリア構造
226 複数のTAC
233 ビット線(BL)TAC領域、BL TAC領域、TAC領域
242 メモリフィンガー
246 ダミーメモリフィンガー
255 上部セレクトゲートカット
300A 領域
300B 領域
300C 領域
312 チャネル構造、チャネル構造
314 スリット構造
316 スリット構造
318 ギャップ
320 チャネル構造領域
322 ダミーチャネル構造
324 バリア構造
326 TAC
330 上部選択ゲート(TSG)階段領域、TSG階段領域
342 メモリフィンガー
344 メモリフィンガー
350 ダミーチャネル領域
355 上部セレクトゲートカット
372 ワード線(WL)TAC領域、WL TAC領域
376 ワード線(WL)TAC領域、WL TAC領域
400A 領域
400B 領域
410 階段領域
412 チャネル構造
414 スリット構造
416 スリット構造
418 ギャップ
420 チャネル構造領域
424 バリア構造
426 複数のTAC、TAC
432 ワード線コンタクト
442 メモリフィンガー
444 メモリフィンガー
482 階段構造(SS)TAC領域、SS TAC領域
484 階段構造(SS)TAC領域、SS TAC領域
455 上部セレクトゲートカット
500 3Dメモリデバイス
500A チップ、第1のチップ
500B チップ、第2のチップ
500C 3Dメモリデバイス
510 第2の基板
514 スリット構造
516 バリア構造
520 周辺相互接続層
522 相互接続構造
524 第2のボンディング界面、第2のボンディング面
526 TAC
530 アレイ相互接続層
532 相互接続構造
534 第1のボンディング界面、第1のボンディング面
540 ベース基板
542 開口部
555 ボンディング界面
560 交互誘電体スタック
560A 第1の誘電体層
560B 第2の誘電体層
570 基板、第1の基板
580 交互導体/誘電体スタック
580A 伝導層
580B 誘電体層
710 第2のシリコン基板、薄くされた第1の基板、単結晶シリコン層、第1の基板
720 交互スタック
726 TAC
730 アレイ相互接続層
733 相互接続構造
740 誘電体層、周辺相互接続層
742 相互接続構造
750 第2の基板
760 誘電体層
762 相互接続構造
Claims (18)
- 第1の基板上に配設される交互層スタックであって、
複数の誘電体層ペアを備える交互誘電体スタックを含む第1の領域、および
複数の導体/誘電体層ペアを備える交互導体/誘電体スタックを含む第2の領域
を備えた交互層スタックと、
前記第1の領域を前記第2の領域から横に隔てるように前記交互層スタックを通じて垂直に、且つ、第1の方向に沿って横に延びる2つの平行なバリア壁を含むバリア構造と、
前記第1の領域内の複数の貫通アレイコンタクトであって、各貫通アレイコンタクトが前記交互誘電体スタックを通じて垂直に延びる貫通アレイコンタクトと、
前記垂直方向に前記交互導体/誘電体スタックを通って延びる複数のチャネル構造と、
複数のダミーチャネル構造であって、各ダミーチャネル構造が、前記交互導体/誘電体スタックを通って垂直に延びる、複数のダミーチャネル構造と、
を備え、
前記2つの平行なバリア構造が、第2の方向に沿って前記複数のダミーチャネル構造によって挟まれ、前記複数のダミーチャネル構造が、前記第2の方向に沿って前記複数のチャネル構造によって挟まれる、3次元(3D)NANDメモリデバイス。 - 前記複数の貫通アレイコンタクトに接触する少なくとも1つの第1の相互接続構造を含むアレイ相互接続層をさらに備え、
前記アレイ相互接続層が、前記第1の基板とは反対側の前記交互層スタックの端部における前記交互層スタック上に配設され、又は、前記交互層スタックとは反対側である前記第1の基板の表面上に配設される、
請求項1に記載のメモリデバイス。 - 第2の基板上における周辺回路と、
前記周辺回路に接触する少なくとも1つの第2の相互接続構造を含む周辺相互接続層と、
をさらに備え、
前記周辺回路が、前記少なくとも1つの第1の相互接続構造及び前記少なくとも1つの第2の相互接続構造を介して前記複数の貫通アレイコンタクトのうちの少なくとも1つと電気的に接続されるように、前記アレイ相互接続層が前記周辺相互接続層に結合される、
請求項2に記載のメモリデバイス。 - 前記バリア構造が、前記交互層スタックを通じて垂直に、且つ、前記第2の方向に沿って横に延びる2つの平行なバリア壁をさらに含み、
前記第1の領域が、前記バリア構造によって横から囲まれる、
請求項1に記載のメモリデバイス。 - 前記バリア構造が、2つの上部選択ゲート階段領域に挟まれている、
請求項4に記載のメモリデバイス。 - 前記交互導体/誘電体スタックを複数のメモリフィンガーに分割するように、前記交互導体/誘電体スタックを通じて垂直に、且つ、前記第1の方向に沿って横にそれぞれ延びる複数のスリット構造をさらに備える、
請求項4に記載のメモリデバイス。 - 前記バリア構造が、前記第2の方向に沿った2つの隣り合ったスリット構造に挟まれている、
請求項6に記載のメモリデバイス。 - 前記バリア構造が、前記第1の方向に沿って直線的に延びる断続的なスリット構造の2つの部分の間に配置される、請求項6に記載のメモリデバイス。
- 複数の第1の領域が前記第2の方向に沿って並べられるように前記第2の領域から前記複数の第1の領域を取り囲む複数のバリア構造をさらに備え、
前記複数の第1の領域の各々が、前記第2の方向に2つの隣り合ったスリット構造の間に挟まれる、
請求項6に記載のメモリデバイス。 - 前記第2の方向に2つの隣り合ったバリア構造によって挟まれている少なくとも1つのスリット構造が、ギャップを含み、前記少なくとも1つのスリット構造が、前記複数のメモリフィンガーのうちの隣り合ったメモリフィンガーのワード線を相互接続するように構成されている、
請求項9に記載のメモリデバイス。 - 前記第1の基板が、前記第1の領域に対応する開口部を含み、
前記第1の領域における各貫通アレイコンタクトが、前記開口部を通じて前記第1の基板を貫く、
請求項1に記載のメモリデバイス。 - 前記第1の領域及び前記バリア構造が、階段領域に配置される、
請求項6に記載のメモリデバイス。 - 前記バリア構造が3面バリア構造になるように、前記バリア構造が、前記第2の方向に沿って横に延び、前記2つの平行なバリア壁に接続されるバリア壁をさらに含む、
請求項4に記載のメモリデバイス。 - 前記スリット構造の少なくとも1つが、前記階段領域で切断されている、
請求項12に記載のメモリデバイス。 - 複数の誘電体層ペアを備える交互誘電体スタックを含む第1の領域、および
複数の導体/誘電体層ペアを備える交互導体/誘電体スタックを含む第2の領域
を備える交互層スタックを第1の基板上に形成するステップと、
前記第1の領域を前記第2の領域から横に隔てるように前記交互層スタックを通じて垂直に、且つ、第1の方向に沿って横に延びる2つの平行なバリア壁を含むバリア構造を形成するステップと、
前記第1の領域に複数の貫通アレイコンタクトを形成する段階であって、各貫通アレイコンタクトが前記交互誘電体スタックを通じて垂直に延びる、複数の貫通アレイコンタクトを形成するステップと、
前記垂直方向に前記交互導体/誘電体スタックを通って延びる複数のチャネル構造を形成する段階と、
複数のダミーチャネル構造であって、各ダミーチャネル構造が、前記交互導体/誘電体スタックを通って垂直に延びる、複数のダミーチャネル構造を形成する段階と、
を含み、
前記2つの平行なバリア構造が、第2の方向に沿って前記複数のダミーチャネル構造によって挟まれ、前記複数のダミーチャネル構造が、前記第2の方向に沿って前記複数のチャネル構造によって挟まれる、3次元(3D)NANDメモリデバイスを形成する方法。 - 前記複数の貫通アレイコンタクトに接触する少なくとも1つの第1の相互接続構造を含むアレイ相互接続層を形成するステップをさらに含み、
前記アレイ相互接続層が、前記第1の基板とは反対側の前記交互層スタックの端部における前記交互層スタック上に形成され、又は、前記交互層スタックとは反対側である前記第1の基板の表面上に配設される、
請求項15に記載の方法。 - 第2の基板上に周辺回路を形成するステップと、
前記周辺回路に接触する少なくとも1つの第2の相互接続構造を含む周辺相互接続層を形成するステップと、
前記周辺回路が、前記少なくとも1つの第1の相互接続構造及び前記少なくとも1つの第2の相互接続構造を介して前記複数の貫通アレイコンタクトのうちの少なくとも1つと電気的に接続されるように、前記アレイ相互接続層を前記周辺相互接続層に結合するステップと、
さらに含む、請求項16に記載の方法。 - 前記第2の領域に少なくとも2つの上部選択ゲート階段領域を形成するステップであって、前記バリア構造が、前記第1の方向に沿って前記少なくとも2つの上部選択ゲート階段領域によって挟まれるようになるステップをさらに含む、
請求項15に記載の方法。
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