JP7451567B2 - 三次元メモリデバイス、および三次元メモリデバイスを形成するための方法 - Google Patents
三次元メモリデバイス、および三次元メモリデバイスを形成するための方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 87
- 239000000758 substrate Substances 0.000 claims description 191
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- 239000003989 dielectric material Substances 0.000 claims description 30
- 238000002955 isolation Methods 0.000 claims description 24
- 230000002093 peripheral effect Effects 0.000 claims description 20
- 239000002019 doping agent Substances 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 16
- 230000008878 coupling Effects 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 7
- 238000005859 coupling reaction Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 189
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 63
- 229910052710 silicon Inorganic materials 0.000 description 63
- 239000010703 silicon Substances 0.000 description 63
- 230000008569 process Effects 0.000 description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- 238000000231 atomic layer deposition Methods 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 13
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- 230000006870 function Effects 0.000 description 7
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- 239000012212 insulator Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- -1 amorphous silicon Chemical compound 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 238000009713 electroplating Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Description
102 P型基板
104 Nウェル
106 Pウェル
108 Nウェル
110 メモリスタック
112 導電層、ワード線
114 誘電層
116 チャネル構造
118 スリット構造
120 ビット線
122 壁形コンタクト
124 ソース線
200 3Dメモリデバイス
202 基板
204 第1のドープ領域
206 第2のドープ領域
208 第3のドープ領域
210 チャネル構造
212 導電層、ワード線
214 誘電層
216 メモリスタック
218 ビット線
220 絶縁構造
222 ソースコンタクト
300、301 3Dメモリデバイス
302 基板
304 第1のドープ領域
306 第2のドープ領域
308 第3のドープ領域
310 絶縁構造
312 チャネル構造
314 導電層、ワード線
316 誘電層
318 メモリスタック
320 ビット線
322 スリット構造
322 スリット構造
324 ソースコンタクト
326 スペーサ
328 ソース線、ソースメッシュ
330 コンタクト
400、401 3Dメモリデバイス
402 絶縁構造
404 ソースコンタクト
500 3Dメモリデバイス
501 基板
502 第1の半導体構造
504 第2の半導体構造
506 接合境界面、結合境界面
508 トランジスタ
510 インターコネクト層
512、514 接合層、結合層
516 インターコネクト層
518 メモリスタック
520 導電層
522 誘電層
524 チャネル構造
526 ビット線
528 絶縁構造
530 半導体層
532 第1のドープ領域
534 第2のドープ領域
536 第3のドープ領域
538 絶縁構造
540 コンタクト
542 コンタクト
602 シリコン基板
604 ドープ領域
606 チャネル構造
608 絶縁構造
610 ドープ領域
612 コンタクト
614 ビット線
616 絶縁構造
618 コンタクト
Claims (17)
- 第1の側面、および前記第1の側面と反対の第2の側面を有する基板と、
前記基板の前記第1の側面に交互の導電層および誘電層を備えるメモリスタックと、
前記メモリスタックを通じて各々が垂直に延びる複数のチャネル構造と、
前記メモリスタックを通じて垂直に延び、前記複数のチャネル構造を複数のブロックへと分離するために横に延びるスリット構造と、
前記基板における、前記スリット構造と接触する第1のドープ領域と、
前記基板の前記第2の側面から前記第1のドープ領域へと垂直に延びる絶縁構造と、
前記基板における、前記絶縁構造によって分離される複数の第2のドープ領域であって、前記第1のドープ領域とは異なる型のドーパントを有し、前記第1のドープ領域と接触している、第2のドープ領域と、
前記第1のドープ領域に電気的に接続されるソースコンタクトと、
対応する前記第2のドープ領域の電圧を制御するための、前記第2のドープ領域のそれぞれ1つと各々が接触する複数のコンタクトと
を備え、
前記第2のドープ領域は、前記絶縁構造および前記第1のドープ領域によって前記ブロックへと分離される三次元(3D)メモリデバイス。 - 前記絶縁構造はトレンチアイソレーションを備える、請求項1に記載の3Dメモリデバイス。
- 前記ブロックの各々における1つまたは複数の前記チャネル構造は、前記ブロックにおける前記第2のドープ領域のそれぞれ1つと接触する、請求項1に記載の3Dメモリデバイス。
- 前記コンタクトは前記基板の前記第1の側面へと延びる、請求項1に記載の3Dメモリデバイス。
- 前記コンタクトは前記基板の前記第2の側面へと延びる、請求項1に記載の3Dメモリデバイス。
- 前記第1のドープ領域はNウェルを備え、前記第2のドープ領域の各々はPウェルを備える、請求項1に記載の3Dメモリデバイス。
- 前記ソースコンタクトは、前記絶縁構造によって包囲され、前記第1のドープ領域と接触するように前記基板の前記第2の側面から垂直に延びる、請求項1に記載の3Dメモリデバイス。
- 前記スリット構造は1つまたは複数の誘電性材料で満たされる、請求項1に記載の3Dメモリデバイス。
- 周辺回路を備える第1の半導体構造と、
交互の導電層および誘電層を備えるメモリスタック、
前記メモリスタックを通じて各々が垂直に延び、前記周辺回路に電気的に連結される複数のチャネル構造、
前記メモリスタックを通じて各々が垂直に延び、前記複数のチャネル構造を複数のブロックへと分離するために横に延びる複数のスリット構造、
前記複数のスリット構造のそれぞれ1つと各々が接触し、同じ型のドーパントを有する複数の第1のドープ領域、および、前記複数の第1のドープ領域と接触し、前記複数の第1のドープ領域とは異なる型のドーパントを有する複数の第2のドープ領域を備える半導体層、
前記複数の第2のドープ領域を前記ブロックへと分離するために、前記半導体層の後側から前記複数の第1のドープ領域のそれぞれ1つへと各々が垂直に延びる複数の絶縁構造、
前記複数の第1のドープ領域に電気的に接続されるソースコンタクト、ならびに、
対応する前記第2のドープ領域の電圧を制御するための、前記第2のドープ領域のそれぞれ1つと各々が接触する複数のコンタクト、
を備える第2の半導体構造と、
前記第1の半導体構造と前記第2の半導体構造との間の接合境界面であって、ハイブリッド結合の結果として、前記第1の半導体構造の基板とは反対側の前記周辺回路の側に形成された結合層と前記第2の半導体構造の前記半導体層とは反対側の前記メモリスタックの側に形成された結合層との間に配置される結合境界面である、接合境界面と
を備える三次元(3D)メモリデバイス。 - 前記絶縁構造の各々はトレンチアイソレーションを備える、請求項9に記載の3Dメモリデバイス。
- 前記ブロックの各々における1つまたは複数の前記チャネル構造は、前記ブロックにおける前記第2のドープ領域のそれぞれ1つと接触する、請求項9に記載の3Dメモリデバイス。
- 前記コンタクトは前記半導体層の前側へと延びる、請求項9に記載の3Dメモリデバイス。
- 前記コンタクトは前記半導体層の前記後側へと延びる、請求項9に記載の3Dメモリデバイス。
- 前記第1のドープ領域はNウェルを備え、前記第2のドープ領域の各々はPウェルを備える、請求項9に記載の3Dメモリデバイス。
- 三次元(3D)メモリデバイスを形成するための方法であって、
基板の第1の側面から、前記基板にドープ領域を形成するステップと、
前記基板の前記第1の側面においてメモリスタックを通じて各々が垂直に延びる複数のチャネル構造を形成するステップと、
前記基板において、前記ドープ領域と接触する第1のドープ領域を、前記メモリスタックを通じて前記基板へと垂直に延びるスリット開口を通じてドーピングすることにより形成するステップと、
前記メモリスタックを通じて前記第1のドープ領域へと垂直に延び、前記複数のチャネル構造を複数のブロックへと分離するために横に延びるスリット構造を形成するステップであって、前記スリット構造は、前記スリット開口内に、1つまたは複数の誘電性材料、または、1つまたは複数の誘電性材料および1つまたは複数の導電性材料を満たすことによって形成される、ステップと、
前記ドープ領域を複数の第2のドープ領域へと分離するために、前記基板の第2の側面から前記第1のドープ領域へと垂直に延びる絶縁構造を形成するステップであって、前記第2のドープ領域は、前記第1のドープ領域とは異なる型のドーパントを有し、前記第1のドープ領域と接触しており、前記第2のドープ領域は、前記絶縁構造および前記第1のドープ領域によって前記ブロックへと分離される、ステップと、
前記第1のドープ領域に電気的に接続されるソースコンタクトを形成するステップと、
対応する前記第2のドープ領域の電圧を制御するための、前記第2のドープ領域のそれぞれ1つと各々が接触する複数のコンタクトを形成するステップと、
を含む方法。 - 基板の第1の側面から、前記基板にドープ領域を形成する前記ステップと、前記基板の前記第1の側面においてメモリスタックを通じて各々が垂直に延びる複数のチャネル構造を形成する前記ステップと、の間に、
前記基板の前記第1の側面に交互の犠牲層および誘電層を備える誘電体スタックを形成するステップと、
前記誘電体スタックを通じて前記基板へと垂直に延びるスリット開口を形成するステップと、
前記スリット開口を通じて前記犠牲層を導電層で置き換えることで、交互の導電層および前記誘電層を備える前記メモリスタックを形成するステップと
をさらに含む、請求項15に記載の方法。 - 前記絶縁構造を形成するステップは、
前記基板の前記第2の側面から、前記第1のドープ領域までトレンチをエッチングするステップと、
前記トレンチを1つまたは複数の誘電性材料で満たすステップと
を含む、請求項15に記載の方法。
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