JP7459136B2 - 三次元メモリデバイス、および三次元メモリデバイスを形成するための方法 - Google Patents
三次元メモリデバイス、および三次元メモリデバイスを形成するための方法 Download PDFInfo
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Description
102 P型基板
104 Nウェル
106 Pウェル
108 Nウェル
110 メモリスタック
112 導電層、ワード線
114 誘電層
116 チャネル構造
118 スリット構造
120 ビット線
122 壁形コンタクト
124 ソース線
200 3Dメモリデバイス
202 基板
204 第1のドープ領域
206 第2のドープ領域
208 第3のドープ領域
210 チャネル構造
212 導電層、ワード線
214 誘電層
216 メモリスタック
218 ビット線
220 絶縁構造
222 ソースコンタクト
300、301 3Dメモリデバイス
302 基板
304 第1のドープ領域
306 第2のドープ領域
308 第3のドープ領域
310 絶縁構造
312 チャネル構造
314 導電層、ワード線
316 誘電層
318 メモリスタック
320 ビット線
322 スリット構造
324 ソースコンタクト
326 スペーサ
328 ソース線、ソースメッシュ
330 コンタクト
331 コンタクト
400、401 3Dメモリデバイス
402 絶縁構造
404 ソースコンタクト
500 3Dメモリデバイス
501 基板
502 第1の半導体構造
504 第2の半導体構造
506 接合境界面
508 トランジスタ
510 インターコネクト層
512、514 結合層
516 インターコネクト層
518 メモリスタック
520 導電層
522 誘電層
524 チャネル構造
526 ビット線
528 絶縁構造
530 半導体層
532 第1のドープ領域
534 第2のドープ領域
536 第3のドープ領域
538 絶縁構造
540 コンタクト
542 コンタクト
602 シリコン基板
604 ドープ領域
606 チャネル構造
608 絶縁構造
610 ドープ領域
612 コンタクト
614 ビット線
616 絶縁構造
618 コンタクト
Claims (17)
- 第1の側面、および前記第1の側面と反対の第2の側面を有する基板と、
前記基板の前記第1の側面に交互の導電層および誘電層を備えるメモリスタックと、
前記メモリスタックを通じて各々が垂直に延びる複数のチャネル構造と、
前記メモリスタックを通じて垂直に延び、前記複数のチャネル構造を複数のブロックへと分離するために横に延びる第1の絶縁構造と、
前記基板における、前記第1の絶縁構造と接触する第1のドープ領域と、
前記第1のドープ領域と接触するように前記基板の前記第2の側面から垂直に延びる第1のコンタクトと、
前記基板における、前記第1のドープ領域と接触する第2のドープ領域と、
前記第2のドープ領域と接触する第2のコンタクトと
を備え、
前記第2のコンタクトは前記基板の前記第2の側面へと延びる、三次元(3D)メモリデバイス。 - 前記第1の絶縁構造は1つまたは複数の誘電性材料で満たされる、請求項1に記載の3Dメモリデバイス。
- 前記第1のコンタクトは垂直インターコネクトアクセス(VIA)コンタクトまたは壁形コンタクトを備える、請求項1に記載の3Dメモリデバイス。
- 前記チャネル構造の各々は前記第2のドープ領域と接触する、請求項1に記載の3Dメモリデバイス。
- 前記第1のドープ領域はNウェルを備え、前記第2のドープ領域はPウェルを備える、請求項1に記載の3Dメモリデバイス。
- 前記第1のドープ領域の各々が前記第1の絶縁構造のそれぞれ1つと接触するように、複数の前記第1の絶縁構造と複数の前記第1のドープ領域とをさらに備え、
前記第2のドープ領域は前記複数の第1のドープ領域と接触する、請求項1に記載の3Dメモリデバイス。 - 前記第2のドープ領域を前記ブロックへと分離するために、前記基板の前記第2の側面から前記第1のドープ領域へと垂直に延びる第2の絶縁構造をさらに備え、
前記第1のコンタクトは前記第2の絶縁構造によって包囲される、請求項1に記載の3Dメモリデバイス。 - 周辺回路を備える第1の半導体構造と、
第1の側面、および前記第1の側面と反対の第2の側面を有する基板、
前記基板の前記第1の側面に交互の導電層および誘電層を備えるメモリスタック、
前記メモリスタックを通じて各々が垂直に延び、前記周辺回路に電気的に連結される複数のチャネル構造、
前記メモリスタックを通じて各々が垂直に延び、前記複数のチャネル構造を複数のブロックへと分離するために横に延びる複数の絶縁構造、
前記複数の絶縁構造のそれぞれ1つと各々が接触する複数の第1のドープ領域、および、前記複数の第1のドープ領域と接触する第2のドープ領域を備える半導体層、
前記第1のドープ領域のそれぞれ1つと接触するように前記半導体層の前記第2のドープ領域を通じて垂直に各々が延びる複数の第1のコンタクト、ならびに、
前記第2のドープ領域と接触する第2のコンタクト
を備え、前記第2のコンタクトは前記基板の前記第2の側面へと延びる、第2の半導体構造と、
前記第1の半導体構造と前記第2の半導体構造との間の接合境界面と
を備える三次元(3D)メモリデバイス。 - 前記絶縁構造の各々は1つまたは複数の誘電性材料で満たされる、請求項8に記載の3Dメモリデバイス。
- 前記コンタクトの各々は垂直インターコネクトアクセス(VIA)コンタクトまたは壁形コンタクトを備える、請求項8に記載の3Dメモリデバイス。
- 前記チャネル構造の各々は前記第2のドープ領域と接触する、請求項8に記載の3Dメモリデバイス。
- 前記第1のドープ領域はNウェルを備え、前記第2のドープ領域はPウェルを備える、請求項8に記載の3Dメモリデバイス。
- 三次元(3D)メモリデバイスを形成するための方法であって、
基板に第2のドープ領域を形成するステップと、
前記基板の第1の側面においてメモリスタックを通じて各々が垂直に延びる複数のチャネル構造を形成するステップと、
前記基板に第1のドープ領域を形成するステップであって、前記第1のドープ領域は前記第2のドープ領域と接触する、ステップと、
前記メモリスタックを通じて前記第1のドープ領域へと垂直に延び、前記複数のチャネル構造を複数のブロックへと分離するために横に延びる第1の絶縁構造を形成するステップと、
前記第1のドープ領域と接触するように前記基板の前記第1の側面と反対の第2の側面から垂直に延びる第1のコンタクトを形成するステップと、
前記第2のドープ領域と接触する第2のコンタクトを形成するステップであって、前記第2のコンタクトは前記基板の前記第2の側面へと延びる、ステップと
を含む方法。 - 前記基板の前記第1の側面に交互の犠牲層および誘電層を備える誘電体スタックを形成するステップと、
前記誘電体スタックを通じて前記基板へと垂直に延びるスリット開口を形成するステップと、
前記スリット開口を通じて前記犠牲層を導電層で置き換えることで、交互の導電層および前記誘電層を備える前記メモリスタックを形成するステップと
をさらに含む、請求項13に記載の方法。 - 前記誘電体スタックを形成するステップの前に、前記基板に前記第2のドープ領域を形成するステップを含む、請求項14に記載の方法。
- 前記第1のコンタクトを形成するステップの前に、前記第2のドープ領域を前記ブロックへと分離するために、前記基板の前記第2の側面から前記第1のドープ領域へと垂直に延びる第2の絶縁構造を形成するステップをさらに含む、請求項15に記載の方法。
- 前記第1のコンタクトを形成するステップは、前記第1のドープ領域と接触するように前記第2の絶縁構造を通じて垂直に延びる前記第1のコンタクトを形成するステップを含む、請求項16に記載の方法。
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WO2022236944A1 (en) * | 2021-05-12 | 2022-11-17 | Yangtze Memory Technologies Co., Ltd. | Memory peripheral circuit having three-dimensional transistors and method for forming the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190067308A1 (en) | 2017-08-24 | 2019-02-28 | Samsung Electronics Co., Ltd. | Non-volatile memory devices and methods of fabricating the same |
CN110246846A (zh) | 2019-06-18 | 2019-09-17 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法 |
CN110494979A (zh) | 2019-06-27 | 2019-11-22 | 长江存储科技有限责任公司 | 新型3d nand存储器件及形成其的方法 |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20180006817A (ko) * | 2016-07-11 | 2018-01-19 | 삼성전자주식회사 | 수직형 메모리 장치 |
KR20180044110A (ko) | 2016-10-21 | 2018-05-02 | 한국전기연구원 | 실리콘 카바이드 트렌치 쇼트키 배리어 다이오드의 제조방법 |
CN106876401B (zh) | 2017-03-07 | 2018-10-30 | 长江存储科技有限责任公司 | 存储器件的形成方法 |
CN106910746B (zh) | 2017-03-08 | 2018-06-19 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法、封装方法 |
JP6978645B2 (ja) * | 2017-03-08 | 2021-12-08 | 長江存儲科技有限責任公司Yangtze Memory Technologies Co., Ltd. | 3次元メモリデバイスのスルーアレイコンタクト構造 |
KR20180137264A (ko) | 2017-06-16 | 2018-12-27 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
KR20190008676A (ko) * | 2017-07-17 | 2019-01-25 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
JP7304335B2 (ja) | 2017-08-21 | 2023-07-06 | 長江存儲科技有限責任公司 | Nandメモリデバイスおよびnandメモリデバイスを形成するための方法 |
CN107658311B (zh) | 2017-08-28 | 2018-12-14 | 长江存储科技有限责任公司 | 三维存储器 |
CN107731833B (zh) * | 2017-08-31 | 2018-12-14 | 长江存储科技有限责任公司 | 一种阵列共源极填充结构及其制备方法 |
KR102442214B1 (ko) * | 2017-10-12 | 2022-09-13 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
US10236301B1 (en) | 2017-12-27 | 2019-03-19 | Micron Technology, Inc. | Methods of forming an array of elevationally-extending strings of memory cells |
KR102592894B1 (ko) * | 2018-05-10 | 2023-10-24 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
US10347654B1 (en) * | 2018-05-11 | 2019-07-09 | Sandisk Technologies Llc | Three-dimensional memory device employing discrete backside openings and methods of making the same |
CN110729305A (zh) | 2018-07-17 | 2020-01-24 | 旺宏电子股份有限公司 | 存储元件及其制造方法 |
CN108987408A (zh) | 2018-07-25 | 2018-12-11 | 长江存储科技有限责任公司 | 一种3d nand存储器及其制造方法 |
CN109103199B (zh) * | 2018-08-07 | 2021-10-29 | 长江存储科技有限责任公司 | 3d存储器件及其制造方法 |
CN109314117B (zh) * | 2018-08-14 | 2019-08-30 | 长江存储科技有限责任公司 | 操作3d存储器件的方法 |
CN109417073B (zh) | 2018-09-10 | 2019-12-06 | 长江存储科技有限责任公司 | 使用梳状路由结构以减少金属线装载的存储器件 |
CN109192734B (zh) * | 2018-09-28 | 2020-10-16 | 长江存储科技有限责任公司 | 3d存储器件 |
WO2020113590A1 (en) * | 2018-12-07 | 2020-06-11 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabricating methods thereof |
CN109786387B (zh) * | 2019-01-09 | 2023-10-17 | 长江存储科技有限责任公司 | 存储器及其形成方法、存储器的存储单元的选择方法 |
US11355486B2 (en) | 2019-02-13 | 2022-06-07 | Sandisk Technologies Llc | Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer |
CN109860197B (zh) * | 2019-02-27 | 2020-04-21 | 长江存储科技有限责任公司 | 三维存储器及形成三维存储器的方法 |
CN109920793B (zh) * | 2019-03-29 | 2021-07-23 | 长江存储科技有限责任公司 | 3d存储器件及其制造方法 |
CN110211966B (zh) * | 2019-06-18 | 2020-11-20 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法 |
JP7459136B2 (ja) | 2020-01-28 | 2024-04-01 | 長江存儲科技有限責任公司 | 三次元メモリデバイス、および三次元メモリデバイスを形成するための方法 |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190067308A1 (en) | 2017-08-24 | 2019-02-28 | Samsung Electronics Co., Ltd. | Non-volatile memory devices and methods of fabricating the same |
CN110246846A (zh) | 2019-06-18 | 2019-09-17 | 长江存储科技有限责任公司 | 一种3d nand存储器件及其制造方法 |
CN110494979A (zh) | 2019-06-27 | 2019-11-22 | 长江存储科技有限责任公司 | 新型3d nand存储器件及形成其的方法 |
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