CN112514067A - 三维nor存储器电路制造中的晶片接合 - Google Patents

三维nor存储器电路制造中的晶片接合 Download PDF

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CN112514067A
CN112514067A CN201980049198.3A CN201980049198A CN112514067A CN 112514067 A CN112514067 A CN 112514067A CN 201980049198 A CN201980049198 A CN 201980049198A CN 112514067 A CN112514067 A CN 112514067A
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memory block
memory
interconnect layer
integrated circuit
layer
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S.B.赫尔纳
E.哈拉里
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Sunrise Memory Corp
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Abstract

存储器阵列和单晶电路在同一集成电路中通过晶片接合(例如，粘合晶片接合或阳极晶片接合)来提供，并且通过互连层的导体互连。附加电路或存储器阵列可由附加晶片接合提供，并在晶片接合界面处通过互连层电连接。存储器阵列可包括具有单晶外延硅沟道材料的存储或存储器晶体管。

Description

三维NOR存储器电路制造中的晶片接合
相关申请的交叉引用
本申请涉及于2018年9月24日提交的美国临时专利申请(“临时申请I”)，序列号62/735678，标题为“三维NOR存储器电路制造中的晶片接合”，并要求其优先权。
本申请还涉及于2018年6月19日提交的序列号为16/012731、标题为“三维NOR存储器阵列结构及其制造方法”的美国专利申请(“同时待审申请”)。本申请还涉及与本申请同日提交的序列号为62/735662的美国临时专利申请(“临时申请II”)，其标题为“用于三维存储器结构中的存储晶体管的外延单晶沟道及其形成方法”。通过引用将同时待审申请和临时申请I和II的公开内容全部并入本文。
发明背景
1.技术领域
本发明涉及在集成电路制造中的晶片接合技术。特别地，本发明涉及高密度三维存储器电路的晶片接合技术。
2.背景技术
晶片接合是许多半导体装置制造时所使用的技术。在晶片接合中，两个相同或接近相同面积的晶片例如通过热压(thermocompression)、黏合(adhensive)、阳极(anodic)或是热(thermal)技术连接。一般来说，在接合之后，将全部或基本上全部基板从一片或两片晶片移除。
前述同时待审申请案揭露了三维存储器结构，其形成在单晶半导体基板顶部上，其被组织为NOR存储器字符串(string)的阵列。在此背景下，“NOR存储器字符串”指的是一组薄膜存储晶体管，其共用源极与漏极区域。图1显示了存储器结构30的剖面，其包含NOR存储器字符串的阵列，其形成在半导体基板上的CMOS(互补金属氧化物半导体)电路与互连层之上。如图1所示，存储器结构30形成在基板150之上。举例来说，可以使用本领域普通技术人员已知用于制作电子电路的半导体晶片作为适合的基板。也可以采用非半导体基板，如二氧化硅。
可以在半导体基板150上或中制作各式电路元件(如图1所示的CMOS晶体管所表示的CMOS电路10)，其经由传统互连层的导体22(例如铜)通过触点或过孔16互相连接。在形成存储器结构30之前，先使用传统的技术将这些电路元件制作在半导体基板之上。在此统称为互连层20的电路通常会嵌入在绝缘层当中，可以包含导体用来支持存储器结构30当中的存储器阵列的运作。存储器结构30会形成于互连层20之上。举例来说，互连层20提供导体24(全局字线global word lines)来连接在存储器结构30中用作各存储晶体管定址用的字线的导体32(例如重参杂多晶硅heavily-doped polysilicon)。在本说明中称导体32为局部字线(local word line)。
如图1所示，存储器结构30包含主动条带(active strip)的多个堆叠体(如主动堆叠体101a、101b与101c)。举例来说，图1显示了堆叠体101a、101b与101c，每一个堆叠体包含了四个主动条带，主动堆叠体通过绝缘层107互相绝缘。图1显示主动条带的剖面，条带纵向延伸到剖面平面内外。在此背景下，主动条带包含漏极层104、源极层103、主体(body)层102与沟道层108。(在主体层102的两侧提供沟道层108)。在某些实施方式中，漏极层104与源极层103两者均为n+多晶硅，而沟道层108为p-多晶硅，主体层102为p+多晶硅。在某些实施方式当中，可以使用电介质层来替代主体层102。如图1所示的主动条带还包含导体层105t与105b，其分别相邻于源极层103和漏极层104，用于减少沿着源极层103和漏极层104长度方向的电阻。沿着主动条带的每个堆叠体的每一边(也就是沿着每个主动条带的每边)，设置有电荷捕获(charge-trapping)层107与多条局部字线32。在图1当中，局部字线32是沿着主动条带的堆叠体两侧的导电栏。可以通过局部字线、一部分的沟道层108、其间的电荷捕获层107的部分，以及源极层103和漏极层104来形成存储晶体管。沿着主动条带形成的多个存储晶体管分享漏极层104和源极层103。沿着一主动条带而共用源极和漏极层的相邻存储晶体管形成一NOR存储器字符串。(开启在该NOR存储器字符串中的任何存储晶体管将导致在共同的源极层和漏极层之间形成一导通的晶体管电流。)
制程的顺序对CMOS装置、互连层与存储器装置造成限制。举例来说，因为需要利用低压化学气相沉积(LPCVD)形成ONO(oxide-nitride-oxide氧化物-氮化物-氧化物)多层结构或堆叠体，存储器装置通常需要在制造期间使用数个小时达至少摄氏750度的热预算(thermal budget)。在ONO多层结构当中，所需的氧化物与氮化物可以分别是高温氧化物(HTO；或二氧化硅)与氮化硅(SiN)。此外，还可能需要一层氧化铝(Al2O3)作为ONO堆叠体中的阻挡氧化物(blocking oxide)。然而，从电气性质来看，晶体化氧化铝(Al2O3)——其产生所需的Al2O3——需要摄氏九百度以上的退火(anneal)温度。然而，超过摄氏350度的制造温度将使得铜无法用于嵌入相关联的低K电介质薄膜中的水平互连层20，甚至是当钨用在垂直互连16当中以连接铜水平互连时也一样。类似地，超过摄氏500度的制造温度将排除使用铝互连层的可能。当制造温度超过摄氏500时，钨可以是互连层材料的选项之一。然而，钨具有较高的电阻，如底下的表1所示。由此产生的互连电阻的增加增加了信号延迟，这对存储器装置性能产生了不利影响。
Figure BDA0002911857150000031
存储器装置的热预算过程至少至少两种方式限制了底下的COMS电路(例如CMOS晶体管10)。首先，必须选用硅化钴或其他高温接触材料，例如钨或硅化钨作为CMOS晶体管10中的栅极、源极/漏极的金属化12，以便允许制造温度的最高值提高到摄氏750度。虽然和硅相比，硅化钴具有相对较低的薄板和接触电阻值，但因为在硅化步骤中需要消耗较多的硅，以及在硅化钴与硅之间介面粗糙度之故，需要在硅材料当中采用较深的掺杂结。相反地，短沟道长度的晶体管需要较浅的掺杂结，以便减少漏电流。虽然硅化镍通常被用在当前一代小型晶体管的源极与漏极接触点中，但由于硅化镍无法承受摄氏450度以上的温度，所以优选硅化钴，而不选硅化镍。当温度高于450℃时，硅化镍薄膜会在硅上团聚，破坏硅化镍薄膜的低片电阻和低接触电阻特性。
第二，对于浅结和窄沟道装置，结形成后应避免600℃以上的温度，以防止掺杂剂扩散出源极和漏极结。
因此，期望一种制造方法，其允许将最佳CMOS装置和互连层与三维NOR存储器结构(例如，图1的存储器结构30)集成，而存储器结构的热预算不限制CMOS装置和互连层的设计选择。
发明内容
根据本发明的一个实施例，存储器阵列和单晶电路在同一集成电路中通过晶片接合(例如，粘着晶片接合或阳极晶片接合)提供，并且通过互连层的导体互连。
附加电路或存储器阵列可由附加晶片接合提供，并由晶片接合界面处的互连层电连接。
根据本发明的一个实施例，存储器阵列可以包括具有单晶外延硅沟道材料的存储或存储器晶体管。
结合附图，在考虑下面的详细描述之后，本发明被更好地理解。
附图说明
图1显示了存储器结构30的剖面，该存储器结构包含NOR存储器字符串的阵列，其形成在半导体基板上的CMOS电路与互连层的顶部上。
图2A显示用于支持三维NOR存储器结构的互连层与CMOS装置被制造于其上的半导体基板100。
图2B显示一三维NOR存储器结构(即存储器结构30)单独地制造在半导体基板110上，在绝缘氧化物(如二氧化硅)层120之上。
图3A显示了要在晶片基板A和B上制造的两个器件A′和B′被晶片接合。
图3B显示装置A′和B′已经完美地对齐，且在晶片接合后两者电连接。
图3C显示在晶片接合后电连接的装置A′和B′，其具有250nm宽的错位。
图3D显示使用粘合金属C来促进晶片A与B在装置A′和B′的接合(即在相互接触点进行接合)。
图4示出，使用图2A和2B的晶片作为示例，可以移除存储器结构30的基板110。
图5显示在存储器结构30之上形成互连层40。
图6A、6B、6C、6D、6E、6F显示使用晶片接合技术来制作CuA和CoA电路的步骤流程。
图7A、7B、7C描绘利用基板300与350的晶片接合来连接存储块310与360。
图8A、8B、8C、8D、8E描绘根据本发明一个实施例的制程，其中CuA型的CMOS晶体管被放置在一存储块之下，该存储器单元中具有外延单晶硅沟道。
为了表示的清楚性和允许附图之间的交叉引用，附图中的相似元素被分配了相似的附图标记。
具体实施方式
根据本发明的一个实施例，不是在与存储器结构30相同的硅基板上制造CMOS装置(例如，CMOS晶体管10)和互连层(例如，互连层20)，而是在单独的半导体基板上制造CMOS装置和互连层。图2A示出了在其上制造用于支持三维NOR存储器结构的互连层20和CMOS装置10的半导体衬底100。如图2B所示，在基板110上，在隔离氧化物(例如，SiO2)层120上单独制造三维NOR存储器结构(即存储器结构30)。基板100和110都可以由硅晶片提供，如本领域普通技术人员所知。
在半导体基板100和110中的每一个上执行所需的制造步骤之后，使用“倒装芯片”技术将晶片接合在一起，其中具有互连层20的半导体基板100的表面接合到具有存储器结构30的半导体基板110的表面。以这种方式，互连层20和CMOS装置10的制造不受对制造存储器结构30最佳的高温的限制。
晶片接合成使得互连层20中的接触点电连接到存储器结构30的对应接触点。每个相应基板中的光刻对准标记允许以最小的失配对准目标接合点。图3A-3D说明基板A和B在指定晶片接合点处的示范晶片接合。图3A显示了在晶片基板A和B上制造的两个装置A′和B′被晶片接合。例如，装置A′和B′可以是互连系统中300nm宽的导体。图3B显示了装置A′和B′在晶圆接合后被完全对齐和电连接。图3C显示了装置A′和B′在晶片接合后电连接，具有250nm宽的错位。(在最先进的晶片接合技术中，对准精度可达到±250nm以内)。基板A和B的接合可使用任何合适的晶片接合技术来执行，例如热压、阳极、等离子体激活、共晶或表面激活晶片接合。在这些技术中，阳极晶片接合是优选的。通过阳极晶片接合，两个晶片基板接触并施加静电场，从而使设备进行电性和物理连接。
根据本发明一个实施例，如图3D所示，粘合金属C可用于促进晶片A和B之间在其相互接触点(即装置A′和B′处)的粘合。例如，粘合金属C可以是铬、钛、铟或其合金、或任何适合的材料。本领域普通技术人员明白晶片接合的原理与机制，因此在本说明中略过细节的讨论。
在接合之后，可以移除一个基板。图4示出，使用图2A和2B的晶片作为示例，可以移除存储器结构30的基板110。基板110可通过任何适当的晶片减薄技术来移除，例如激光剥离、机械抛光或化学蚀刻。在一个实施例中，机械抛光可与化学蚀刻结合以移除基板110。通过结合机械抛光和化学蚀刻，与单独使用任一技术相比，基板110可以更低的成本和更高的精度(即，对存储器结构30无损伤)来去除。例如，假设基板110为500微米厚。那么，机械抛光可首先在初始步骤中从基板移除约480微米，从而留下约20微米厚的基板110以通过化学蚀刻移除。
在通过机械抛光的晶片薄化技术当中，晶片会围绕其中心在研磨表面上旋转。当得到的基板表面粗糙时，通过机械力使晶片变薄有时被称为研磨”，当得到的衬底表面光滑时，其被称为“抛光”。可使用研磨或抛光方法，或其任何组合。在完成机械研磨或抛光步骤之后，化学蚀刻可移除存储器结构30的剩余20微米。
基板110的化学蚀刻可使用任何适当的化学过程来完成。用于硅基板110的合适化学试剂的实例包括KOH、TMAH、HF+、HNO3或HF+和NH4F。硅基板110和存储器结构30之间的氧化物层可用作蚀刻停止层。如图4所示，蚀刻停止层120确保存储器结构30保持完整，不受基板110的化学蚀刻的损害。当氧化层(例如，SiO2)用作蚀刻停止层时，可使用KOH，因为其蚀刻硅的速度约为其蚀刻SiO2的500倍。因此，SiO2层可作为硅蚀刻的有效蚀刻停止。
在移除基板110之后，可在接合晶片上进行进一步制造。例如，图5示出形成互连层40和存储器结构30。在存储器结构30的形成与互连层40的形成分离的情况下，可以为互连层40选择铝或铜。这种互连可以在较低的温度下形成(例如，450℃或更低)。
根据本发明另一实施例，晶片接合可以用来在存储器阵列下制造单晶晶体管，其被称为阵列下方的CMOS(“CuA”)，以及在存储阵列上方制造单晶晶体管，称为阵列上方的CMOS(“CoA”)。图6A-6F显示了使用晶片接合技术来制造CuA和CoA电路的一系列步骤。
如图6A所示，在基板200之上制作CMOS晶体管210，而存储器阵列140是制作在基板130之上。接着，将基板130翻过来，利用晶片接合技术接合到基板200，使得如图6B所示，存储器阵列140通过互连层220电连接至基板200之上的CMOS晶体管210。然后移除基板200以暴露存储器阵列140。此后，如图6C所示，从存储器阵列140的暴露侧上方制造互连层150。
如图6D所示，在基板260之上制作第二组CMOS晶体管290。基板260最优选为绝缘体上硅(“SOI”)晶片，其中在氧化物(SiO2)层的相对侧上提供两层单晶硅。如图6D所示，CMOS晶体管290及其上方的互连层300形成在硅层280上和上方，硅层280通过SiO2层270与基板260分离。然后翻转基板260并进行晶片接合，以允许CMOS晶体管290通过互连层150电连接存储器阵列140，如图6E所示。
然后将基板260移除到暴露的SiO2层270，并且互连层310被制造在上方并电连接CMOS晶体管290，如图6F所示。所得到的组合是构建在单晶硅基板200内的CuA型CMOS晶体管210，存储器阵列140至少部分地覆盖CMOS晶体管220，CoA型CMOS晶体管290至少部分覆盖存储器阵列140，以及多层互连层150、200和310覆盖和下面有存储器阵列140。通过在存储器阵列下方和上方提供CMOS晶体管，如图6A-6F所示，实现了高效存储器阵列。高效存储器阵列是指在半导体管芯上制造的存储器阵列，其上几乎所有的区域都被存储器单元占据。例如，在图6A-6F中，存储器阵列140下的CMOS晶体管210可以是高压或模拟晶体管，而存储器阵列140上的CMOS晶体管290可以是低电压、短沟道高性能逻辑CMOS晶体管，其在尽可能接近芯片的输入/输出焊盘的物理位置是期望的。
根据本发明的另一实施例，可以使用晶片接合将存储块接合到另一存储块。以此方式，可以在单个芯片上实现高面积密度存储器结构，同时通过最小化所制造的存储器结构的纵横比来简化制造。图7A-7C示出了使用基板300和350的晶片接合来连接存储器块310和360。如图7A所示，CMOS晶体管210连同互连层220和存储器块310被制造在基板300上，而存储器块360被制造在基板350上。然后翻转基板350并将其与基板360晶片接合，使得存储器块310和350电连接，如图7B所示。然后移除基板350并制造互连层370，如图7C所示。
根据本发明的又一实施例，可通过沉积从单晶基板出来的外延硅层来形成用于存储单元晶体管的单晶硅沟道。这样的处理对于具有CuA型CMOS晶体管的存储器块是困难的，因为从基板到存储器阵列的源极/漏极层的“清晰”路径可能不可用。例如，在通过上述引用合并的临时申请II中公开了在薄膜存储晶体管中形成单晶外延硅的示例。特别地，在其它类型的薄膜存储晶体管中，临时申请II公开了一种类型的薄膜存储晶体管，在本文中称为准易失性存储器(QVM)电路”，其具有数据保持时间(例如，100毫秒到一年)，该数据保持时间大于传统动态随机存取存储器(DRAM)电路，小于传统非易失性存储器电路。QVM电路可以例如被组织为NOR存储器字符串的三维阵列。当仅将存储器块构建在硅衬底的顶部时(即，在其下面没有CuA型CMOS晶体管)，为外延硅沉积提供清晰的路径。然后，可以将具有所得到的存储器块的基板晶片接合到已在其上制造了CMOS晶体管的另一基板上。图8A-8E示出了根据本发明的一个实施例的过程，通过该过程，CuA型CMOS晶体管被提供在存储器单元中具有外延单晶硅通道的存储器块下面。
如图8A所示，主动条带的堆叠体(每个主动条带具有源极和漏极层420)首先形成在基板400上，沟槽将相邻的主动条带的堆叠体分隔开来，直至基板400，如图8A所示。然后从基板400的表面402生长从硅基板400出来的外延硅430，如图8B所示，各向异性蚀刻然后从沟槽中基本上移除所有外延硅430，除了留在主动条带的源极层和漏极层之间的凹陷区域中的外延硅沟道440，如图8C所示。然后，存储器块810的制造进行到完成，如图8D所示。(例如，在通过引用并入的同时待审申请中公开了示例性制造工艺。)然后翻转基板400并将其晶片接合到基板450，基板450包含CMOS晶体管210和在其上形成的互连层220，如图8D-8E所示。如前所述，基板400可被移除，并且互连层可被制造在存储器块上方。
提供上述详细描述是为了说明本发明的具体实施例，而不是旨在限制本发明。本发明范围内的许多变化和修改是可能的。本发明在随附的权利要求中阐述。

Claims (15)

1.一种集成电路，包含：
单晶半导体基板；
第一电路集合，其包含形成于该半导体基板中的单晶晶体管；
第一互连层，其包含形成在该电路顶部上的多个导体；以及
第一存储块，其通过该第一互连层的导体与该第一电路集合电连接，其中该第一互连层的导体与该第一存储块通过晶片接合而连接。
2.如权利要求1的集成电路，其中该晶片接合为下列其中之一：热压晶片接合、粘合、阳极与热晶片接合。
3.如权利要求1的集成电路，更包含形成在该第一存储块之上的第二互连层，其中该第二互连层包含多个导体，以及其中该第一互连层与该第二互连层设置于该第一存储块的相对侧上。
4.如权利要求3的集成电路，更包含第二电路集合，其中该第二电路集合包含单晶晶体管，其中该第二电路集合通过该第二互连层的导体电连接至该第一存储块，以及其中该第二电路集合与该第二互连层的导体通过晶片接合而连接。
5.如权利要求4的集成电路，其中该第二电路集合形成于硅层中，且该硅层设置于绝缘层上硅晶片的绝缘层之上。
6.如权利要求5的集成电路，更包含第三互连层，其中该第三互连层包含多个导体，且该第三互连层设置于该绝缘层的与该硅层相对的一侧上，该第二电路集合形成在该硅层上。
7.如权利要求4的集成电路，其中该第一电路集合包含高压或模拟晶体管。
8.如权利要求4的集成电路，其中该第二电路集合由低压、短沟道高性能逻辑互补金属氧化物半导体晶体管形成。
9.如权利要求3的集成电路，更包含第二存储块，其中该第二存储块通过该第二互连层的导体电连接到该第一存储块，以及其中该第二存储块与该第二互连层的导体通过晶片接合而连接。
10.如权利要求1的集成电路，其中该第一存储块包含具有单晶硅沟道材料的存储单元。
11.如权利要求1的集成电路，更包含第二存储块，其中该第二存储块电连接至该第一存储块，以及其中该第一存储块与该第二存储块通过晶片接合而连接。
12.如权利要求11的集成电路，更包含第二互连层，其在该第一存储块的相对侧上形成于该第二存储块的顶部上，其中该第二互连层包含多个导体。
13.如权利要求1的集成电路，其中该第一存储块包含下列其中之一或更多：非易失性存储器字符串阵列与准易失性存储器字符串阵列。
14.如权利要求13的集成电路，其中该第一存储块被组织为三维存储器阵列。
15.如权利要求14的集成电路，其中该三维存储器阵列包含NOR型存储器字符串。
CN201980049198.3A 2018-09-24 2019-09-23 三维nor存储器电路制造中的晶片接合 Pending CN112514067A (zh)

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