CN112567516A - 三维nor存储器阵列的制造方法 - Google Patents

三维nor存储器阵列的制造方法 Download PDF

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CN112567516A
CN112567516A CN201980045255.0A CN201980045255A CN112567516A CN 112567516 A CN112567516 A CN 112567516A CN 201980045255 A CN201980045255 A CN 201980045255A CN 112567516 A CN112567516 A CN 112567516A
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E.哈拉利
S.B.赫纳
W-Y.H.钱
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Sunrise Memory Corp
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Abstract

一种制造三维存储器结构的过程包括：(a)在半导体衬底的平坦表面之上提供一个或多个有源层，每个有源层包括(i)具有第一电导率的第一半导体层和第二半导体层；(ii)将第一半导体层和第二半导体层分离的介电层；以及(ii)一个或多个牺牲层，牺牲层的至少一个与第一半导体层相邻；(b)蚀刻有源层以创建多个有源堆叠体和第一组沟槽，每个沟槽分离且暴露相邻的有源堆叠体的侧壁；(c)由硅氧化物填充第一组沟槽；(d)图案化并蚀刻硅氧化物，以创建各自邻接相邻的有源堆叠体的硅氧化物列并暴露有源堆叠体的一个或多个侧壁的部分；(e)通过各向同性蚀刻穿过有源堆叠体的侧壁的暴露的部分，从侧壁的暴露的部分移除牺牲层，以在有源层中创建对应的腔体。

Description

三维NOR存储器阵列的制造方法
技术领域
本发明涉及非易失性NOR型的存储器串。特别地，本发明涉及用于非易失性NOR型的存储器串的三维阵列的制造过程。
背景技术
在共同未决申请I和II中已经描述了表示一般非易失性存储器单元的阵列的高密度结构。共同未决的申请I和II的存储器阵列被组织为在半导体衬底之上制造的连接的储存晶体管的堆叠体(“有源堆叠体”)。具体而言，共同未决的申请I和II公开了每个有源堆叠体中的半导体层的多个条带(“有源条带”)，每个条带提供被组织为NOR型的存储器串或“NOR存储器串”的储存晶体管。其上构造存储器阵列的半导体衬底包括各种类型的支持电路，诸如电源电路、地址解码器、感测放大器、输入和输出电路、比较器以及控制和其他逻辑电路。
图1a示意性地图示了含有可以使用本发明的方法制造的NOR存储器串的存储器结构100。在该上下文中，NOR存储器串由共享公共源极区域和公共漏极区域的单独且独立可寻址的储存晶体管构成。如在共同未决的申请I和II中所描述，每个存储器串可以沿有源条带的一侧形成，该有源条带包括半导体和导体材料的多层。存储器结构100被组织为m个有源堆叠体，每个有源堆叠体含有n个有源条带，其中m和n可以是任何整数。例如，m可以是1、2、4、8、16、32、64，…，8192或更大。相似地，n可以是1、2、4、8，...，64或更大。
如图1a所示，存储器结构100由有源堆叠体130-(p-1)、130-p、130-(p+1)表示。在每个有源堆叠体中，n个有源条带——标记为101-1、102-1、...、101-n——由隔离层106彼此之间分离且电隔离。隔离层106可以是例如氮化硅。每个有源堆叠体在外部由层电荷储存材料121覆盖，该层电荷储存材料121可以由例如氧化物-氮化物-氧化物(“ONO”)三层提供，如本领域普通技术人员已知的那样。在有源堆叠体之间的空间中提供由电荷储存材料121与有源条带分离的多个导电列(未示出)。这些导电列提供栅极电极，该栅极电极用于在读取、写入和擦除操作期间在相邻的有源堆叠体的任一侧上选择和操作沿有源条带形成的储存晶体管。在下面的详细描述中，为了简化详细描述并且为了参考方便，将实质上垂直于半导体衬底的表面的方向(“垂直”)标记为z，沿每个有源条带的长度的方向标记为y，以及沿每个有源条带的宽度方向标记为x。x和y方向也被称为“水平”。可以在存储器结构100上方或下方形成一个或多个互连层(“全局互连层”)以提供导体，以将储存结构100的NOR存储器串中的储存晶体管的端子互连到半导体衬底中的电路。
典型地，每个有源堆叠体中的一个或多个部分108专用于形成“阶梯”或“反向阶梯”结构，其允许每个有源条带中的半导体或导体材料层中的一个或多个(例如，在有源条带中提供公共漏极区域或“位线”的半导体层)穿过通孔(和埋入式接触件)中的导体从全局互连层进行电存取。在图1a中，在每个有源堆叠体的前面和背面提供部分108(“阶梯部分”)。在一个或多个阶梯部分的外部的每个有源堆叠体中有源条带的一个或多个部分(“一个或多个阵列部分”)中形成储存晶体管。在图1a中，在阶梯部分108之间提供阵列部分109。
图1b示意性地图示了有源条带101的半导体和导体层。如图1b所示，有源条带101包括(i)n+半导体层103和104(例如n型多晶硅)，它们可以为NOR存储器串提供公共源极区域(或“源极线”)和公共漏极区域(或“位线”)；和(ii)本征或轻掺杂的p型(p-)半导体层102，其可以为NOR存储器串的储存晶体管提供沟道区域。在虚线之间的并且由电荷储存材料层121与每个有源条带分离的是假设的导体(未示出)，该导体用作NOR串的储存晶体管的栅极电极。在图1b中的虚线指示导体122-(k-1)、122-k和122-(k+1)(其代表这样的导体)的位置。另外，如图1b所示，在n+半导体层103和104附近提供的导体层105(例如具有粘合和阻挡膜的钨)。导体层105减少NOR存储器串的公共源极区域和公共漏极区域中的电阻。隔离层106(例如，氮化硅)将有源堆叠体中的每个有源条带彼此电隔离。
本发明提供用于制造存储器结构100的期望的有效过程。
发明内容
根据本发明的一个实施例，一种制造三维存储器结构的过程包括：(a)在半导体衬底的平坦表面之上提供一个或多个有源层，每个有源层包括(i)具有第一电导率的第一半导体层和第二半导体层；(ii)将第一半导体层和第二半导体层分离的介电层；以及(ii)一个或多个牺牲层，牺牲层的至少一个与第一半导体层相邻；(b)蚀刻有源层以创建多个有源堆叠体和第一组沟槽，每个沟槽分离且暴露相邻的有源堆叠体的侧壁；(c)由硅氧化物填充第一组沟槽；(d)图案化并蚀刻硅氧化物，以创建各自邻接相邻的有源堆叠体的硅氧化物列并暴露有源堆叠体的一个或多个侧壁的部分；(e)通过各向同性蚀刻穿过有源堆叠体的侧壁的暴露的部分，从侧壁的暴露的部分移除牺牲层，以在有源层中创建对应的腔体；(f)由金属或导体材料填充有源堆叠体中的腔体；(g)使介电层从有源堆叠体的暴露的侧壁凹陷；以及(h)由具有与第一导电率相反的第二导电率的第三半导体层填充介电层中的凹陷。另外，提供隔离层以分离相邻的有源层。
根据一个实施例，该过程还包括使金属或导体层从有源步骤的暴露的侧壁凹陷，其中，填充介电层中的凹陷也填充金属或导体层中的凹陷。
根据一个实施例，该过程还包括：(a)在使介电层凹陷之前移除硅氧化物列，以及(b)在由第二半导体层填充介电层中的凹陷之后，重新创建硅氧化物列。
在一个实施例中，该过程还包括在有源堆叠体的暴露的侧壁之上提供电荷材料，并且通过用导体材料填充由相邻的硅氧化物列和相邻的有源堆叠体围绕的空间来形成字线。第三半导体层包括原位掺杂硼的多晶硅。在该实施例中，(i)每个有源层的第一半导体层和第二半导体层分别形成组织为NOR存储器串的多个储存晶体管的公共漏极区域和公共漏极区域；(ii)第三半导体层形成NOR存储器串中的储存晶体管的沟道区域；以及(iii)字线形成NOR存储器串中的储存晶体管的栅极电极。
根据本发明的一个实施例，一种用于存取三维存储器结构中一个或多个半导体层的阶梯结构，包括：(i)提供第一有源层；(ii)在第一有源层的顶上提供第一隔离层；(iii)在第一隔离层的顶上提供第二有源层，其中，第一有源层和第二有源层各自包括(a)具有第一电导率的第一半导体层；(b)在第一半导体层底下的绝缘材料的介电层；以及(c)在介电层底下的第二半导体层；(iv)在第二有源层的顶上提供第二隔离层；(iv)在第二隔离层之上提供光致抗蚀剂层且将光致抗蚀剂图案化以在光致抗蚀剂层中创建开口，从而暴露第二隔离层的第一区域；(v)各向异性地移除第二隔离层的暴露的第一区域和第二有源层在第二隔离层的第一区域下方的部分，以便暴露第一隔离层的第一区域；(vi)使光致抗蚀剂层凹陷以增大光致抗蚀剂层中的开口，使得暴露第二隔离层的第二区域；(vii)各向异性地移除(a)第一隔离层的暴露的第一区域和第二隔离区域的暴露的第二区域，以及(ii)第一半导体层在第一隔离层的暴露的第一区域和第二隔离区域的暴露的第二区域底下的部分；(viii)使用绝缘材料填充通过(v)和(vii)的各向异性地移除步骤所创建的腔体；(ix)将步骤(i)至(viii)重复预先确定的次数；以及(x)在预先确定的位置处各向异性地移除绝缘材料，以创建到达两个或更多个有源层的第一半导体层的通孔开口。
通过考虑下面的详细描述并结合附图，更好地理解本发明。
附图说明
图1a示意性地图示了含有可以使用本发明的方法制造的类型的NOR存储器串的存储器结构100。
图1b示意性地图示了图1a的存储器结构100中的有源条带101的半导体和导体层。
图2(i)、2(ii)、2(iii)、2(iv)、2(v)和2(vi)图示了根据本发明的一个实施例的存储器结构100的阶梯部分108。
图3(i)是存储器结构100的阵列部分109的x-z平面横截面视图，示出了图案化的光致抗蚀剂层205，其为每个有源堆叠体限定45-nm的宽度，并且为在相邻的有源堆叠体之间的每个沟槽限定65-nm的宽度。
图3(ii)示出了在使用硅氧化物填充沟槽、移除光致抗蚀剂206，且通过CMP平坦化得到的表面之后，具有有源堆叠体207a-207e的得到的存储器结构100。
图3(iii)和3(iv)分别是顶视图和x-z平面横截面视图，示出了在蚀刻沟槽209以形成字线之后得到的存储器结构100。
图3(v)示出了在从有源堆叠体移除SAC4层105s-b和105s-t，从而在它们的位置上创建腔体211之后得到的存储器结构100。
图3(vi)和3(vii)分别是顶视图和x-z平面横截面视图，示出了在使用金属/导体材料填充沟槽209和腔体211之后得到的存储器结构100。
图3(viii)和3(ix)分别是顶视图和x-z平面横截面视图，示出了在金属/导体层105和塞缝(spline)氧化物102o二者都凹陷之后得到的存储器结构100。
图3(x)示出了穿过字线沟槽的x-z平面横截面视图，示出了填充金属/导体层105和塞缝氧化物102o中的凹陷的沟道多晶硅102。
图3(xi)是在将电荷储存材料213和字线214沉积和平坦化之后的存储器结构100的x-z平面横截面视图。
图3(xii)是图示在形成全局互连层之后的存储器结构100的阵列部分108的顶视图。
图4示出了在将字线间隔体列图案化并蚀刻之后的存储器结构100的顶视图。
在该详细的描述中，附图中的相似元件被提供相似的附图标记，以便于参考附图中的特征。
具体实施方式
本发明提供了用于制造含有NOR存储器串的阵列的存储器结构的有效过程。在下面的详细描述中，每个步骤的参数(例如，温度、压力、前驱物、组分和尺寸)仅出于示例性目的来提供。在考虑了该详细的描述时，本领域普通技术人员将能够在不脱离本发明范围的情况下修改或改变这些参数。
根据本发明的一个实施例，提供了一种过程，通过该过程可以在半导体衬底的平坦表面之上形成含有NOR存储器串的存储器结构。最初，各种类型的支持电路可以形成在半导体衬底中或半导体衬底的表面处(例如，制造电源电路、地址解码器、感测放大器、输入和输出电路、比较器以及控制和其他逻辑电路)。
隔离层(例如，硅氧化物)可以形成在平坦表面上。埋入式接触件可以形成在隔离层中形成，用于连接到底下的电路。一个或多个全局互连层然后可以形成在隔离层上方。(在下面的详细描述中，这些层共同地被称为衬底150。)
此后，提供基础氧化物膜107(例如50-nm的硅氧化物膜)。然后提供有源条带的半导体层和导体层(共同地作为“有源层”)。可以逐层提供多个有源层，每个有源层通过隔离膜106(例如30-nm的氮化物层)与下一个有源层隔离。在一个实施例中，在沉积的顺序中，每个有源层可以包括(a)牺牲层105s-b(“SAC4层105s-b”；例如，40-nm的锗化硅的层)；以及(b)n+掺杂的多晶硅层104(“漏极多晶硅104”；例如30nm的原位掺杂砷的多晶硅膜)；(c)硅氧化物层102o(“塞缝氧化物102o”；80-nm的硅氧化物膜)；(d)n+多晶硅层103(“源多晶硅103”；例如，30-nm的原位(in situ)掺杂砷的多晶硅膜)；(e)牺牲层105s-t(“SAC4层105s-t”；例如，40-nm的锗化硅的层)。SAC4层105s-b和105s-t是各自随后将由金属导体层替换的牺牲层，如下所描述。
在有源层的沉积期间，在阶梯部分108中形成了用于电存取要形成的每个有源条带的漏极多晶硅104的阶梯结构。由阵列部分109上方的掩模保护阵列部分109免受阶梯形成步骤的影响。根据本发明，可以对每两个有源层使用一个光刻步骤来形成阶梯结构。图2(i)至2(vi)图示了根据本发明的一个实施例的在存储器结构100的阶梯部分108中的阶梯结构形成。
图2(i)示出了在沉积有源层101-1和101-2之后的存储器结构100。此后，将光致抗蚀剂层201沉积和图案化在存储器结构100之上。第一蚀刻步骤从不受光致抗蚀剂201保护的区域中逐个膜地移除(a)隔离层106和(b)有源层101-2(即，“有源层101-2的SAC4层105s-tb，源极多晶硅103，塞缝氧化物102o，漏极多晶硅104和SAC4层105s-b)。该第一蚀刻步骤在紧接有源层101-1上方的隔离106处停止。得到的结构在图2(ii)中示出。
然后，将光致抗蚀剂层201凹陷以进一步暴露有源层101-2的附加区域。得到的结构在图2(iii)中示出。此后，第二蚀刻步骤从紧接有源层101-1和101-2上方的隔离膜106的暴露的部分移除(a)两个有源层101-1和101-2的SAC4层105s-t，以及(b)有源层101-1和101-2的源极多晶硅103。该第二蚀刻步骤在两个有源层101-1和101-2两者的塞缝氧化物层102o处停止。作为两个台阶的阶梯结构的得到的结构在图2(iv)中示出。然后移除光致抗蚀剂层201。
然后提供硅氧化物202以填充由第一蚀刻步骤和第二蚀刻步骤创建的腔体。随后的平坦化步骤(例如，化学机械抛光(CMP))使得到的表面平坦化。得到的结构在图2(v)中示出。然后可以在硅氧化物202以及有源层101-1和101-2中的每一个的下卧的塞缝氧化物102o中创建通孔，以允许存取有源层101-1和101-2中的每一个的漏极多晶硅104。如下所讨论，在沉积所有有源层之后的随后的氧化物蚀刻中创建这些通孔。
每两个沉积的有源层重复结合图2(i)至2(v)讨论的步骤。注意到，结合图2(i)至2(v)讨论的这些阶梯形成步骤需要每两个沉积的有源层一个光刻步骤，这比先前使用的阶梯形成步骤更有利，该先前使用的阶梯形成步骤对于每个沉积的有源需要一个光刻步骤。
在将存储器结构100的所有有源层沉积并且填充来自最后两个有源层上的最近的第一蚀刻步骤和第二蚀刻步骤的腔体之后，可以在适当的时间执行氧化物蚀刻以创建到达每个有源层的漏极多晶硅层104的通孔。得到的结构在图2(vi)中示出。在图2(vi)和下面讨论的每个图中，仅出于示例性目的，示出了四个有源层101-1、101-2、101-3和101-4。在图2(vi)中，通孔203-1、203-2、203-3和203-4是对可以被创建以存取存在的有源层的半导体和导体材料层的通孔图示说明的通孔。本领域普通技术人员将理解，本发明适用于具有期望的任何数目的有源层和通孔的任何结构。当用导体材料(例如钨或p+多晶硅)填充时，这些通孔穿过要在存储器结构100上方形成的一个或多个全局互连层中的导体在漏极多晶硅104与半导体衬底150中的电路之间提供电连接。
在沉积所有有源层之后，在阵列部分109中的有源层之上提供硬掩模层205。提供并图案化光致抗蚀剂层206，以限定有源堆叠体及有源堆叠体之间的沟槽。图3(i)是存储器结构100的阵列部分109的x-z平面横截面视图，示出了图案化的光致抗蚀剂层206，其为每个有源堆叠体限定45-nm的宽度，并且为在相邻的有源堆叠体之间的每个沟槽限定65-nm的宽度。穿过不受光致抗蚀剂层206保护的硬掩模层205和有源层的蚀刻创建有源堆叠体及有源堆叠体之间的沟槽。然后沉积硅氧化物208以填充沟槽。图3(ii)示出了在使用硅氧化物填充沟槽、移除光致抗蚀剂206且由CMP平坦化之后得到的存储器结构100，其具有有源堆叠体207a至207e。除非指定，否则图3(i)-3(xii)中的所有x-z平面横截面视图都是在存储器结构100的阵列部分109中制成的。
然后将二硅氧化物208图案化并蚀刻，以限定随后要由导体填充的沟槽(“字线沟槽”)。剩余的硅氧化物208(“硅氧化物列”)在相邻的字线导体之间提供电绝缘。图3(iii)和3(iv)分别是顶视图和x-z平面横截面视图，示出了在蚀刻字线沟槽209之后得到的存储器结构100。在图3(iii)和3(iv)中，字线沟槽和剩余的氧化物列均为65nm宽。图3(iv)的横截面沿图3(iii)所示的虚线A-A'截取。
接下来，通过选择性各向同性蚀刻技术移除每个有源层中分别与源极多晶硅103和漏极多晶硅104相邻的牺牲SAC4层105s-t和105s-b。从字线沟槽209横向地继续进行各向同性蚀刻，直到移除SAC4层105s-t和105s-b中的所有牺牲材料。在该过程期间，硅氧化物列向有源堆叠体(例如，图3(iv)的有源堆叠体207a-207e)提供机械支撑。图3(v)示出了在从有源堆叠体中移除所有SAC4层105s-b和105s-t，从而在它们的位置上创建腔体211之后得到的存储器结构100。
然后使用金属/导体材料填充腔体211和字线沟槽209。可以通过例如阻挡材料(例如，氮化钨或氮化钛)和钨的连续沉积来提供金属/导体材料。图3(vi)和3(vii)分别是顶视图和x-z平面横截面视图，示出了在使用金属/导体材料填充字线沟槽209和腔体211之后得到的存储器结构100。在图3(vii)中，有源条带中的腔体211由金属/导体层305替换。图3(vii)的x-z平面横截面视图沿图3(vi)所示的虚线B-B'截取。
此后，各向异性蚀刻从字线沟槽移除金属/导体材料305。在一个实施例中，在由金属/导体层305替换SAC4层之后，硅氧化物列208继续提供机械支撑。替代地，此时可以由各向异性氧化物移除硅氧化物列。
然后可以进行选择性的各向同性蚀刻以使金属/导体层105和塞缝氧化物102o凹陷。在一个实施例中，选择性各向同性蚀刻使每个金属/导体层305从有源堆叠体的侧壁凹陷5-6nm。各向同性氧化物蚀刻使塞缝氧化物102o从有源堆叠体的侧壁凹陷例如5-6nm。如果不移除硅氧化物列208，则各向同性氧化物蚀刻还使硅氧化物列208的暴露的侧壁沿y方向在每一侧上凹陷相同的量。图3(viii)和3(ix)分别是顶视图和x-z平面横截面视图，示出了在金属/导体层305和塞缝氧化物102o二者都凹陷之后得到的存储器结构100。图3(viii)涉及其中保留硅氧化物列208的实施例。
轻掺杂的p-多晶硅(“沟道多晶硅102”)可以然后被沉积以填充在金属/导体层305和塞缝氧化物102o两者中的凹陷以及字线沟槽。可以跟随沟道多晶硅102的各向异性蚀刻以从字线沟槽209移除沟道多晶硅102。可以通过沉积具有例如5.0×1018cm-3的掺杂物浓度的原位掺硼的多晶硅来提供沟道多晶硅102。图3(x)是穿过字线沟槽209的x-z平面横截面视图，示出了填充金属/导体层305和塞缝氧化物102o中的凹陷的沟道多晶硅102。在各向同性氧化物蚀刻之前不移除硅氧化物列208的一个缺点是在硅氧化物列208后面的塞缝氧化物102o的部分受到保护且不会凹陷。因此，在有源条带上沉积的沟道多晶硅102沿y方向不是连续的，并且有源条带上的每个存储器单元具有沟道多晶硅的非常小的分开的、离散的区域，这可能无法在储存晶体管操作(例如，擦除操作)期间有效提供足够的电荷载流子。
如果如上所讨论的在由金属/导体层305替换SAC4层105s-t和105s-t之后移除硅氧化物列208，则此时可以通过使用硅氧化物填充在相邻的有源堆叠体之间的沟槽(由移除硅氧化物列208产生)、图案化并蚀刻硅氧化物，来提供字线间隔体列。得到的字线间隔体列是相似的，并且它们如果已经被保留，则被称为前向硅氧化物列208。图4示出了在将字线间隔体列图案化和形成之后的存储器结构100的顶视图。为了简化下面的详细描述，在处理的剩余部分中，可以将这些字线间隔体列与硅氧化物列208相同地处理。因此，这些字线间隔体列也被标记为208，并且在本详细描述的剩余部分中在这两组列之间没有其他区别。
然后可以沉积电荷储存材料213，其与字线沟槽209的侧壁共形地排列。可以通过连续(按顺序)沉积：2-nm厚的隧道氧化物、6-nm厚的富硅氮化物、6-nm厚的硅氧化物和2-nm厚的铝氧化物(Al2O3)，来实现电荷储存材料213。此后，衬有电荷储存材料的字线沟槽209然后可以由导体材料214(例如，p+多晶硅)填充以提供字线。然后由CMP平坦化可以从存储器结构100的顶表面移除多余的电荷储存材料213和导体材料214。图3(xi)是在已经将电荷储存材料213和字线214沉积和平坦化之后的存储器结构100的x-z平面横截面视图。
可以将缓冲氧化物215沉积在存储器结构100之上，将缓冲氧化物215图案化并蚀刻以向缓冲氧化物215下方的字线214提供接触通孔。这些接触通孔可以由钨填充(“钨插头”)。还可以在阶梯部分108中形成的通孔中同时提供钨插头，以接触漏极多晶硅或位线104。可以在存储器结构100上方提供全局互连线，以随后将字线214和位线104互连到半导体衬底150中的电路。图3(xii)示出了存储器结构100的阵列部分108的部分的顶视图。如图3(xii)所示，由全局互连线216到字线214的连接是错开的(即，全局互连线216中的每一个连接字线214中的每隔一个；其他全局互连线连接沿第一全局互连线上剩余的字线排列)。
提供以上详细描述以说明本发明的特定实施例，并且不旨于限制以上详细描述。在本发明范围内的许多改变和修改是可能的。本发明在所附权利要求中提出。

Claims (9)

1.一种过程，包括：
在半导体衬底的平坦表面之上提供一个或多个有源层，每个有源层包括(i)具有第一电导率的第一半导体层和第二半导体层；(ii)将所述第一半导体层和第二半导体层分离的介电层；以及(ii)一个或多个牺牲层，牺牲层的至少一个与所述第一半导体层相邻；
蚀刻所述有源层以创建多个有源堆叠体和第一组沟槽，所述第一组沟槽的每一个分离且暴露相邻的有源堆叠体的侧壁；
由硅氧化物填充所述第一组沟槽；
图案化并蚀刻所述硅氧化物，以创建各自邻接相邻的有源堆叠体的硅氧化物列并暴露所述有源堆叠体的一个或多个侧壁的部分；
通过各向同性蚀刻穿过所述有源堆叠体的侧壁的暴露的部分，从所述侧壁的暴露的部分移除所述牺牲层，以在所述有源层中创建对应的腔体；
由金属或导体材料填充所述有源堆叠体中的腔体；
使所述介电层从所述有源堆叠体的暴露的侧壁凹陷；以及
由具有与所述第一导电率相反的第二导电率的第三半导体层填充所述介电层中的凹陷。
2.根据权利要求1所述的过程，其中，相邻的有源层由隔离层分离。
3.根据权利要求1所述的过程，还包括使所述金属或导体层从所述有源步骤的暴露的侧壁凹陷，其中，填充所述介电层中的凹陷也填充所述金属或导体层中的凹陷。
4.根据权利要求1所述的过程，还包括：
在使所述介电层凹陷之前移除所述硅氧化物列，以及
在由所述第二半导体层填充所述介电层中的凹陷之后，重新创建所述硅氧化物列。
5.根据权利要求1所述的过程，还包括在所述有源堆叠体的暴露的侧壁之上提供电荷材料。
6.根据权利要求1所述的过程，还包括通过用导体材料填充由相邻的硅氧化物列和相邻的有源堆叠体围绕的空间来形成字线。
7.根据权利要求6所述的过程，其中，所述第三半导体层包括原位掺杂硼的多晶硅。
8.根据权利要求7所述的过程，其中，(i)每个有源层的所述第一半导体层和第二半导体层分别形成组织为NOR存储器串的多个储存晶体管的公共漏极区域和公共漏极区域；(ii)所述第三半导体层形成所述NOR存储器串中的储存晶体管的沟道区域；以及(iii)所述字线形成所述NOR存储器串中的储存晶体管的栅极电极。
9.一种过程，包括：
(i)提供第一有源层；
(ii)在所述第一有源层的顶上提供第一隔离层；
(iii)在所述第一隔离层的顶上提供第二有源层，其中，所述第一有源层和第二有源层各自包括(a)具有第一电导率的第一半导体层；(b)在所述第一半导体层底下的绝缘材料的介电层；以及(c)在所述介电层底下的第二半导体层；
(iv)在所述第二有源层的顶上提供第二隔离层；
(iv)在所述第二隔离层之上提供光致抗蚀剂层且将所述光致抗蚀剂图案化以在所述光致抗蚀剂层中创建开口，从而暴露所述第二隔离层的第一区域；
(v)各向异性地移除所述第二隔离层的暴露的第一区域和所述第二有源层在所述第二隔离层的第一区域下方的部分，以便暴露所述第一隔离层的第一区域；
(vi)使所述光致抗蚀剂层凹陷以增大所述光致抗蚀剂层中的所述开口，使得暴露所述第二隔离层的第二区域；
(vii)各向异性地移除(a)所述第一隔离层的暴露的第一区域和所述第二隔离区域的暴露的第二区域，以及(ii)所述第一半导体层在所述第一隔离层的暴露的第一区域和所述第二隔离区域的暴露的第二区域底下的部分；
(viii)使用所述绝缘材料填充通过(v)和(vii)的各向异性地移除步骤所创建的腔体；
(ix)将步骤(i)至(viii)重复预先确定的次数；以及
(x)在预先确定的位置处各向异性地移除所述绝缘材料，以创建到达两个或更多个有源层的所述第一半导体层的通孔开口。
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CN203760476U (zh) * 2014-02-26 2014-08-06 唐棕 半导体器件

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WO2024012084A1 (zh) * 2022-07-14 2024-01-18 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
WO2024087353A1 (zh) * 2022-10-27 2024-05-02 武汉新芯集成电路制造有限公司 存储块及其制程方法、存储单元

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