CN102610615A - 三维nor型阵列的存储器装置 - Google Patents
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- 230000015654 memory Effects 0.000 title claims abstract description 149
- 239000004065 semiconductor Substances 0.000 claims abstract description 135
- 238000003475 lamination Methods 0.000 claims description 90
- 238000003860 storage Methods 0.000 claims description 50
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 239000011810 insulating material Substances 0.000 claims description 13
- 238000013459 approach Methods 0.000 claims 1
- 238000003491 array Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 25
- 239000010410 layer Substances 0.000 description 84
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 47
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 20
- 229920005591 polysilicon Polymers 0.000 description 20
- 239000000377 silicon dioxide Substances 0.000 description 20
- 239000011232 storage material Substances 0.000 description 20
- 238000012545 processing Methods 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- 235000012239 silicon dioxide Nutrition 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 238000005530 etching Methods 0.000 description 13
- 108091006146 Channels Proteins 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 239000002131 composite material Substances 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 239000000284 extract Substances 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 239000002784 hot electron Substances 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000007667 floating Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000012856 packing Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000002070 nanowire Substances 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002071 nanotube Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910001930 tungsten oxide Inorganic materials 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 208000004350 Strabismus Diseases 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 125000003963 dichloro group Chemical group Cl* 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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Abstract
本发明公开了一种三维存储器装置。该三维存储器装置包括多个脊形的存储器单元的叠层。字线排列在存储器单元的叠层的上方。位线结构耦合至沿着存储器的叠层的多重位置。源极线结构耦合至沿着叠层的每个半导体材料条状物的多重位置。位线结构及源极线结构位于字线中相邻的字线之间。
Description
技术领域
本发明主张在2011年1月19日提出的美国临时专利申请第61/434,221号的优先权,且在此结合参照该美国临时专利申请。
本发明有关于高密度存储器装置,尤其是关于存储器装置中存储器单元的多重平面的排列以提供一三维(three-dimensional,3D)阵列。
背景技术
当装置在集成电路的关键维度缩小至一般存储器单元技术的限制时,设计者一直在寻找用于叠层存储器单元的多重平面的技术,以达到更大的存储容量,且达到降低每位的成本。举例而言,在Lai等人的“AMulti-Layer Stackable Thin-Film Transistor(TFT)NAND-Type FlashMemory,”IEEE Int′l Electron Devices Meeting,11-13 Dec.2006,以及在Jung等人的“Three Dimensionally Stacked NAND Flash MemoryTechnology Using Stacking Single Crystal Si Layers on ILD and TANOSStructure for Beyond 30nm Node”,IEEE Int′l Electron Devices Meeting,11-13 Dec.2006的文献中,薄膜晶体管技术应用于电荷捕捉存储器技术。
同时,在Johnson等人的“512-Mb PROM With a Three-DimensionalArray of Diode/Anti-fuse Memory Cells”IEEE J.of Solid-State Circuits,vol.38,no.11,Nov.2003.的文献中,交叉点阵列(cross-point array)技术已应用于抗熔丝存储器(anti-fuse memory)。在Johnson等人所述的设计中,在交叉点提供存储器元件给多层的字线与位线。存储器元件包括连接至字线的p+多晶硅阳极以及连接至位线的n多晶硅阴极,且由抗熔丝材料分隔阳极与阴极。
在Lai等人、Jung等人及Johnson等人所述的处理中,对于每个存储层而言有多个关键光刻步骤。因此,制造装置所需要的关键光刻步骤的数量,为所要实行的层状物的数量的倍数。因此,虽然使用三维阵列可达成较高密度的优点,但较高的制造成本却限制了此技术的使用。
Tanaka等人的“Bit Cost Scalable Technology with Punch and PlugProcess for Ultra High Density Flash Memory”,2007 Symposium on VLSITechnology Digest of Technical Papers;12-14 June 2007,pages:14-15的文献所述的另一种结构,提供在电荷捕捉存储器技术中的垂直NAND型单元。Tanaka等人所述的结构中,包含多栅极场效晶体管结构。此多栅极场效晶体管结构具有操作如NAND型栅极的垂直通道,并使用硅-氧化硅-氮化硅-氧化硅-硅(Silicon-Oxide-Nitride-Oxide-Silicon,SONOS)电荷捕捉技术,以在每个栅极/垂直通道接口产生存储点。此存储器结构是基于将半导体材料的柱状物排列为多栅极单元的垂直通道,此多栅极单元具有相邻于衬底的较低选择栅极以及在顶端的较高选择栅极。使用与柱状物相交的平面电极层来形成多个水平控制栅极。使用在控制栅极的平面电极层因无需关键光刻工艺,从而节省成本。然而,每个垂直单元则需要许多关键光刻步骤。而且能以此方法层叠的控制栅极在数量上存在有限制,此限制由如垂直通道的导电性、所使用的编程与擦除处理及其它的因素决定。
因此希望提供一种用于具有低制造成本的三维集成电路存储器的结构,包含可靠的、非常小的存储器元件以及增进的处理窗口,此处理窗口与具有栅极结构的存储器单元条状物的邻近的叠层相关。
发明内容
在各种实施例中,存储器架构实行三维NOR型阵列。
三维存储器装置包含多个脊形叠层,以由绝缘材料分隔的多重半导体材料条状物所形成,且在此所述的实施例中排列为存储器单元串,此存储器单元串能通过译码电路耦合至感测放大器。
半导体材料条状物在脊形叠层的侧面具有侧表面。多个字线正交地延伸在多个脊形叠层的上方,且能耦合至列(row)译码器。字线具有叠层及字线的表面。存储器元件为可编程且为非易失性的,如同下方所述的实施例中的可编程电阻结构或电荷捕捉结构。存储器元件也可以如下述为可编程且为易失性的。在叠层内,共形的字线的组合(The combination of theconformal word line)、存储器元件及半导体条状物形成存储器单元的叠层。故此阵列结构,提供为存储器单元的三维阵列。
多个字线结构耦合至沿着多个叠层的每个半导体材料条状物的多重位置。而且,多个源极线结构耦合至沿着多个叠层的每个半导体材料条状物的多重位置。多个字线结构及多个源极线结构位于多个字线中的相邻的字线之间。许多实施例被称为NOR型排列。
能制作多个脊形叠层及多个字线以使存储器单元自对准。举例而言,能使用单一刻蚀掩模定义在脊形叠层中的多个半导体条状物,而导致交错且能相对加深的沟道的形成以及叠层的形成,其中半导体条状物的侧表面为垂直对齐,或者对齐于由刻蚀所造成的脊形物的倾斜侧面。能使用在多个叠层上方进行地毯式沉积处理(blanket deposition processes)而制作的单层或多层的材料,且使用其它非关键对齐步骤的处理,来形成存储器元件。而且,能在用来提供存储器元件的材料的此单层或多层的上方使用共形沉积(conformal deposition),接下来通过使用单一刻蚀掩模的刻蚀处理来定义线条,而形成多个字线。因此,能仅使用对于多个叠层中的半导体条状物的单一对齐步骤,以及使用对于多个字线的单一对齐步骤,构建出自对准的存储器单元的三维阵列。
多个位元线中的特定位线、多个源极线中的特定源极线及多个字线中的特定字线的组合的选择,识别特定的存储器元件。
许多实施例包括紧接于多个字线结构的二极管。如此的二极管防止逸散电流流入如未选择的位线的下侧路径。在一实施例中,半导体材料条状物包括二极管的n型硅,且二极管包括条状物中的p型区域。在另一实施例中,半导体材料条状物包括二极管的n型硅,且二极管包括与半导体材料条状物接触的p型插头。
一些实施例中,包括阶梯结构,将多条源极线结构耦合至多条源极线。
此技术的另一实施形式为存储器装置,包括集成电路衬底、包含NOR型存储器单元的叠层且在集成电路衬底上的存储器单元的三维阵列、排列于NOR型存储器单元的叠层上方的多条字线、耦合至沿着NOR型存储器单元的叠层的多重位置的多个字线结构、耦合至沿着多个叠层的每个半导体材料条状物的多重位置的多个源极线结构。多个字线结构及多个源极线结构位于多条字线中的相邻的字线之间。
此发明的另一实施例为运算三维存储器阵列的方法,包括:
在三维阵列中对NOR型存储器单元的相邻的叠层施加偏压,包含:
对位线施加偏压,此位线经由二极管耦合至沿着NOR型存储器单元的叠层的多重位置。
本发明的其它实施例及有益效果能在下述的附图、具体实施方式及权利要求中看到。
附图说明
图1绘示三维存储器结构的立体图,作为描述在本文的三维存储器结构,包含平行于Y轴且排列于多个脊状叠层中的半导体条状物的多个平面,包含位于半导体条状物的侧表面上的存储层,以及包含与排列于多个脊形叠层上方的底表面共形的多个字线。
图2绘示从图1的结构中沿X-Z平面提取的存储器单元的剖视图。
图3绘示从图1的结构中沿X-Y平面提取的存储器单元的剖视图。
图4绘示集成电路的概要图,集成电路包含具有列、行及平面译码电路的三维暂存存储器阵列。
图5绘示三维NOR型闪存结构的立体图,作为描述于本文的三维存储器结构,包含平行于Y轴且排列于多个脊状叠层中的半导体条状物的多个平面,包含位于半导体条状物的侧表面上的电荷捕捉存储层,以及包含与排列于多个脊形叠层上方的底表面共形的多个字线。
图6绘示从图5的结构中沿X-Z平面提取的存储器单元的剖视图。
图7绘示从图5的结构中沿X-Y平面提取的存储器单元的剖视图。
图8绘示集成电路的概要图,集成电路包含具有列、行及平面译码电路的三维NOR型闪存阵列。
图9绘示如图5的三维NOR型闪存结构的另外实施方式,在其中移除字线间的存储层。
图10绘示从图9的结构中沿X-Z平面提取的存储器单元的剖视图。
图11绘示从图9的结构中沿X-Y平面提取的存储器单元的剖视图。
图12绘示用于制造如图1、图5、图9的存储器装置的处理中的第一阶段。
图13绘示用于制造如图1、图5、图9的存储器装置的处理中的第二阶段。
图14A绘示用于制造如图1的存储器装置的处理中的第三阶段。
图14B绘示用于制造如图5的存储器装置的处理中的第三阶段。
图15绘示用于制造如图1、图5、图9的存储器装置的处理中的第三阶段。
图16绘示用于制造如图1、图5、图9图的存储器装置的处理中的第四阶段,接下来为硬掩模及可选的注入步骤的进一步的阶段。
图17绘示三维NOR型闪存阵列结构的立体图。
图18绘示三维NOR型闪存阵列结构的简化布局图。
图19绘示阶梯结构的实施例,为将三维存储器的不同的层状物电性耦合至不同的源极线。
图20绘示阶梯结构的另一实施例,为将三维存储器的不同的层状物电性耦合至不同的源极线。
图21绘示如图17所示且在所选择的存储器单元执行编程运算的三维NOR型闪存阵列结构的立体图。
图22绘示如图17所示且在所选择的存储器单元执行读取运算的三维NOR型闪存阵列结构的立体图。
图23绘示如图17所示且在所选择的存储器单元执行擦除运算的三维NOR型闪存阵列结构的立体图。
图24绘示已经制造且测试的八层垂直栅极、薄膜晶体管、BE-SONOS电荷捕捉装置的局部剖视图。
【主要元件符号说明】
10、110、210、212、214:绝缘层
11、12、13、14、111、112、113、114:半导体条状物
15、115、215、315:层状物
16、17、116、117、260:字线
18、19、118、119:硅化物层
20、120、220:沟道
21、22、23、24、121、122、123、124:绝缘材料
25、26、125、126:主动区域
97:隧穿介电层
98:电荷存储层
99:阻挡介电层
110A:表面
113A、114A:侧表面
128、129、130:源极/漏极
128a、129a、130a:区域
211、213:半导体层
225:层状物
226:硅化物层
250:叠层
397:隧穿介电层
398:电荷存储层
399:阻挡介电层
858、958:平面译码器
859、959:源极线
860、960:存储器阵列
861、961:列译码器
862、962:字线
863、963:行译码器
864、964:位线
865、965:总线
866、966:方块
867、967:数据总线
868、968:方块
869、969:偏压安排状态装置
871、971:数据输入线
872、972:数据输出线
874、974:其它电路
875、975:集成电路
具体实施方式
实施例的详细实施方式请参照图1至图23。
图1为三维可编程电阻存储器阵列的2×2局部的立体图,其中,从图中移除填充材料,以给予构成三维阵列的半导体条状物的叠层以及正交字线的视图。在此附图中,仅显示二平面。然而,平面的数量能被延伸至非常大的数量。如图1所示,在集成电路衬底上形成存储器阵列,集成电路衬底设置于位于下方的半导体或其它结构(未在图中绘示)的上方并具有绝缘层10。存储器阵列包含由绝缘材料21、22、23、24分隔的半导体条状物11、12、13、14的多个叠层。如图所示,叠层为延伸于Y轴的脊形,以使半导体条状物11至14能配置成存储器单元串。半导体条状物11及13能作用为第一存储器平面中的存储器单元串。半导体条状物12及14能作用为第二存储器平面中的存储器单元串。如暂存存储器材料的存储器材料层状物15,在此实施例中为涂布于多个半导体条状物的叠层,且在其它实施例中至少涂布于半导体条状物的侧壁。多个字线16、17正交地排列于半导体条状物的多个叠层的上方。字线16、17具有表面与半导体条状物的多个叠层共形,且填充由多个叠层定义的沟道(例如,元件符号20),并在叠层上的半导体条状物11至14的侧表面以及字线16、17间的交叉点定义接口区域多层阵列。硅化物(例如,钨硅化物、钴硅化物、钛硅化物)层18、19能形成在字线16、17的顶表面的上方。
在一实施例中,存储器材料层状物15能由如薄栅极氧化物(<5nm)的暂存存储器材料组成,以使装置为具有浮动本体的1T的MOSFET。如此能作为一动态随机存取存储器(dynamic random access memory,DRAM)使用。
在另一实施例,存储器材料层状物15能由如二氧化硅、氮氧化硅或其它氧化硅的抗熔丝材料组成,例如具有1至5纳米等级的厚度。
半导体条状物11至14能为具有第一导电型(例如,p型)的半导体材料。字线16、17能为具有第二导电型(例如,n型)的半导体材料。举例而言,半导体条状物11至14能使用p型多晶硅来制作,同时字线16、17能使用相对重地掺杂的n+型多晶硅来制作。半导体条状物的宽度应要足够宽到提供用于耗尽区域(depletion region)的空间,以支持二极管操作。因此,包括由p-n结所形成的整流器且在阳极与阴极间具有存储器材料层状物的存储器单元,为形成于多晶硅条状物与线状物间的交叉点的三维阵列中。在其它实施例中,能使用包含过渡金属氧化物的不同的存储器材料,如钨上氧化钨或经掺杂的金属氧化物半导体条状物。如此的材料能被编程及被擦除,且能被用于实行于每单元中存储多位的运算。
图2绘示形成于字线16及半导体条状物14的相交处的存储器单元,沿X-Z平面切取的剖视图。主动区域25、26形成于条状物14的两侧且位于字线16及条状物14之间。
在DRAM应用中,层状物15具有暂存存储器材料。在例如通过通道热电子(channel hot electron,CHE)编程而进行编程之后,在很短的时间中在衬底内产生碰撞离子。
在可编程电阻式存储器的应用中,在原始状态下,暂存存储器材料层状物15及抗熔丝材料具有高电阻。在编程后,抗熔丝材料击穿(breaksdown),而造成在抗熔丝材料内中的一个或二个主动区域25、26呈现低电阻状态。
在描述于此的实施例中,每个存储器单元具有二个主动区域25、26,其中一个区域在半导体条状物14的各个侧面上。图3绘示形成于字线16、17及半导体条状物14的相交处的存储器单元,沿X-Y平面提取的剖视图。说明来自通过字线16定义的字线的电流路径,通过存储器材料层状物15,向下流至半导体条状物14。
在图3中以实心箭头所示的电流,从n+字线16流入p型半导体条状物,且沿着半导体条状物(虚线箭头)流至感测放大器,而能被测量并指出所选择的存储器单元的状态。
典型的暂存存储器偏压将伴随三维立体图而讨论于下,且讨论通过如通道热电子(channel hot electron,CHE)编程而进行的编程,来产生碰撞离子。
在典型的可编程电阻式存储器实施例中,使用厚度与抗熔丝材料相同的氧化硅层约1纳米厚,编程脉冲能包括5至7伏特脉冲,且具有约1微秒的脉冲宽度,而在如下参照图17所述的晶载(on-chip)控制电路的控制下被施加。读取脉冲能包括依据配置的脉冲宽度,而在晶载控制电路的控制下被施加。读取脉冲能远短于编程脉冲。
图4为根据本发明的实施例的集成电路的简化的方块图。在此所述实行的NOR型排列中,集成电路线875在半导体衬底上,包含三维动态随机存取存储器阵列860(DRAM)。另一实施例为可编程电阻存储器阵列860(RRAM)。列(row)译码器861耦合至多条字线862,且沿着存储器阵列860中的列来排列。行(column)译码器863耦合至位线864,且沿着存储器阵列860中对应叠层的行来排列,以从阵列860中的存储器单元读取及编程数据。平面译码器858通过源极线859耦合至存储器阵列860中的多个平面中。在总线865上,将地址供给至行译码器863、列译码器861及平面译码器858。在此实施例中,方块866中的感测放大器及数据输入结构,通过数据总线867耦合至行译码器863。从集成电路875上的输入/输出端口,或从集成电路875的内部或外部的其它数据来源,通过数据输入线871,将数据供给至方块866中的数据输入结构。在所述的实施例中,集成电路上包含其它电路874,例如一般目的的处理器或特殊目的应用电路,或者提供由存储器阵列所支持的系统单芯片功能的模块的组合。从方块866中的感测放大器,通过数据输出线872,将数据供给至集成电路875上的输入/输出端口,或者供给至集成电路875的内部或外部的其它数据标的。
使用偏压安排状态装置869而实行于此实施例中的控制器,此控制器控制经由电压供应器或在方块868中的供应器所产生或所提供的偏压安排供给电压的施加,例如读取电压及编程电压。控制器能使用如现有技术的特殊目的逻辑电路来实行。在另外实施例中,控制器包括一般目的的处理器,此处理器能实行在相同的集成电路上,此集成电路执行计算机程序以控制装置的运算。在其它实施例中,特殊目的逻辑电路及一般目的的处理器的组合能被使用在此控制器的实行。
图5为三维电荷捕捉存储器阵列的2×2局部的立体图,其中,从图中移除填充材料,以给出构成三维阵列的半导体条状物的叠层以及正交字线的视图。在此附图中,仅显示二平面。然而,平面的数量能被延伸至非常大的数量。如图5所示,在集成电路衬底上形成存储器阵列,集成电路衬底设置于位于下方的半导体或其它结构(未再图中绘示)的上方并具有绝缘层110。存储器阵列包含由绝缘材料121、122、123、124分隔的半导体条状物111、112、113、114的多个叠层(附图中绘示二个)。如图所示,叠层为延伸于Y轴的脊形,以使半导体条状物111至114能配置成存储器单元串。半导体条状物111及113能作用为在第一存储器平面中的存储器单元串。半导体条状物112及114能作用为在第二存储器平面中的存储器单元串。
第一叠层中在半导体条状物111及112之间的绝缘材料121,以及第二叠层中在半导体条状物113及114之间的绝缘材料123,具有约40纳米或更厚的有效氧化物厚度(effective oxide thickness,EOT),其中此有效氧化物厚度,根据二氧化硅的介电常数以及所选择的绝缘材料的介电常数的比例,而为一正规化的绝缘材料的厚度。使用于此的术语「约40纳米」,为认定有大约10%等级的变化,此通常发生在此类型的制造结构中。绝缘材料的厚度能担任关键角色,以减少结构的相邻层状物中的单元间的干涉。在一些实施例中,当达成层状物间的重要隔绝时,此绝缘材料的EOT能与30nm一样薄。
如介电电荷捕捉结构的存储器材料层状物115,在此实施例中为涂布于多个半导体条状物的叠层。多个字线116、117正交地排列于半导体条状物的多个叠层的上方。字线116、117具有表面与半导体条状物的多个叠层共形,且填充由多个叠层定义的沟道(例如,元件符号120),并在叠层上的半导体条状物111至114的侧表面以及字线116、117间的交叉点定义接口区域多层阵列。硅化物(例如,钨硅化物、钴硅化物、钛硅化物)层118、119能形成于字线116、117的顶表面的上方。
在字线111至114上,也能通过在通到区域中提供纳米线或纳米管结构的方式,构建出纳米线MOSFET型单元,如同Paul等人在“Impact of aProcess Variation on Nanowire and Nanotube Device Performance”,IEEETransactions on Electron Devices,Vol.54,No.9,September 2007所提出的相关叙述内容。其中,在此完整提出此文章而将其作为参考文献以合并理解。
因此,能形成配置成NOR型快闪阵列的SONOS型存储器单元的三维阵列。源极、漏极及通道形成于硅(silicon,S)半导体条状物111至114中,存储器材料层状物115包含能以氧化硅(silicon oxide,O)形成的隧穿介电层97、能以氮化硅(silicon nitride,N)形成的电荷存储层98、能以氧化硅(silicon oxide,O)形成的阻挡介电层99以及包括字线116、117的多晶硅(S)的栅极。
半导体条状物111至114能为p型半导体材料。字线116、117能为相同或不同导电类型的半导体材料(例如,p+型)。举例而言,半导体条状物111至114能使用p型多晶硅或p型外延单晶硅来制作,同时字线116、117能使用相对重地掺杂的p+型多晶硅来制作。
另外,半导体条状物111至114能为n型半导体材料。字线116、117能为相同或不同导电类型的半导体材料(例如,p+型)。此n型条状物安排会造成埋设通道及耗尽模式电荷捕捉存储器单元。举例而言,半导体条状物111至114能使用n型多晶硅或n型外延单晶硅来制作,同时字线116、117能使用相对重地掺杂的p+型多晶硅来制作。用于n型半导体条状物的典型的掺杂浓度在每立方厘米中约为10的18次方(1018/cm3),其中,能使用的实施例其掺杂浓度为每立方厘米中为10的17次方(1017/cm3)至每立方厘米中为10的19次方(1019/cm3)的范围中。N型半导体条状物的使用能尤其有利于无结的实施例中,以增进沿着NOR型存储器的导电性,且从而允许较高的读取电流。
因此,包括具有电荷存储结构的场效晶体管的存储器单元,形成于交叉点的三维阵列中。当使用宽度维度为25纳米等级的半导体条状物及字线,且脊形叠层之间的间隙为25纳米等级时,具有数十层的装置(例如,32层)能在单一芯片中趋近兆位容量(10的12次方,1012)。
存储器材料层状物115能包括其它电荷存储结构。举例而言,能使用由SONOS(BE-SONOS)电荷存储结构策动的能带间隙,此结构包含介电隧穿层97,介电隧穿层97包含在零偏压下形成为倒U形价带的复合材料。在一实施例中,复合隧穿介电层包含作为空穴隧穿(hole tunneling)层的第一层、作为能带偏移(band offset)层的第二层以及作为隔绝层的第三层。在此实施例中的层状物115的空穴隧穿层,包括在半导体条状物的侧表面上二氧化硅,例如使用原位蒸气产生技术(in-situ steam generation,ISSG)并伴随不论是通过后沉积NO退火还是通过在沉积期间将NO增加至周围的可选的氮化工艺的方式形成。二氧化硅的第一层的厚度小于20埃,优选为15埃或更薄。代表的实施例能为10埃至12埃的厚度。
在此实施例中的能带偏移层包括躺设于空穴隧穿层上的氮化硅,例如使用低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)的方式形成,且例如使用二氯硅甲烷(dichlorosilane,DCS)及NH3作为前驱物。在另外处理中,能带偏移层包括氮氧化硅,为使用于N2O作为前驱物的相似处理来制作。氮化硅的能带偏移层厚度小于30埃,优选为25埃或更薄。
在此实施例中的隔绝层包括躺设于氮化硅的能带偏移层上的二氧化硅,例如使用LPCVD及以高温氧化物(high temperature oxide,HTO)沉积的方式形成。二氧化硅的隔绝层厚度小于35埃,优选为25埃或更薄。此三层隧穿层造成倒U形价带能级。
第一位置的价带能级,为足以诱发空穴隧穿通过在半导体主体及第一位置的接口间的薄区域的电场,也足以在第一位置之后,提升价带能级至有效消除第一位置之后在复合隧穿介电层中的空穴隧穿势垒的能级。此结构在三层隧穿介电层中构建出倒U形价带能级,且使电场能由高速的空穴隧穿所协助,同时在电场不存在或由其它运算目的所诱发的较小的电场的存在时,能有效防止电荷渗漏通过复合隧穿介电层,其它运算例如从单元读取数据或编程相邻的单元。
在代表的装置中,存储器材料层状物115包含由复合隧穿介电层策动的能带间隙,此复合隧穿介电层包括小于2纳米厚的二氧化硅层、小于3纳米厚的氮化硅层以及小于4纳米厚的二氧化硅层。在一实施例中,复合隧穿介电层是由极薄氧化硅层O1(例如,小于或等于15埃)、极薄氮化硅层N1(例如,小于或等于30埃)以及极薄氧化硅层O2(例如,小于或等于35埃)所组成,极薄氧化硅层O2在从具有半导体主体的界面偏移15埃或更小偏移的情况下,造成价带能级约2.6eV的增加。O2层通过较低价带能级(较高空穴隧穿势垒)以及较高的导电带能级,在第二偏移(例如,从接口约30埃至45埃)的情况下,分隔N1层与电荷捕捉层。因为第二位置从接口距离在较远的位置,而在第二位置之后,足以诱发空穴隧穿的电场会提升价带能级至有效消除空穴隧穿势垒的能级。因此,O2层不会严重地干涉由空穴隧穿所协助的电场,同时在低场期间增进由隧穿介电层策动以阻挡渗漏的能力。
在此实施例的存储器材料层状物115中的电荷捕捉层,包括具有厚度大于50埃的氮化硅,在此实施例中例如包含约70埃,其中例如使用LPCVD而形成的。能采用其它电荷捕捉材料及结构,例如包含氮氧化硅(SixOyNz)、富硅氮化硅、富硅氧化硅以及包含埋嵌纳米粒子的捕捉层等物质。
在此实施例的存储器材料层状物115中的阻挡介电层,包括具有厚于50埃的厚度的二氧化硅层,在此实施例中例如包含约90埃,能通过从氮化物湿法转化(wet conversion)或通过湿炉氧化处理而形成的。其它实施例能使用高温氧化(high temperature oxide,HTO)或LPCBD SiO2实行。其它阻挡介电层能包含如氧化铝的高κ材料。
在代表实施例中,空穴隧穿层能为13埃的二氧化硅,能带偏移层能为20埃的氮化硅,隔绝层能为25埃的二氧化硅,电荷捕捉层能为70埃的氮化硅,以及阻挡介电层能为90埃的氧化硅。栅极材料为使用在字线116、117中的p+多晶硅(公函数约为5.1eV)。
图6绘示形成于字线116及半导体条状物114的相交处的电荷捕捉存储器单元,沿X-Z平面切取的剖视图。主动电荷捕捉区域125、126形成于条状物114的两侧且位于字线116及条状物114之间。在此所述的实施例中,如图6所示,每个存储器单元为双栅极场效晶体管,具有主动电荷存储区域125、126,其中一个区域在半导体条状物114的各个侧面上。在附图中以实心箭头所示的电流,沿着p型半导体条状物流入感测放大器,而能被测量并指出所选择的存储器单元的状态。
图7绘示形成于字线116、117及半导体条状物114的相交处的电荷捕捉存储器单元,沿X-Y平面提取的剖视图。说明电流路径下流至半导体条状物114。在作用为字线的字线116、117间的源极/漏极区域128、129、130能为无结,源极及漏极掺杂所具有的导电类型不会与在字线下方的通道区域的导电类型相反。在无结的实施例中,电荷捕捉场效晶体管能具有p型通道结构。而且,在一些实施例中,能在定义字线之后,以自对准注入程序进行源极及漏极的掺杂。
在另外实施例中,半导体条状物111至114能以无结安排来使用轻微掺杂的n型半导体主体,而造成能以耗尽模式运算的埋设通道场效晶体管,伴随用于电荷捕捉单元的自然挪移的较低阈值分布。
图8绘示根据本发明实施例的集成电路的简化的方块图。在此所述实行的NOR型排列中,集成电路线975在半导体衬底上,包含三维闪存阵列960。列译码器961耦合至多个字线962,且沿着存储器阵列960中的列来排列。行译码器963耦合至位线964,且沿着存储器阵列960中对应叠层的行来排列,以从阵列960中的存储器单元读取及编程数据。平面译码器958通过源极线959耦合至存储器阵列960中的多个平面中。在总线965上,将地址供给至行译码器963、列译码器961及平面译码器958。在此实施例中,方块966中的感测放大器及数据输入结构,通过数据总线967耦合至行译码器963。从集成电路975上的输入/输出端口,或从集成电路975的内部或外部的其它数据来源,通过数据输入线971,将数据供给至方块966中的数据输入结构。在所述的实施例中,集成电路上包含其它电路974,例如一般目的的处理器或特殊目的应用电路,或者提供由存储器阵列所支持的系统单芯片功能的模块的组合。从方块966中的感测放大器,通过数据输出线972,将数据供给至集成电路975上的输入/输出端口,或者供给至集成电路975的内部或外部的其它数据标的。
使用偏压安排状态装置969而实行在此实施例中的控制器,此控制器控制经由电压供应器或在方块968中的供应器所产生或所提供的偏压安排供给电压的施加,例如读取电压、擦除电压、编程电压、擦除验证电压及编程验证电压。控制器能使用如现有技术的特殊目的逻辑电路来实行。在另外实施例中,控制器包括一般目的的处理器,此处理器能实行在相同的集成电路上,此集成电路执行计算机程序以控制装置的运算。在其它实施例中,特殊目的逻辑电路及一般目的的处理器的组合能被使用在此控制器的实行。
图9绘示如图5的结构的另外结构的立体图。在附图中,将再次使用相似结构的元件符号,且不再描述。图9与图5不同之处在于:由于形成字线的刻蚀处理,绝缘层110的表面110A以及半导体条状物113、114的侧表面113A、114A,外露于作用为字线的字线116之间。因此,在字线之间,能完全或部分地刻蚀存储器材料层状物115而不伤害运算。然而,在一些结构中,不必须刻蚀穿过存储器层状物115,此存储器层状物115形成如描述于此的介电电荷捕捉结构。
图10如同图6,绘示沿X-Z平面提取的存储器单元的剖视图。图10与图6相同,在此剖视图中,绘示图9的结构,此结构造成与实行在图5的结构相同的存储器单元。图11如同图7,绘示沿X-Y平面提取的存储器单元的剖视图。图11与图7不同之处在于:沿着半导体条状物114的侧表面(例如,元件符号114A)的区域128a、129a及130a,能移除存储器材料。
图12至图16绘示基本处理流程的阶段,此流程用于仅使用二个图案化掩模步骤实行如上所述的三维存储器列,此图案化掩模步骤为用于阵列形成的关键对齐步骤。在图12中,所示的结构是由绝缘层210、212、214的交错沉积以及使用掺杂半导体而形成的半导体层211、213所构成,例如在芯片的阵列区域中进行地毯式沉积。根据实行形式,半导体层211、213能使用具有n型或p型掺杂的多晶硅或外延单晶硅来实行。交错绝缘层210、212、214能例如使用二氧化硅、其它氧化硅或氮化硅来实行。这些层状物能以各种方式形成,此方式包含可用于技艺中的低压化学气相沉积LPCVD处理。
图13绘示光刻图案化步骤的结果,此步骤用于定义半导体条状物的多个脊形叠层250,其中半导体条状物为使用半导体层211、213的材料来实行,且通过绝缘层212、214来隔绝。深且高的长宽比的沟道能形成于叠层中,此叠层支持许多层状物,且使用应用碳硬掩模及反应离子刻蚀的光刻基本处理来形成。
虽未绘示,在此步骤中,定义存储器串的另外方位:位线端至源极线端方位,以及源极线端至位线端方位。
图14A至图14B分别显示下个阶段,用于包含如抗熔丝单元结构的可编程电阻存储器结构的实施例,以及用于包含如SONOS型存储单元结构的可编程电荷捕捉存储器结构的实施例。
图14A绘示于实施例中地毯式沉积存储器材料层状物215的结果,其中,存储器材料是由如图1所示的抗熔丝结构的单层所组成。在另外情况下,不施加地毯式沉积,而是施加氧化处理,以在外露的半导体条状物的侧面上形成氧化物,其中,此氧化物作用为存储器材料。
图14B绘示地毯式沉积层状物315的结果,其中,层状物315包括多层电荷捕捉结构,此结构包含如上关于图4所述的隧穿层397、电荷捕捉层398及阻挡层399。如图14A及图14B所示,存储器层状物215、315以共行方式沉积于半导体条状物的脊形叠层(图13的250)的上方。
图15显示高度长宽比填充步骤的结果,其中,沉积如具有n型或p型掺杂的多晶硅的导电材料以形成层状物225,以用于作用为字线的字线。而且,在使用多晶硅的实施例中,硅化物层226能形成在层状物225的上方。如附图所示,在所述的实施例中,使用如多晶硅的低压化学气相沉积的高度长宽比的沉积技术,以完全填充脊形叠层间的沟道220,甚至是具有高度长宽比在10纳米等级的宽度非常狭窄的沟道。
图16显示第二光刻图案化步骤的结果,使用此步骤以定义作用为三维存储器阵列的字线的多个字线260。第二光刻图案化步骤使用针对阵列的关键维度且用于刻蚀字线间的高度长宽比沟道的单一掩模,而不刻蚀穿透脊形叠层。能使用刻蚀处理刻蚀多晶硅,此处理对于氧化硅或氮化硅上方的多晶硅具有高度选择性。因此,根据相同掩模使用交错刻蚀处理,以刻蚀穿透导电层及绝缘层,且此处理停止在位于下方的绝缘层210上。
在此步骤,也能定义接地选择线。在此步骤,虽然栅极结构共形于个别半导体条状物叠层,也能定义由串选择线控制的栅极结构。
可选的制造步骤包含在多个字线的上方形成硬掩模,以及在栅极结构的上方形成硬掩模。硬掩模能使用相对厚的氮化硅或其它能阻挡离子注入处理的材料来形成。在形成硬掩模之后,能施加注入以增加半导体条状物中的阶梯结构的掺杂浓度,且从而减少沿着半导体条状物的电流路径的电阻。通过使用受控制的注入能量,能造成注入渗透至半导体条状物的底部,以及叠层中的每个躺设其上的半导体条状物。
随后,移除硬掩模,以沿着字线的顶表面与门极结构的上方外露硅化物层。在阵列的顶部上方形成层间介电质之后,开设与插头连接的通孔(via),形成例如使用钨填充材料的插头而抵达至栅极结构的顶表面。图案化躺设其上的金属线,以作为SSL线连接至行译码电路。构建出三平面译码网络,并使用一字线、一位线及一SSL线存取所选择的单元。参照发明名称为「Plane Decoding Method and Device for Three DimensionalMemories」的美国专利申请第6,906,940号。
图24绘示已经制造且测试的八层垂直栅极、薄膜晶体管、BE-SONOS电荷捕捉装置的局部剖视图。此装置以75纳米的半截距制作。通道为约18纳米厚的n型多晶硅。使用无增加结注入,以造成无结结构。位于条状物之间以隔绝Z方向上的通道的绝缘材料,为约40纳米厚的二氧化硅。以p+多晶硅线提供栅极。因使用沟道刻蚀而形成随着沟道愈深则条状物的宽度逐渐愈宽的倾斜侧壁的结构,故较低的条状物的宽度大于较高的条状物的宽度,且条状物间的绝缘材料比多晶硅被刻蚀得更多。
图17绘示三维NOR型闪存阵列结构的立体图。从图中移除填充材料,以外露增加的结构。举例而言,移除脊形叠层中的半导体条状物之间的绝缘层,且移除半导体条状物的脊形叠层之间的绝缘层。
在绝缘层上形成多层阵列,多层阵列包含共形于多个脊形叠层且做用为字线WLn+1、WLn、WLn-1的多个字线。字线的数量能扩大至符合特定应用的需求。多个脊形叠层中的每个皆包含半导体条状物。叠层的数量能扩大至符合特定应用的需求。在相同平面上的半导体条状物通过横向半导体条状物电性耦合在一起,此横向半导体条状物电性耦合至多个源极线。半导体条状物的每个平面具有对应的源极线电压。虽然半导体条状物的特定平面能具有多重横向源极线条状物,但这些位于相同平面上的条状物分享共享的源极线电压。平面的数量能扩大至符合特定应用的需求。
半导体条状物的叠层在沿着每个半导体条状物的多重位置耦合至源极线。而且,半导体状物的叠层在沿着每个半导体条状物的多重位置耦合至位线。此结果为NOR型排列,其中,沿着半导体条状物的字线的位置,为介于连接至字线的一侧面的源极线以及连接至字线另一侧面的位线接触插头之间。在所示的排列中,这些元件沿着半导体条状物由左到右的顺序,为源极线—字线—位线接触—字线—源极线—字线—位线接触。
特定字线选择存储器单元的特定垂直平面。特定源极线选择存储器单元的特定水平平面。特定位线选择存储器单元的特定叠层。字线信号、源极线信号及位线信号的三重组合,足以从存储器单元的三维阵列选择特定的存储器单元。
所示的存储器单元能分享相同的位线而向左右重复。所示的存储器单元能分享相同的字线而向前后重复。而且,所示的存储器单元能增加更多的半导体叠层的平面而向上重复。
图18绘示三维NOR型闪存阵列结构的简化布局图。通过DIFF指示半导体条状物的叠层,指出三个垂直固体条状物。在此情况中,指示半导体条状物的三个叠层。通过横向源极线条状物连接并通过共享SL指示相同平面上但不同叠层的半导体条状物。半导体条状物的每个平面具有对应的源极线电压。特定源极线电压在沿着半导体条状物的叠层的多重位置,耦合至半导体条状物的叠层的特定层状物的横向源极线。
躺设于其上的半导体条状物的叠层,为由WLn+2、WLn+1、WLn、WLn-1指示的横向字线。字线与半导体条状物的共形的重叠,指示存储器单元的位置。存储器单元的特定类型,能随着夹设于字线及半导体条状物之间的特定存储器材料而有所不同。最后,通过金属BL指示的位线为排列成与半导体条状物平行,且躺设于字线的上方。每个位线在沿着半导体条状物的叠层的多重位置,耦合至半导体条状物的特定叠层的所有的层状物。通过BL接触来指示这些位置。
图19绘示阶梯结构的实施例,为将三维存储器的不同的层状物电性耦合至不同的源极线。不同的阶梯被指示为SL(1)、SL(2)及SL(3),指示每个阶梯具有对应的源极线电压,正如同半导体条状物的叠层的每个平面分享共享源极线电压。阶梯结构连接半导体条状物的叠层的不同的平面至源极线接触及源极线,再连接至译码器。
阶梯结构耦合至每个横向源极线条状物。另外,因为在相同平面上的横向源极线条状物分享相同源极线电压,只要横向源极线条状物是电性连接在一起的,横向源极线条状物的子集能具有阶梯结构。此阶梯结构电性连接至用于连接译码电路的不同源极线,以选择阵列内的平面。阶梯结构的较高阶梯比阶梯结构的较低阶梯移除较多材料,以使源极线接触能抵达至较低阶梯,而不会被较高阶梯阻挡。在定义多个脊形叠层时,这些阶梯结构能同时被图案化。
图20绘示阶梯结构的另一实施例,为将三维存储器的不同的层状物电性耦合至不同的源极线。
对照于图19阶梯结构,图20的阶梯结构具有延伸部,此延伸部通过不同的延伸长度从三维阵列往外延伸。阶梯结构的较低阶梯比阶梯结构的较高阶梯延伸得较多,以使源极线接触能抵达至较低阶梯,而不会被较高阶梯阻挡。
图21至图23显示用于不同运算的偏压配置的实施例。被选择来执行运算的存储器单元以虚线圈指示。对应此存储器单元的位线、字线及源极线为「被选择的」。不对应此存储器单元的其它位线、字线及源极线为「不被选择的」。
所示的存储器单元能分享相同的位线而向左右重复。所示的存储器单元能分享相同的字线而向前后重复。而且,所示的存储器单元能增加更多的半导体叠层的平面而向上重复。
图21绘示如图17所示且在所选择的存储器单元执行编程运算的三维NOR型闪存阵列结构的立体图。
不被选择的位线以0V施加偏压。被选择的位线以5V施加偏压。不被选择的源极线施加偏压为浮动。被选择的源极线以0V施加偏压。不被选择的字线以0V施加偏压。被选择的字线以10V施加偏压。
指示的偏压执行通道热电子(channel hot electron,CHE)编程。因为通过p+多晶插头位线接触及n型半导体条状物形成二极管,而能消除杂散电流路径(stray current paths),例如从被选择的位线流入不被选择的位线的路径。
图22绘示如图17所示且在所选择的存储器单元执行读取运算的三维NOR型闪存阵列结构的立体图。
不被选择的位线以0V施加偏压。被选择的位线以1.5V施加偏压。不被选择的源极线施加偏压为浮动。被选择的源极线以0V施加偏压。不被选择的字线以0V施加偏压。被选择的字线以介于擦除及编程阈值电压之间的读取参考电压Vref施加偏压。
指示的位线偏压大于二极管导通偏压(diode turn-on bias),以允许充足的读取边限。此外,因通过p+多晶插头位线接触及n型半导体条状物形成二极管,而能消除逸散电流路径,例如从被选择的位线流入不被选择的位线的路径。
图23绘示如图17所示且在所选择的存储器单元执行擦除运算的三维NOR型闪存阵列结构的立体图。
位线施加偏压为浮动。不被选择的源极线施加偏压为浮动。被选择的源极线以13V施加偏压。字线以0V施加偏压。
指示的偏压执行用于擦除的空穴注入。对于不被选择的存储器单元而言,高的正WL偏压能帮助防止擦除干扰(erase disturb)。
在另一实施例中,也能在三维NOR型DRAM存储器阵列上,以易失性存储方式执行图21至图23的编程、读取及擦除偏压安排。
虽然本发明通过参照详述于上的优选实施例及范例而公开,但应理解为这些范例为用于说明而非用于限定。考虑到对于本领域的普通技术人员而言,将随时发生修改及组合,其中,修改及组合将在本发明的精神及下列权利要求的范畴内。
Claims (20)
1.一种存储器装置,其特征在于,包括:
一集成电路衬底;
多个半导体材料条状物的叠层,从该集成电路衬底伸出,这些叠层为脊形,且这些叠层在多个平面位置中的不同平面位置包含由绝缘材料分隔的至少二个半导体材料条状物;
多条字线,正交地排列在这些叠层上方;
多个存储器元件,位于这些叠层及这些字线的表面之间;
多个位线结构,耦合至沿着这些叠层的每个半导体材料条状物的多重位置;以及
多个源极线结构,耦合至沿着这些叠层的每个半导体材料条状物的多重位置,
其中这些位线结构及这些源极线结构位于这些字线中的相邻的字线之间。
2.根据权利要求1所述的存储器装置,其特征在于,这些存储器元件分别包括一隧穿层、一电荷捕捉层及一阻挡层。
3.根据权利要求1所述的存储器装置,其特征在于,这些存储器元件支持易失性存储。
4.根据权利要求1所述的存储器装置,其特征在于,还包括多个二极管,紧接于这些位线结构。
5.根据权利要求1所述的存储器装置,其特征在于,还包括多个二极管,其中这些半导体材料条状物包括这些二极管的n型硅,且各该二极管包括各该半导体材料条状物中的一p型区域。
6.根据权利要求1所述的存储器装置,其特征在于,还包括多个二极管,其中这些半导体材料条状物包括这些二极管的n型硅,且各该二极管包括与各该半导体材料条状物接触的一p型插头。
7.根据权利要求1所述的存储器装置,其特征在于,其中多条位线中的特定一位线、多条源极线中的特定一源极线及多条字线中的特定一字线的组合的选择,识别这些存储器元件中的一特定存储器元件。
8.根据权利要求1所述的存储器装置,其特征在于,还包括:
多个阶梯结构,将这些源极线结构耦合至多条源极线。
9.一种存储器装置,其特征在于,包括:
一集成电路衬底;
一存储器单元的三维阵列,在该集成电路衬底上,该三维阵列包含多个NOR型存储器单元的叠层;
多个字线,排列在这些NOR型存储器单元的叠层上方;
多个字线结构,耦合至沿着这些NOR型存储器单元的叠层的多重位置;
多个源极线结构,耦合至沿着这些叠层的每个半导体材料条状物的多重位置,
其中这些位线结构及这些源极线结构位于这些字线中的相邻的字线之间。
10.根据权利要求9所述的存储器装置,其特征在于,该三维阵列包括在一接口区域中的多个存储器元件,各该存储器元件包括一隧穿层、一电荷捕捉层及一阻挡层。
11.根据权利要求9所述的存储器装置,其特征在于,该三维阵列包括在该接口区域中的多个存储器元件,支持易失性存储。
12.根据权利要求9所述的存储器装置,其特征在于,还包括多个二极管,紧接于这些位线结构。
13.根据权利要求9所述的存储器装置,其特征在于,还包括多个二极管,其中这些叠层包括这些二极管的n型硅,且各该二极管包括各该叠层中的一p型区域。
14.根据权利要求9所述的存储器装置,其特征在于,还包括多个二极管,其中这些叠层包括这些二极管的n型硅,且各该二极管包括与各该叠层接触的一p型插头。
15.根据权利要求9所述的存储器装置,其特征在于,其中多个字线中的特定一位线、多个源极线中的特定一源极线及多个字线中的特定一字线的组合的选择,识别这些存储器单元的该三维阵列中的一特定存储器单元。
16.根据权利要求9所述的存储器装置,其特征在于,还包括:
多个阶梯结构,将这些源极线结构耦合至多个源极线。
17.一种运算三维存储器阵列的方法,其特征在于,包括:
在一三维阵列中对多个NOR型存储器单元的相邻的叠层施加偏压,包含:
对多条位线施加偏压,这些位线经由多个二极管耦合至沿着这些NOR型存储器单元的叠层的多重位置。
18.根据权利要求17所述的方法,其特征在于,这些叠层包括多个存储器元件,各该存储器元件包括一隧穿层、一电荷捕捉层及一阻挡层。
19.根据权利要求17所述的方法,其特征在于,这些叠层包括多个存储器元件,支持易失性存储。
20.根据权利要求17所述的存储器装置,其特征在于,还包括多个二极管,紧接于多个位线结构。
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US20120182801A1 (en) | 2012-07-19 |
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