CN113169041B - 形成多层垂直nor型存储器串阵列的方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 39
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 42
- 239000003989 dielectric material Substances 0.000 claims description 30
- 239000004020 conductor Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 8
- 239000011232 storage material Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 5
- 239000012777 electrically insulating material Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 21
- 239000002184 metal Substances 0.000 description 21
- 229910052581 Si3N4 Inorganic materials 0.000 description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 16
- 239000010409 thin film Substances 0.000 description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 230000005641 tunneling Effects 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- -1 indium gallium zinc compound Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
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Abstract
提供了一种使用镶嵌局部位线形成3维垂直NOR型存储器串阵列的方法。本发明的方法还通过分两步蚀刻局部字线来避免条带化。通过分两步刻蚀局部字线,降低了局部字线的堆叠体(“字线堆叠体”)的图案化和蚀刻的深宽比,这提高了字线堆叠体的结构稳定性。
Description
相关申请的交叉引用
本申请涉及并要求于2018年12月7日提交的美国临时申请(“临时申请”)的优先权,序列号62/777,000,题为“Methods for Forming Multilayer Horizontal NOR-typeThin-film Memory Strings”。
本发明还涉及于2018年8月21日提交的美国专利申请(“非临时申请I”),序列号16/107,732,题为“Three-Dimensional vertical NOR Flash Thin film TransistorStrings”,其是2017年12月11日提交的美国专利申请序列号15/837,734且题为“Three-Dimensional vertical NOR Flash Thin film Transistor Strings”的继续申请,其是2016年11月4日提交的美国专利申请序列号15/343,332且题为“Three-Dimensionalvertical NOR Flash Thin film Transistor Strings”的分案申请,其与以下相关并要求其优先权:(i)美国临时专利申请,序列号62/260,137,题为“Three-Dimensional verticalNOR Flash film Transistor Strings”,于2015年11月25日提交。
本申请还与以下申请相关:美国临时专利申请(“临时专利申请II”),序列号62/625,818,题为“Three-dimensional Vertical NOR Flash Thin-film TransistorStrings”,于2018年2月2日提交;(ii)美国专利申请(“临时申请III”),序列号62/630,214,题为“Three-dimensional Vertical NOR Flash Thin-film Transistor Strings”,于2018年3月13日提交;以及(iii)美国临时专利申请(“临时申请IV”),序列号62/771,922,题为“Staircase Structures for Electrically Connecting Multiple HorizontalConductive Layers of a 3-Dimensional Memory Device”,提交于2018年11月27日。
非临时申请以及临时申请I、II、III和IV的公开内容通过引用整体并入本文中。
背景技术
1.技术领域
本发明涉及3维存储器结构。特别地,本发明涉及以垂直NOR型存储器串的阵列组织的3维存储器结构。
2.相关技术的讨论
形成垂直NOR型存储器串阵列的方法之前已经描述过;例如,形成这种存储器阵列的各种变体在以上通过引用并入的非临时申请和临时申请II和III中公开。
发明内容
根据本发明的一个实施例,提供了一种利用镶嵌局部垂直位线形成3维垂直NOR型存储器串阵列的方法。本发明的方法还通过分两步蚀刻局部字线来避免条带化。通过分两步刻蚀局部字线,降低了局部字线的堆叠体(“字线堆叠体”)的图案化和蚀刻的深宽比,这提高了字线堆叠体的结构稳定性。本发明还解决了在两个步骤中蚀刻字线条带时附带的对准问题。
通过结合附图考虑以下详细描述,可以更好地理解本发明。
附图说明
图1示出了设置在导电层(“全局互连线”)5上并与其隔离的存储器结构10,其包括多个导体,每个导体沿着第一方向(X方向)延伸。
图2示出了填充沟槽55的牺牲电介质层60,移除了沉积在存储器结构10的顶部的多余的电介质材料。
图3示出了另一掩模层,其沉积在存储器结构10上并被图案化以形成掩模结构70。
图4示出了第二组沟槽80,其通过蚀刻穿过存储器结构100的多层而形成,以形成多层堆叠体90。
图5示出了在通过选择性蚀刻移除每个多层中的SiN层30之后的具有腔35的存储器结构10。
图6示出了填充存储器结构10的字线带的腔35的金属层100。
图7示出了在通过任何合适的平坦化技术(例如CMP)从存储器结构10的顶表面移除了多余的牺牲电介质材料之后的沟槽80中的牺牲电介质层110。
图8示出了穿过存储器结构10的沟槽55和80中的通孔120的图案化和蚀刻。
图9示出了在图8中的通孔120中共形地沉积以下层:通孔120:(i)隧穿电介质层130,(ii)电荷存储层140,(iii)阻挡电介质层150,(iv)沟道层160,(v)衬垫层170和(vi)牺牲电介质层180。
图10示出了在重复图8的形成通孔和图9的沉积各个层之后得到的存储器结构10。
图11示出了使用光刻法和蚀刻在牺牲电介质层180中限定的轴200。
图12示出了每个轴200用半导体材料210填充,其形成了用于沿着该通孔形成的薄膜晶体管的公共源极区。
图13示出了通过重复图11至12的限定通孔、蚀刻衬垫层170和用半导体层填充通孔的步骤而提供的漏极半导体层220。
图14示出了设置在存储器结构10上方用于接触漏极半导体层220的全局互连线230。
图15示出了能够接触存储器结构10的局部字线240的楼梯结构。
图16示出了能够接触局部字线240的图15的楼梯结构中的通孔和导体250。
图17A和17B示出了条带化的现象,其是微观矩形特征的应力引起的变形。
图18、19、20和21,结合上面的图14-16,示出了根据本发明的第二实施例的存储器结构10的制造。
图22、23、24、25、26、27、28和29,结合上面的图8-16,示出了根据本发明的第二实施例的存储器结构10的制造。
为了便于附图之间的交叉引用和详细描述的简化,附图中相同的元件被分配相同的附图标记。
具体实施方式
在该详细描述中,针对一个实施例描述的工艺步骤可以用于不同的实施例中,即使在不同的实施例中未明确描述这些工艺步骤。当本文提及包括两个或更多个限定的步骤的方法时,限定的步骤可以以任何顺序或同时进行,除非本文另有规定或提供具体说明。此外,除非另有规定或明确说明,否则该方法还可以包括在任何限定的步骤之前、两个限定的步骤之间或所有限定的步骤之后执行的一个或多个其他步骤。
图1示出了设置在半导体衬底的平坦表面15上的导电层(“全局互连线”)5上并与之隔离的存储器结构10。法向于平坦表面15是沿着第一方向(Z方向)。全局互连线5中的导体包括多个导体,每个导体沿着正交于Z方向的第二方向(X方向)延伸。导电层5中的导体沿着第三方向(Y方向,基本上正交于X方向和Z方向)与和其相邻的导体分离和隔离。全局互连线5在尚未形成的垂直局部字线与形成在半导体衬底(未示出)中的控制、解码、电压源和感测电路之间提供电连接性。这种连接性可以是直接的,也可以是通过选择晶体管(未示出)进行的。
全局互连线5可以包括任何合适的导电材料,例如钨(W)、氮化钛(TiN)、钛(Ti)、钽(Ta)、铬(Cr)、钼(Mo)、钴(Co)或这些材料的任何组合。如图1所示,存储器结构10包括32个多层(例如,多层20),其中每个可以包括例如氮化硅(SiN)层30和氧化硅(SiO2)层40。替代地,层30可以例如包括p型掺杂或n型掺杂的硅或硅锗,而不是氮化硅。可以使用任何合适的技术来沉积每个多层中的每个层,例如,低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)、原子层沉积(ALD,它本身是CVD的一种形式)、溅射、或蒸发,最优选通过PECVD。尽管图1示出了32个多层,但存储器结构10中的多层的数量可以是任何合适的数量(例如,一个、两个、十六个、六十四个或更多)。在沉积存储器结构10之后,沉积掩模层(例如,碳基掩模层)并使用光致抗蚀剂层(未示出)来将其图案化以形成掩模结构50。掩模结构50均具有宽度L2且通过宽度L1的沟槽和与其相邻的掩模结构分开,宽度L2优选不小于两倍的所需宽度L1。宽度L1限定了要形成的有源带之间的沟槽的所需宽度。
然后,第一组沟槽55通过以下方式形成:使用掩模结构50蚀刻穿过存储器结构10的多层,然后移除掩模结构50。图2示出了填充沟槽55的牺牲电介质层60,移除了沉积在存储器结构10的顶部的多余的电介质材料。从存储器结构10的顶部移除牺牲电介质层60可以使用任何合适的技术来完成稿,例如化学机械抛光(CMP)或者回蚀刻,最优选为CMP。牺牲电介质层60可以包括任何合适的材料(例如,SiO2、多孔SiO2、硼掺杂的SiO2(BSG)、磷掺杂的SiO2 PSG)、硼磷掺杂的SiO2(BPSG)、SiOH、SiCOH,这些材料的任何组合,或任何合适的材料)。最优选地,牺牲电介质层60由可以比SiN层30和SiO2层40被蚀刻快得多的材料形成。
此后,如图3所示,另一掩模层沉积在存储器结构10上并被图案化以形成掩模结构70。掩模结构70(其每一个在沟槽50之一中的牺牲电介质层60以及该沟槽的两侧的多层的部分上延伸)通过宽度L1彼此分开(如在掩模结构50中一样)以限定平行于第一组沟槽55的第二组沟槽80。图4示出了第二组沟槽80,其通过以下方式形成:蚀刻穿过存储器结构10的多层,从而形成各自沿着Y方向延伸的窄多层堆叠体(“字线堆叠体”)90。每个字线堆叠体中的每个多层形成“字线带”。字线堆叠体90均具有宽度L3,其远小于掩模结构50和70的宽度L2。通过在掩模结构50和70中使用相对较大的L2值,避免了被称为“条带化”的问题。
(图17A和17B示出了条带化的现象,其是微观矩形特征的应力引起的变形。图17A示出了微观矩形特征(例如,通过显影掩模材料形成的特征),其具有预期的尺寸,宽度X1、长度Y1和高度Z1。在一些制造过程中,当深宽比Z1/X1超过10时,矩形特征中的应力可能导致沿长度Y1的变形,使得所得的特征“条带”从预期的直线变为一系列相连的S曲线,如图17B所示。宽度较小时,条带化更加严重,尤其是当X1缩放到约45nm以下时)。
在实践中,由于现有光刻工具的局限性,可能发生一些未对准,使得每个掩模结构70在其下方的左右堆叠体上的重叠并不完全相等。例如,如果目标宽度L3为50纳米且最坏情况下的未对准为±5纳米,则左侧重叠可以达到55纳米宽,而右侧重叠可以窄至45纳米宽。宽度的这种制造可变性导致尚未形成的偶数和奇数金属导体字线的宽度的可变性。进而,宽度的可变性可能导致较窄的字线的较高电阻。可以在芯片设计中吸收这种可变性,例如,通过将每个堆叠体的左侧和右侧薄膜晶体管视为属于两个独立的组,每个组都设置有其专用的参考晶体管或参考存储器串,这些参考晶体管或参考存储器串由其相应的组构成。
接下来,如图5所示,存储器结构10中的每个字线带的SiN层30通过选择性蚀刻移除。可以使用任何合适的技术(例如腐蚀性气体或湿法化学酸或碱)移除SiN层30。例如,可以在加热到180℃的磷酸中通过湿法蚀刻来移除SiN层30。当每个SiN层30被一直蚀刻到沟槽55中的牺牲电介质层60时,蚀刻停止。由于没有对沟槽55中的牺牲电介质层60进行实质的蚀刻,它们的支撑允许字线堆叠体90保持其预期的结构形状(即,沿整个长度分别为窄、长和高),即使移除了每个字线带中的构成SiN层30,从而在字线堆叠体90中形成腔或不连续性35。注意,在现有技术水平下,可能不需要跨接在相邻堆叠体90之间并以适当间隔放置的支架来支撑狭窄的有源堆叠体。但是,将来对于高度缩放的3维存储器阵列可能需要这样的支架,当宽度L3变得过窄时,或当字线堆叠体过高时(例如,字线带的数量过大),使得以适当的间隔支撑非常长的字线堆叠体变得很谨慎。
然后提供一个或多个金属层以形成金属层100,该金属层填充每个字线带中的腔35。然后,通过适当的蚀刻从沟槽80的侧壁移除金属层100,仅将金属层100留在字线带中,如图6所示。在一些实施例中,通过选择性地蚀刻直到远离沟槽80的侧壁约6纳米,使金属层100进一步凹陷,以便容纳要放置在其中的氧化物盖层或硅阻挡盖层,如本领域普通技术人员已知的。氧化物盖层或硅阻挡盖层将金属层100分开以免与尚未形成的电荷俘获层直接接触。金属层100可以是任何合适的金属,例如TiN、TaN、Ta、W、Mo或这些金属的任何组合,其通过任何合适的技术来沉积,例如ALD、CVD、PVD、溅射、蒸发或这些技术的任何适当组合,最优选对于比如TiN的衬垫金属为ALD且对于诸如W或Mo的填充金属为CVD。如图7所示,在较薄的TiN层107之间的钨层105的组合形成金属层100。
图7示出了沉积在在通过任何合适的平坦化技术(例如CMP)从存储器结构10的顶表面移除了多余的牺牲电介质材料之后的沟槽80中的牺牲电介质层110。然后使用光刻法对牺牲电介质层60和110图案化,并进行蚀刻以提供长形的通孔120,其延伸穿过存储器结构10的高度(即,沿着Z方向),暴露字线堆叠体90的侧壁,如图8所示。每个沟槽中的通孔120中的相邻通孔隔开预定距离,例如,沿着每个通孔120的Y方向的长度。
然后,在长形的通孔120中依次共形地沉积以下膜:(i)隧穿电介质层130,(ii)电荷存储层140,(iii)阻挡电介质层150,(iv)沟道层160,(v)以及可选的衬垫层170,以及(vi)牺牲电介质层180。可以使用任何合适的技术,例如LPCVD、CVD、ALD、PVD或蒸发,最优选地是LPCVD和ALD,来沉积这些层。隧穿电介质层130可以是电荷载流子可以隧穿通过的任何合适的材料(例如二氧化硅)。隧穿电介质层130可以是任何合适的厚度(例如,0.5至10.0nm)。电荷存储层140可以是任何合适的材料,例如:(i)SiN或富硅的SiN,任何合适的形式(例如非晶、纳米晶体或多晶),或(ii)氮化硅、氧化硅基体、氧化硅或富硅氧化硅中的锗纳米晶体。电荷存储层140可以是任何合适的厚度(例如,0.5至20nm)。阻挡电介质层150可以是氧化硅、氮化硅、氮氮化硅、氧化铝或氧化铪,或这些材料的任何合适的组合。阻挡电介质层150可以是足以阻止载流子通过的任何合适的厚度(例如,3至30nm)。
沟道层160是合适的n型或p型半导体材料(例如,硅、硅锗、或铟镓锌化合物(IGZO),或氧化锌),其具有合适的厚度(例如,2至30nm)且通常原位相对较轻地掺杂或不掺杂。牺牲电介质层180可以包括任何合适的材料(例如,SiO2、多孔SiO2、硼掺杂的SiO2(BSG)、磷掺杂的SiO2(PSG)、硼磷掺杂的SiO2(BPSG)、SiOH、SiCOH,或这些材料的任何组合)。可选的衬垫层170是一种材料,其适于用作牺牲电介质层180(例如,氧化铝或氮化硅)的尚未进行蚀刻的蚀刻停止,其具有任何合适的厚度(例如,0.5至5nm)。在将这些层共形地沉积到通孔120中之后,可以从存储器结构10的顶部移除多余的材料,然后使用任何合适的技术(例如,CMP)进行平坦化。
之后,重复图8的形成通孔的步骤,以通过移除沟槽55和80的牺牲电介质层60和110的剩余部分来形成通孔125,同时保护通孔120中的沉积层。然后,在通孔125中共形地沉积与通孔120中相同的材料:(i)隧穿电介质层130,(ii)电荷存储层140,(iii)阻挡电介质层150,(iv)沟道层160,(v)可选的衬垫层170,以及(vi)牺牲电介质层180。所得的结构如图10所示。在图10中,沟槽55和80中的电介质材料现在被字线堆叠体90之间的连续沉积层的相邻行替换。如果需要,该第二组轴中的电荷存储材料可以具有与较早组的轴中的电荷存储材料不同的特性。
然后如图11所示,使用光刻法在牺牲电介质层180中限定轴200并对其进行蚀刻。每个轴200从存储器结构10的顶部向下延伸到全局互连线5,穿过存储器结构10和全局互连线5之间的隔离层中的开口。在轴200的蚀刻期间,其可以是牺牲电介质层180的大功率干法蚀刻,沟道层160的侧壁由对蚀刻具有抵抗力的衬垫层170保护。如图11所示,沿X方向的相邻的轴彼此对齐,但替代地也可以使它们彼此交错。沿X方向的轴200的每隔一个相邻的轴仅暴露于下面的全局互连线5中的同一导体。然后,例如通过湿法蚀刻移除每个轴200中暴露的衬垫层170的一部分,该湿法蚀刻不会损坏下面的沟道层160。
然后,用半导体材料210填充每个轴200,这形成了用于沿着该通孔形成的薄膜晶体管的公共源极区。源极半导体层210可以是任何合适的重n型掺杂或p型掺杂的材料,例如硅、锗或硅锗。替代地,仅沿着轴的壁部分地填充沉积的源极材料,然后用低电阻率的材料(例如,TiN或钨,未示出)填充腔中的剩余空间。可以使用平坦化技术(例如,CMP)移除覆盖存储器结构10的顶部的半导体层210的任何部分。所得的结构如图13所示。源极半导体层210电连接到全局互连线5。
漏极半导体层220通过以下方式提供:重复在牺牲电介质层180中限定和蚀刻通孔的步骤,蚀刻衬垫层170并用图11-12的重掺杂的n型或p型半导体层210填充通孔,除了漏极半导体层220的通孔的蚀刻不穿通到全局互连线5,使得漏极半导体层220不接触全局互连线5。所得的结构如图13所示。源极半导体层210在图13中用“X”标记。第二组全局互连线,标记为全局互连线230,其在存储器结构10上方用于接触局部漏极半导体层220,如图14所示,形成全局位线,其将每隔一个的相邻的轴220直接地或通过选择晶体管连接到衬底中的电路。此时,每个轴200的源极半导体区域210和漏极半导体层220形成垂直NOR型(VNOR)存储器串的薄膜存储晶体管的公共源极区和公共漏极区(“位线”),每个薄膜晶体管形成在字线带100和沟道层160、隧道电介质层130、电荷存储层140与阻挡电介质层150之间的横向重叠区域处。在一个实施例中,每个字线带100控制其每个侧边缘上的NOR型存储器晶体管。
在根据本发明的VNOR存储器阵列中,字线带的典型的标称最小宽度L1是50纳米,而将相邻的字线堆叠体分开的沟槽55或80的标称最小宽度可以是80纳米,且具有32个有源层的字线堆叠体的高度可以超过2,000纳米(2微米)。因此,50纳米的独立字线堆叠体的深宽比将为2000/50,或40:1,在蚀刻过程中保持不动将是一个严峻的挑战,更不用说通过连续的工艺步骤,这将对良率和成本产生不利影响。然而,使用根据本发明的方法,图1和图3的每个掩模结构50和70的宽度L2是50+80+50=180纳米,因此,使用掩模结构50或70的蚀刻的深宽比是2,000/180,或者11:1。
在一些实施例中,出于裸芯尺寸的考虑,有利的是,将通过全局互连线5或全局互连线230电连接的一些电路(例如,解码电路,以及一些读取、写入和擦除供给电压源)放置在存储器结构10正下方的半导体衬底的一部分中。(这些解码电路和电压源未在图14中示出)全局互连线5与半导体衬底中的这些电路之间的电连接易于获得。为了将半导体衬底中的这些电路电连接到存储器结构10上方的全局互连线230,可能需要在存储器结构10的一侧或多侧提供附加的垂直连接器,以及位于全局互连线230与半导体衬底中的电路之间的导体。在一个实施例中,可以通过以下方式来避免这种迂回路径:提供垂直导体,其将全局字线200直接通过密集封装的存储器结构10和密集间隔的全局互连线5连接到半导体衬底中的电路。这些垂直导体可以通过以下方式来实现:使局部垂直源极半导体层210或局部垂直漏极半导体层220中的所选半导体层也用作连接到半导体衬底中的电路的导体。当以此方式使用时,一种选择是用更导电的材料(例如金属)而不是重掺杂的半导体来填充通孔。为了使用这些垂直导体建立电气路径,可能需要额外的掩模和蚀刻步骤,以在将这些电路放置在半导体衬底中的地方正上方或附近的位置,在其相应的轴的底部穿通通孔开口。
在一些实施例中,当垂直局部源极半导体层210和垂直局部漏极半导体层220都连接到形成在存储器结构10上方的全局互连线230时,不需要在存储器结构10的下面形成全局互连线5。这样的布置避免了将源极半导体层210连接到全局互连线5所需的穿通掩模和蚀刻步骤。反之,半导体层210和漏极半导体层220可以都在存储器结构10的底部通过穿通通孔接触到全局互连线5。在任一情况下,可以避免两组全局互连线之一,前提是全局互连线具有全局互连线5或全局互连线230的约一半的节距,这可能需要双重曝光或更先进的光刻技术。
与局部字线的连接是通过“楼梯”方法进行的。在楼梯结构中,字线堆叠体中的字线带被切割成逐渐更大的长度,以允许垂直导体在台阶处接触连续的字线带的局部字线。例如,在以上通过引用并入的临时申请IV中公开了一种形成楼梯结构的类似方法。在存储器形成并连接到顶部和底部全局字线之后,通过“楼梯”方法进行与字线的连接。楼梯结构通过以下方式进行:首先提供掩模层以暴露并蚀刻掉每个字线堆叠体中的顶部字线带的一部分,以暴露字线带的金属层100,以及连续地(i)使掩模层凹陷;(ii)蚀刻掉每个暴露的字线带的一部分,在的每个台阶处暴露金属层100的一部分,直到字线堆叠体中的每个字线带——除了底部字线带以外——的一部分被移除,如图15所示。图15仅示出了沿着存储器结构10(沿着字线带的长度)的端部。(端部之间的部分,即,包含薄膜晶体管的部分,是图1-14中所示的部分)使用例如在临时申请IV中讨论的光致抗蚀剂凹陷技术,从一端或两端沿Y方向使掩模层凹陷,而不需要额外的光刻步骤来暴露连续的字线带。
然后将电介质材料沉积在楼梯结构上并通过CMP进行平坦化。图16示出了,对所得的电介质材料进行图案化和蚀刻以获得通孔开口,该通孔开口然后被导电材料(例如,难熔金属,例如钨)250填充,以提供到由楼梯结构暴露的每个有源层中的字线层240的端部的接触。以这种方式,每条字线连接到半导体衬底中的或在单独的配套集成电路上的选择电路(例如,解码器和电压源)。这种集成电路可以使用本领域已知的倒装晶片技术(例如,通过连接的晶片之间的多个微型铜柱)连接到半导体衬底中的电路。
根据本发明的另一实施例,高深宽比字线带的结构支撑是由在形成字线带之前形成的电介质支柱提供的。如图18所示,以与上面关于图1所讨论的基本相同的方式形成包括全局互连线的存储器结构10。然而,与图1的掩模层50不同,提供了掩模层260,其被图案化以允许轴265被蚀刻穿过字线堆叠体。在蚀刻轴265并移除掩模260之后,轴265被电介质材料填充以形成电介质支柱270,从结构10的顶部适当地移除多余的电介质材料(例如,通过CMP或回蚀刻),如图19所示。用于电介质支柱270的合适的电介质材料包括任何合适的材料(例如,SiO2、SiN、SiON、SiC、SiCOH、PSG、BSG或BPSG,最优选SiO2),其使用任何合适的技术来沉积(例如,ALD、LPCVD或PECVD,最优选LPCVD)。
然后,存储器结构10通过以下被图案化以形成字线堆叠体285:利用来自电介质支柱270的机械支撑来形成沟槽280,电介质支柱270基本上不被蚀刻。所得的结构如图20所示。电介质支柱270为字线带的高深宽比堆叠体280提供机械支撑。沉积牺牲电介质材料290(其可以是与电介质支柱270相同的材料)来填充沟槽280。可以从字线堆叠体285的顶部移除多余的牺牲电介质材料290,例如使用CMP或回蚀刻。之后,可以沉积和图案化掩模层(未示出),以允许从填充的沟槽280的每隔一个沟槽移除牺牲电介质材料290。在从沟槽280的每隔一个沟槽移除掩模层和牺牲电介质材料290之后的存储器结构10在图22中示出。存储器结构10的制造的其余部分可以根据上面的描述和图4-16进行。
本发明的又一实施例使用堆叠掩模来形成字线带。参照图22,沉积并图案化第一掩模层300。第一掩模层300限定了字线堆叠体的最终尺寸和节距。在形成第一掩模层300之后,如23所示,沉积并图案化第二掩模层310。第二掩模层310的节距和尺寸大于第一掩模层300,并且设置在第一掩模层300的顶部。第二掩模层310限定存储器结构10中的每隔一个最终字线堆叠体,如图23所示。图23还示出了沟槽320,其在限定第二掩模层310之后被蚀刻穿过存储器结构10。
平坦化步骤(例如,回蚀刻步骤)移除第二掩模层310的一部分,使得第二掩模层310的顶部与第一掩模层300齐平。然后沉积牺牲电介质材料以填充沟槽320,接着从第一掩模层300和第二掩模层310的顶部移除多余的牺牲电介质材料330,如图24所示。
然后通过选择性蚀刻技术移除第二掩模层310的其余部分。第一掩模层300和牺牲电介质层330然后用作掩模以蚀刻第二组沟槽340,如图25所示。之后,通过选择性蚀刻技术移除第一掩模层300的其余部分,如图26所示。
然后通过选择性蚀刻技术移除氮化硅层(40),留下腔350,如图27所示。然后沉积金属层360以填充沟槽340和腔350。然后通过各向同性蚀刻技术移除沟槽340的侧壁和牺牲电介质材料330的顶表面上的金属,留下填充腔350的金属360,如图28所示。该金属替换工艺的细节在上文结合图4和图5的描述中已经详细描述。此后,牺牲电介质材料370被沉积到沟槽340中,接着从存储器结构10的顶表面移除任何多余的牺牲电介质材料370。存储器结构10的制造的其余部分可以根据上面的描述和图8-16进行。
提供上述详细描述是为了说明本发明的具体实施例,而不是为了限制。在本发明的范围内的多种变化和修改是可能的。本发明在所附权利要求中得到阐述。
Claims (19)
1.一种高深宽比蚀刻的方法,包括:
在半导体衬底的表面上方制备多个材料多层,所述多个材料多层沿着正交于所述半导体衬底的表面的第一方向上下叠置,其中每个材料多层包括第一电介质材料的第一层和第一材料的第二层;
使用第一掩模沿着所述第一方向图案化和蚀刻所述材料多层以形成第一组沟槽,所述第一组沟槽将所述材料多层划分为第一组多层堆叠体,其中所述第一组沟槽中的每一个沿着平行于所述半导体衬底的表面的第二方向延伸;
用第二电介质材料填充所述第一组沟槽;以及
使用第二掩模沿着所述第一方向图案化和蚀刻所述第一组多层堆叠体以形成第二组沟槽,所述第二组沟槽将所述第一组多层堆叠体划分成第二组多层堆叠体,其中所述第二组沟槽中的每一个沿着平行于所述第一组沟槽的所述第二方向延伸;
用第二电介质材料填充所述第二组沟槽;以及
在所述第一组沟槽和第二组沟槽中选择性地蚀刻所述第二电介质材料的第一部分,以提供沿着所述第一方向延伸的第一多个轴;
在每个轴中共形地沉积电荷存储材料;
在所述电荷存储材料上共形地沉积具有第一导电性的半导体层;以及
用第三电介质材料填充每个轴。
2.如权利要求1所述的方法,其中蚀刻所述材料多层和蚀刻所述第一组多层均涉及深宽比小于40的蚀刻。
3.如权利要求1所述的方法,其中所述第二掩模提供掩模结构,每个掩模结构与所述第一组多层堆叠体中的至少两个相邻的多层堆叠体和它们之间的所述第一组第二电介质材料填充的沟槽中的一个重叠。
4.如权利要求1所述的方法,其中所述第一材料包括导电材料。
5.如权利要求4所述的方法,还包括:
在每个轴中穿过所述第三电介质材料选择性地蚀刻第一通孔和第二通孔;以及
用具有与所述第一导电性相反的第二导电性的第二半导体材料在每个轴中填充所述第一通孔和第二通孔。
6.如权利要求5所述的方法,还包括,在用所述第三电介质材料填充每个轴之前,在所述具有第一导电性的半导体层上沉积衬垫层,且其中所述方法还包括,在用所述第二半导体材料在每个轴中填充所述第一通孔和第二通孔之前,移除所述衬垫层以暴露所述具有第一导电性的半导体层。
7.如权利要求5所述的方法,还包括,在制备所述材料多层之前,在所述半导体衬底的表面上方提供多个导体,每个导体沿着正交于所述第一方向和第二方向中的每一个的第三方向延伸。
8.如权利要求7所述的方法,其中所述导体通过隔离层与所述材料多层隔离,其中在每个轴中蚀刻所述第一通孔和第二通孔还包括蚀刻穿过所述隔离层,以能够在所述第一通孔和第二通孔中的所选通孔中的导电材料之间提供导电路径,并且电连接到所述导体中的对应的导体。
9.如权利要求5所述的方法,还包括在所述第二组多层堆叠体上方提供多个导体,每个导体沿着正交于所述第一方向和第二方向中的每一个的第三方向延伸。
10.如权利要求9所述的方法,还包括提供导电路径,以使得所述第一通孔和第二通孔中的所选通孔中的所述第二半导体材料能够电连接到所述导体中的一个。
11.如权利要求9所述的方法,还包括:
在所述半导体衬底中提供电路元件;以及
将所述第一通孔和第二通孔中的所选通孔中的所述第二半导体材料电连接到所述电路元件中的对应的电路元件,所述电路元件中的每一个位于其对应的第一通孔和第二通孔下方。
12.如权利要求11所述的方法,还包括在所述电路元件和所述材料多层之间提供隔离层,其中将所述第一通孔和第二通孔中的所选通孔中的所述第二半导体材料中的所选第二半导体材料电连接到其对应的电路元件包括穿过所述隔离层形成导电路径。
13.如权利要求5所述的方法,还包括用所述第二半导体材料部分地填充所述第一通孔和第二通孔,之后用低电阻率导体材料填充所述第一通孔和第二通孔。
14.如权利要求4所述的方法,还包括:
在所述第一组沟槽和第二组沟槽中选择性地蚀刻所述第二电介质材料的第二部分,以提供沿着所述第一方向延伸的第二多个轴;
在所述第二多个轴中的每一个中共形地沉积电荷存储材料;
在所述第二多个轴中的每一个中的电荷存储材料上共形地沉积具有所述第一导电性的半导体层;以及
用所述第三电介质材料填充所述第二多个轴中的每一个。
15.如权利要求14所述的方法,其中所述第二多个轴中的所述电荷存储材料具有与所述第一多个轴中的电荷存储材料不同的特性。
16.如权利要求1所述的方法,所述第一材料包括牺牲层,所述方法还包括用导电材料选择性地替换所述牺牲层。
17.如权利要求16所述的方法,其中替换所述牺牲层包括横向地穿过所述第二组沟槽选择性地蚀刻所述牺牲层直至所述第一组沟槽中的所述第二电介质材料。
18.如权利要求1所述的方法,还包括在所述第二组多层堆叠体中的每个多层堆叠体的一个或多个端部处形成楼梯结构,其中每个楼梯结构具有沿着所述第二方向连续地延伸所述多层堆叠体的层的台阶,且其中每个台阶暴露所述多层堆叠体中的多层中的导电层。
19.如权利要求18所述的方法,还包括在所述楼梯结构上提供电绝缘材料,并且沿着所述第一方向提供通孔连接以电连接到所述楼梯结构的每个台阶中的所述导电层。
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US20240099003A1 (en) | 2024-03-21 |
US11282855B2 (en) | 2022-03-22 |
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US20200185411A1 (en) | 2020-06-11 |
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WO2020118301A4 (en) | 2020-07-30 |
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