CN112530900B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN112530900B
CN112530900B CN202010093083.9A CN202010093083A CN112530900B CN 112530900 B CN112530900 B CN 112530900B CN 202010093083 A CN202010093083 A CN 202010093083A CN 112530900 B CN112530900 B CN 112530900B
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wiring layer
layer
substrate
memory cell
cell array
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CN112530900A (zh
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内山泰宏
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Kioxia Corp
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Abstract

本发明的实施方式提供一种能够容易地将衬底上的元件与存储单元阵列内的电极层连接的半导体装置及其制造方法。根据实施方式，半导体装置具备：第1衬底；逻辑电路，设置于所述第1衬底上；及存储单元阵列，设置于所述逻辑电路的上方，且包含被积层的多个电极层及设置于所述多个电极层上方的半导体层。所述装置还具备：第1及第2插塞，设置于所述逻辑电路的上方，且电连接于所述逻辑电路；焊盘，设置于所述第1插塞上；及金属配线层，设置于所述存储单元阵列上，电连接于所述半导体层，且电连接于所述第2插塞。

Description

半导体装置及其制造方法
[相关申请案]
本申请案享有以日本专利申请案2019-169763号(申请日：2019年9月18日)为基础申请案的优先权。本申请案通过参考该基础申请案而包含基础申请案的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
当在衬底上方的较高的位置配置存储单元阵列的情况下，存在难以将衬底上的元件与存储单元阵列内的电极层连接的情况。
发明内容
实施方式提供一种能够容易地将衬底上的元件与存储单元阵列内的电极层连接的半导体装置及其制造方法。
根据实施方式，半导体装置具备：第1衬底；逻辑电路，设置于所述第1衬底上；及存储单元阵列，设置于所述逻辑电路上方，且包含被积层的多个电极层、及设置于所述多个电极层上方的半导体层。所述装置还具备：第1及第2插塞，设置于所述逻辑电路的上方，且电连接于所述逻辑电路；焊盘，设置于所述第1插塞上；及金属配线层，设置于所述存储单元阵列上，电连接于所述半导体层，且电连接于所述第2插塞。
附图说明
图1是表示第1实施方式的半导体装置的构造的剖视图。
图2是表示第1实施方式的柱状部的构造的剖视图。
图3～8是表示第1实施方式的半导体装置的制造方法的剖视图。
图9是表示第2实施方式的半导体装置的构造的剖视图。
图10是表示第3实施方式的半导体装置的构造的剖视图。
图11是表示第4实施方式的半导体装置的构造的剖视图。
图12是表示第5实施方式的半导体装置的构造的剖视图。
图13是表示第6实施方式的半导体装置的构造的剖视图。
图14是表示第7实施方式的半导体装置的构造的剖视图。
具体实施方式
以下，参考附图对本发明的实施方式进行说明。在图1至图14中，对相同的构成附注相同的符号，并省略重复的说明。
(第1实施方式)
图1是表示第1实施方式的半导体装置的构造的剖视图。图1的半导体装置是将阵列芯片1与电路芯片2贴合所得的三维存储器。
阵列芯片1具备包含多个存储单元的存储单元阵列11、存储单元阵列11上的绝缘膜12、及存储单元阵列11下的层间绝缘膜13。绝缘膜12是第1绝缘膜的例子。绝缘膜12例如是氧化硅膜或氮化硅膜。层间绝缘膜13例如是氧化硅膜或包含氧化硅膜及其它绝缘膜的积层膜。
电路芯片2设置于阵列芯片1下。符号S表示阵列芯片1与电路芯片2的贴合面。电路芯片2具备层间绝缘膜14、及层间绝缘膜14下的衬底15。衬底15是第1衬底的例子。层间绝缘膜14例如是氧化硅膜、或包含氧化硅膜及其它绝缘膜的积层膜。衬底15例如是硅衬底等半导体衬底。
图1表示与衬底15的表面平行且相互垂直的X方向及Y方向、及与衬底15的表面垂直的Z方向。在本说明书中，将+Z方向作为上方向，将-Z方向作为下方向。-Z方向可以与重力方向一致，也可以不一致。
阵列芯片1具备多条字线WL、及源极线SL作为存储单元阵列11内的多个电极层。图1表示存储单元阵列11的阶梯构造部21。各字线WL经由接触插塞22而与字线层23电连接。贯通多条字线WL的各柱状部CL经由介层插塞24而与位线BL电连接，且与源极线SL电连接。源极线SL设置在这些字线WL上，且与下述源极配线层46电连接。源极线SL包含作为半导体层的第1层SL1、及作为金属层的第2层SL2。第2层SL2设置于第1层SL1上，作为阻挡金属层发挥功能。第1层SL1例如是n+型多晶硅层。第2层SL2例如是钛(Ti)层、或包含钛层及氮化钛膜的积层膜。
电路芯片2具备多个晶体管31。各晶体管31具备介隔栅极绝缘膜而设置于衬底15上的栅极电极32、及设置于衬底15内的未图示的源极扩散层及漏极扩散层。此外，电路芯片2具备：多个接触插塞33，设置于这些晶体管31的源极扩散层或漏极扩散层上；配线层34，设置于这些接触插塞33上，且包含多条配线；及多条配线层35，设置于配线层34上，且各包含多条配线。
电路芯片2还具备：多个介层插塞36，设置于配线层35上；及多个金属垫37，设置于这些介层插塞36上。金属垫37例如是铜(Cu)层或铝(Al)层。金属垫37是第1垫的例子。本实施方式的电路芯片2作为控制阵列芯片1的动作的控制电路(逻辑电路)发挥功能。该控制电路由晶体管31等构成，且电连接于金属垫37。该控制电路例如包含存储单元阵列11的周边电路。
阵列芯片1具备：多个金属垫41，设置于金属垫37上；多个介层插塞42，设置于金属垫41上；及多条配线层43，设置于这些介层插塞42上，且各包含多条配线。金属垫41例如是铜层或铝层。金属垫41是第2垫的例子。此外，阵列芯片1具备设置于配线层43上的多个介层插塞44，这些介层插塞44包含多个介层插塞44a、及多个介层插塞44b。介层插塞44a是第1插塞的例子，介层插塞44b是第2插塞的例子。这些介层插塞44在存储单元阵列11的外部设置于存储单元阵列11的侧方。
阵列芯片1还具备金属垫45、源极配线层46、及钝化膜47。
金属垫45设置于介层插塞44a及绝缘膜12上，通过与介层插塞44a相接而电连接于介层插塞44a。本实施方式的金属垫45作为半导体装置的外部连接垫(焊盘)发挥功能。
源极配线层46设置于介层插塞44b、存储单元阵列11、及绝缘膜12上，通过与介层插塞44b相接而电连接于介层插塞44b。源极配线层46是金属配线层的例子。源极配线层46包含：第1部分R1，介隔绝缘膜12而设置于存储单元阵列11上；及第2部分R2，在绝缘膜12内设置于存储单元阵列11上。其结果为，源极配线层46以与源极线SL相接的方式设置于源极线SL上，且电连接于源极线SL。
本实施方式的金属垫45及源极配线层46设置于1个相同的配线层内，分别包含阻挡金属层45a、46a、及阻挡金属层45a、46a上的配线材层45b、46b。阻挡金属层45a、46a例如是氮化钛膜等金属层。配线材层45b、46b例如是铝层等的金属层。本实施方式的金属垫45及源极配线层46如下文所述通过在存储单元阵列11及绝缘膜12上形成1个配线层并对该配线层进行加工而形成，在该配线层内形成金属垫45及源极配线层46。
本实施方式的金属垫45及源极配线层46分别设置于以贯通绝缘膜12的方式设置的介层插塞44a、44b上。由此，介层插塞44a的上端或介层插塞44b的上端设置于比源极线SL的上表面更高的位置。同样地，金属垫45的下表面或源极配线层46的第1部分R1的下表面设置于比源极线SL的上表面更高的位置。另一方面，源极配线层46的第2部分R2的下表面与源极线SL的上表面相接。具体来说，源极配线层46的阻挡金属层46a与源极线SL的第2层SL2相接。
钝化膜47设置于金属垫45、源极配线层46、及绝缘膜12上。钝化膜47例如是氧化硅膜等绝缘膜，且具有使金属垫45的上表面露出的开口部P。金属垫45能够经由该开口部P利用焊接线、焊锡球、金属凸块等连接于安装衬底或其它装置。
如图1所示，存储单元阵列11经由存储单元阵列11下的金属垫41、37等而与电路芯片2电连接，例如，与构成逻辑电路的晶体管31等电连接。对于金属垫45或源极配线层46也同样如此。金属垫45经由介层插塞44a或介层插塞44a下的金属垫41、37等而与电路芯片2电连接，源极配线层46经由介层插塞44b或介层插塞44b下的金属垫41、37等而与电路芯片2电连接。在本实施方式中，在图1的截面中，存储单元阵列11与晶体管31电连接，在与图1不同的截面中，金属垫45或源极配线层46与晶体管31电连接。
图2是表示第1实施方式的柱状部CL的构造的剖视图。
如图2所示，存储单元阵列11具备交替地积层于层间绝缘膜13(图1)上的多条字线WL及多个绝缘层51。字线WL例如是W(钨)层。绝缘层51例如是氧化硅膜。
柱状部CL依次包含阻挡绝缘膜52、电荷储存层53、隧道绝缘膜54、通道半导体层55、及核心绝缘膜56。电荷储存层53例如是氮化硅膜，介隔阻挡绝缘膜52而形成于字线WL及绝缘层51的侧面。电荷储存层53也可以是多晶硅层等半导体层。通道半导体层55例如是多晶硅层，介隔隧道绝缘膜54而形成于电荷储存层53的侧面。阻挡绝缘膜52、隧道绝缘膜54、及核心绝缘膜56例如是氧化硅膜或金属绝缘膜。
图3至图8是表示第1实施方式的半导体装置的制造方法的剖视图。
图3表示包含多个阵列芯片1的阵列晶圆W1、及包含多个电路芯片2的电路晶圆W2。阵列晶圆W1也称为存储晶圆，电路晶圆W2也称为CMOS晶圆。
请留意图3的存储晶圆W1的朝向与图1的阵列芯片1的朝向相反。在本实施方式中，通过将阵列晶圆W1与电路晶圆W2贴合而制造半导体装置。图3表示为了贴合而翻转朝向之前的存储晶圆W1，图1表示为了贴合而翻转朝向且被贴合及切割之后的阵列芯片1。请留意存储晶圆W1具备设置于绝缘膜12下的衬底16。衬底16例如是硅衬底等半导体衬底。衬底16是第2衬底的例子。
在本实施方式中，首先，如图3所示，在存储晶圆W1的衬底16上形成存储单元阵列11、绝缘膜12、层间绝缘膜13、阶梯构造部21、金属垫41等，在电路晶圆W2的衬底15上形成层间绝缘膜14、晶体管31、金属垫37等。
例如，当在衬底16上形成存储单元阵列11等时，在衬底16上依次形成绝缘膜12、源极线SL的第2层SL2、及源极线SL的第1层SL1，在源极线SL上交替地形成多个绝缘层51及多个牺牲层。接下来，在这些绝缘层51及牺牲层内形成多个柱状部CL，然后，将这些牺牲层置换为多条字线WL。这样，在衬底16上介隔绝缘膜12而形成存储单元阵列11。此外，当在衬底16上形成金属垫41等时，在衬底16上依次形成介层插塞44、配线层43、介层插塞42、及金属垫41。此时，介层插塞44以贯通绝缘膜12而到达至衬底16的方式形成。
另一方面，当在衬底15上形成晶体管31或金属垫37时，在衬底15上依次形成栅极电极32、接触插塞33、配线层34、配线层35、介层插塞36、及金属垫37。
接下来，如图4所示，利用机械压力将阵列晶圆W1与电路晶圆W2贴合。由此，将层间绝缘膜13与层间绝缘膜14粘合。接下来，在400℃下将阵列晶圆W1及电路晶圆W2退火。由此，金属垫41与金属垫37接合。其结果为，衬底15与衬底16介隔层间绝缘膜13或层间绝缘膜14而贴合。图4表示该贴合的结果、配置于衬底15上方的存储单元阵列11、插塞44、衬底16等。
接下来，通过CMP(Chemical Mechanical Polishing，化学机械抛光)将衬底15薄膜化之后，通过CMP将衬底16去除，使绝缘膜12露出(图5)。接下来，通过光刻法及蚀刻在绝缘膜12形成开口部H1，使存储单元阵列11的源极线SL在开口部H1内露出(图5)。
接下来，通过溅镀在源极线SL及绝缘膜12上形成配线层48(图6)。配线层48包含形成于源极线SL及绝缘膜12上的阻挡金属层48a、及形成于阻挡金属层48a上的配线材层48b。阻挡金属层48a例如为氮化钛膜。配线材层48b例如是铝层。
接下来，通过RIE(Reactive Ion Etching，反应离子刻蚀)对配线层48进行加工(图7)。其结果为，在配线层48内形成金属垫45及源极配线层46。金属垫45形成于介层插塞44a上，源极配线层46形成于介层插塞44b及源极线SL上。图7的源极配线层46包含介隔绝缘膜12而设置于存储单元阵列11上的第1部分R1、及在绝缘膜12内设置于存储单元阵列11上的第2部分R2。
这样，本实施方式的金属垫45及源极配线层46通过对相同的配线层48进行加工而形成。金属垫45的阻挡金属层45a及源极配线层46的阻挡金属层46a来自配线层48的阻挡金属层48a，金属垫45的配线材层45b、及源极配线层46的配线材层46b来自配线层48的配线材层48b。
接下来，在金属垫45、源极配线层46、及绝缘膜12上形成钝化膜47(图8)。然后，在钝化膜47形成开口部P，使金属垫45在开口部P内露出(参考图1)。进而，将阵列晶圆W1及电路晶圆W2切断为多个芯片。这样，制造本实施方式的半导体装置。
以下，再次参考图1，对本实施方式的源极线SL或源极配线层46进行说明。
当考虑源极配线层46的配置时，考虑将源极配线层46与字线层23同样地配置于存储单元阵列11之下。在此情况下，为了将源极线SL与源极配线层46电连接，必须将贯通多条字线WL的多个接触插塞设置于源极线SL与源极配线层46之间。这种接触插塞的存在会成为提高半导体装置的集成度的阻碍。
此外，源极线SL是在将阵列晶圆W1与电路晶圆W2贴合之前形成，因此，难以使用厚金属层形成源极线SL。理由在于金属层会受到用于贴合的退火的影响。因此，考虑源极线SL是仅由半导体层形成还是由半导体层及薄金属层形成。然而，在这些情况下，源极线SL的电阻会变高，因此，要求在源极线SL与源极配线层46之间配置多数个接触插塞，抑制源极线SL的电压效应。然而，此种多数个接触插塞的存在成为提高半导体装置的集成度的较大的阻碍。
因此，在本实施方式中，通过将源极配线层46配置于存储单元阵列11上、具体而言将源极配线层46配置于源极线SL上而使之与源极线SL电连接。由此，无需将贯通多条字线WL的多个接触插塞设置于源极线SL与源极配线层46之间，从而可提高半导体装置的集成度。
在此情况下源极配线层46配置于衬底15上方的较高的位置，因此，还认为难以与晶体管31等电连接。理由在于，本实施方式的半导体装置通过阵列晶圆W1与电路晶圆W2的贴合而形成，因此，存储单元阵列11配置于衬底15上方的较高的位置，存储单元阵列11上的源极配线层46配置于衬底15上的更高的位置。如果将源极配线层46配置于存储单元阵列11上，那么与将源极配线层46配置于存储单元阵列11下的情况相比，源极配线层46与晶体管31的距离变远。
然而，本实施方式的源极配线层46配置于与金属垫(焊盘)45相同高度，因此，可以利用与金属垫45相同的方法连接于晶体管31。即，与利用介层插塞44a将金属垫45连接于晶体管31同样地，可以利用介层插塞44b将源极配线层46连接于晶体管31。由此，即便源极配线层46配置于衬底15上方的较高的位置，也可以容易地将源极配线层46与晶体管31等连接。由此，根据本实施方式，能够利用这种源极配线层46或介层插塞44b容易地将源极线SL与晶体管31等连接。
此外，因为本实施方式的源极配线层46是在将阵列晶圆W1与电路晶圆W2贴合之后形成的，所以可以避免源极配线层46受到用于贴合的退火的影响。由此，容易使用厚金属层形成源极配线层46，从而能够减少源极线SL及源极配线层46的合计电阻。由此，能够减少介层插塞44b的根数，从而提高半导体装置的集成度。
另外，在本实施方式中，已对将源极线SL与晶体管31电连接的源极配线层46进行了说明，但本实施方式也能同样地应用于将存储单元阵列11内的其它电极层与衬底15上的其它元件电连接的配线层。这种电极层的例子是字线WL或选择线等，这种元件的例子是存储单元或二极管等。
此外，本实施方式的金属垫45及源极配线层46包含于相同的配线层内，但也可包含于不同的配线层内。例如，也可形成某一配线层，对该配线层进行加工而形成金属垫45，然后，形成另一配线层，对该另一配线层进行加工而形成源极配线层46。但是，在金属垫45及源极配线层46包含于相同的配线层内的情况下，可以获得能够同时形成金属垫45及源极配线层46的优点。
如上所述，本实施方式的半导体装置具备源极配线层46，该源极配线层46设置于存储单元阵列11上，电连接于源极线SL，且电连接于介层插塞44b。由此，根据本实施方式，能够容易地将衬底15上的晶体管31等元件与存储单元阵列11内的源极线SL等电极层连接。
另外，在本实施方式中，将阵列晶圆W1与电路晶圆W2贴合，但也可以取而代之将阵列晶圆W1彼此贴合。参考图1至图8而在前文中所述的内容或参考图9至图14将在后文中所述的内容也能应用于阵列晶圆W1彼此的贴合。
此外，图1表示层间绝缘膜13与层间绝缘膜14的交界面或金属垫41与金属垫37的交界面，但通常在上述退火后无法观察到这些交界面。然而，这些交界面所在的位置例如可以通过检测金属垫41的侧面或金属垫37的侧面的斜率或金属垫41的侧面与金属垫37的位置偏移来推定。
(第2至第7实施方式)
图9是表示第2实施方式的半导体装置的构造的剖视图。
相对于第1实施方式的源极配线层46介隔绝缘膜12而形成于源极线SL上，本实施方式的源极配线层46未介隔绝缘膜12而形成于源极线SL上。这种构造例如能够通过在图3的步骤中省略形成绝缘膜12，或在图5的步骤中将绝缘膜12全部去除而实现。在这种构造中例如有可以减小源极配线层46与源极线SL的接触电阻的优点。
图10是表示第3实施方式的半导体装置的构造的剖视图。
相对于第1实施方式的源极配线层46具备一个第2部分R2，本实施方式的源极配线层46具备多个第2部分R2。这种构造例如能够通过在图5的步骤中形成多个开口部H1而实现。这种构造例如具有可以提高源极配线层46与源极线SL的接触部位的布局的自由度的优点。
图11是表示第4实施方式的半导体装置的构造的剖视图。
本实施方式的源极线SL形成于介层插塞44b上，本实施方式的源极配线层46形成于源极线SL上，经由源极线SL而电连接于介层插塞44b。即，本实施方式的源极配线层46未与介层插塞44b接触，而是经由源极线SL间接连接于介层插塞44b。这种构造例如能够通过在图3的步骤中在源极线SL上形成介层插塞44b而实现。在这种构造例如具有可以提高源极线SL的布局的自由度的优点。
图12是表示第5实施方式的半导体装置的构造的剖视图。
相对于第1实施方式的源极线SL包含作为半导体层的第1层SL1、及作为金属层的第2层SL2，本实施方式的源极线SL只包含作为半导体层的第1层SL1。这种构造例如能够通过在图3的步骤中省略形成第2层SL2而实现。在这种构造例如具有容易形成源极线SL的优点。另一方面，在如第1实施方式的构造例如具有可以减小源极配线层46与源极线SL的接触电阻的优点。
图13是表示第6实施方式的半导体装置的构造的剖视图。
本实施方式的源极配线层46与源极线SL的上表面及侧面接触。这种构造例如能够通过在图5的步骤中将源极线SL的侧方的层间绝缘膜13去除而实现。在这种构造中，例如具有可以减小源极配线层46与源极线SL的接触电阻的优点、或可以利用介层插塞44b消除GIDL(Gate Induced Drain Leakage，栅致漏极泄漏)的优点。
另外，本实施方式的源极线SL的第1层SL1例如相当于图4所示的衬底16的一部分。这种第1层SL1通过在图3的步骤中省略在衬底16上形成绝缘膜12、第2层SL2、及第1层SL1且在图5的步骤中将衬底16局部去除而形成。由此，衬底16的残余部分变为第1层SL1。然后，在图5的步骤中，在第1层SL1上形成第2层SL2。此情况下的第1层SL1例如是n-型硅层。在下述第7实施方式中也同样如此。
图14是表示第7实施方式的半导体装置的构造的剖视图。
本实施方式的源极配线层46也与第6实施方式的源极配线层46同样地，与源极线SL的上表面及侧面接触。但是，在本实施方式中，金属垫45的高度或源极配线层46的高度只在介层插塞44附近变低。这种构造例如能够通过在图5的步骤中只在介层插塞44附近将源极线SL的侧方的层间绝缘膜13去除而实现。这种构造例如具有可以减小源极配线层46与源极线SL的接触电阻的优点、或可以利用介层插塞44b消除GIDL的优点。
另外，图14的构造例如具有将层间绝缘膜13去除的区域变窄的优点。另一方面，图13的构造例如具有金属垫45内不会产生阶差的优点。
以上，对若干个实施方式进行了说明，但这些实施方式是只作为例子来提示的，并不意图限定发明的范围。在本说明书中说明的新颖的装置及方法能够以其它多种形态实施。此外，对于本说明书中说明的装置及方法的形态，可以在不脱离发明的主旨的范围内进行各种省略、置换、变更。随附的权利要求书及与其均等的范围旨在包含发明的范围或主旨所包含的这种形态或变化例。
[符号的说明]
1 阵列芯片
2 电路芯片
11 存储单元阵列
12 绝缘膜
13 层间绝缘膜
14 层间绝缘膜
15 衬底
16 衬底
21 阶梯构造部
22 接触插塞
23 字线层
24 介层插塞
31 晶体管
32 栅极电极
33 接触插塞
34 配线层
35 配线层
36 介层插塞
37 金属垫
41 金属垫
42 介层插塞
43 配线层
44 介层插塞
44a 介层插塞
44b 介层插塞
45 金属垫
45a 阻挡金属层
45b 配线材层
46 源极配线层
46a 阻挡金属层
46b 配线材层
47 钝化膜
48 配线层
48a 阻挡金属层
48b 配线材层
51 绝缘层
52 阻挡绝缘膜
53 电荷储存层
54 隧道绝缘膜
55 通道半导体层
56 核心绝缘膜

Claims (11)

1.一种半导体装置，具备：
第1衬底；
逻辑电路，设置在所述第1衬底上；
存储单元阵列，设置于所述逻辑电路的上方，且包含被积层的多个电极层、及设置于所述多个电极层上方的半导体层；
第1及第2插塞，设置于所述逻辑电路的上方，且电连接于所述逻辑电路；
焊盘，设置于所述第1插塞上；及
金属配线层，设置于所述存储单元阵列上，电连接于所述半导体层，且电连接于所述第2插塞；且
所述金属配线层是与所述半导体层的上表面及侧面相接而设置。
2.根据权利要求1所述的半导体装置，其中所述焊盘及所述金属配线层设置于相同的配线层内。
3.根据权利要求1或2所述的半导体装置，其中所述第1及第2插塞在所述存储单元阵列的外部设置于所述存储单元阵列的侧方。
4.根据权利要求1或2所述的半导体装置，其中所述半导体层包含于源极线，所述金属配线层包含于源极配线层。
5.根据权利要求1或2所述的半导体装置，其中所述金属配线层设置于所述半导体层上及所述第2插塞上。
6.根据权利要求1或2所述的半导体装置，其中
所述半导体层设置于所述第2插塞上，
所述金属配线层设置于所述半导体层上，经由所述半导体层而电连接于所述第2插塞。
7.根据权利要求1或2所述的半导体装置，其中
还具备设置于所述存储单元阵列上的第1绝缘膜，
所述金属配线层包含介隔所述第1绝缘膜而设置于所述存储单元阵列上的第1部分、及在所述第1绝缘膜内设置于所述存储单元阵列上的第2部分。
8.根据权利要求1或2所述的半导体装置，其中具备
多个第1垫，设置于所述第1衬底的上方；及
多个第2垫，设置于所述第1垫上；且
所述存储单元阵列、所述第1插塞、及所述第2插塞各经由任一所述第1垫及任一所述第2垫而电连接于所述逻辑电路。
9.一种半导体装置的制造方法，包括如下步骤：
在第1衬底上设置逻辑电路，
在所述逻辑电路的上方设置包含积层的多个电极层、及设置于所述多个电极层上方的半导体层的存储单元阵列，
在所述逻辑电路的上方设置电连接于所述逻辑电路的第1及第2插塞，
在所述第1插塞上形成焊盘，
在所述存储单元阵列上形成金属配线层，所述金属配线层与所述半导体层的上表面及侧面相接，且电连接于所述第2插塞。
10.一种半导体装置的制造方法，包括如下步骤：
在第1衬底上形成逻辑电路，
在第2衬底的上方形成包含半导体层、及积层于所述半导体层上方的多个电极层的存储单元阵列，
在所述第2衬底的上方形成第1及第2插塞，
通过将所述第1衬底与所述第2衬底贴合而在所述逻辑电路的上方配置所述存储单元阵列及所述第1及第2插塞，
在所述贴合后将所述第2衬底去除，
在所述第2衬底去除后，在所述第1插塞上形成焊盘，
在所述第2衬底去除后，在所述存储单元阵列上形成金属配线层，所述金属配线层与所述半导体层的上表面及侧面相接，且电连接于所述第2插塞。
11.根据权利要求10所述的半导体装置的制造方法，其中
所述焊盘及所述金属配线层是通过在所述第2衬底去除后对形成于所述第1插塞及所述存储单元阵列上的相同的配线层进行加工而形成。
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