CN112236858B - 用于Xtacking架构的焊盘引出结构 - Google Patents

用于Xtacking架构的焊盘引出结构 Download PDF

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Publication number
CN112236858B
CN112236858B CN202080002344.XA CN202080002344A CN112236858B CN 112236858 B CN112236858 B CN 112236858B CN 202080002344 A CN202080002344 A CN 202080002344A CN 112236858 B CN112236858 B CN 112236858B
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die
layer
conductive layer
contact structure
contact
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CN112236858A (zh
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肖亮
伍术
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202410284779.8A priority Critical patent/CN117936507A/zh
Priority to CN202410284893.0A priority patent/CN118039598A/zh
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Abstract

本公开内容提供了一种制造半导体器件的方法。该方法可以包括：面对面地键合第一管芯和第二管芯，第一管芯包括：衬底；在第一管芯的正面形成的在半导体层之上的晶体管，其中在衬底与半导体层之间具有绝缘层；以及在第一管芯的正面的延伸穿过绝缘层的第一接触结构。该方法还可以包括：使第一接触结构从第一管芯的背面暴露；从第一管芯的背面在绝缘层中形成接触孔以使半导体层暴露；以及在第一管芯的背面形成与第一接触结构连接的第一焊盘引出结构和在接触孔上与半导体层导电地连接的第二焊盘引出结构。

Description

用于Xtacking架构的焊盘引出结构
技术领域
概括地说，本申请描述了与半导体存储器件有关的实施例。
背景技术
已开发了三维(3D)NAND闪存存储技术以实现较高的数据存储密度而不需要较小的存储单元。3D NAND存储器件通常包括形成垂直存储单元串的阵列晶体管和形成外围电路的外围晶体管。在常规的3D NAND器件中，在相同衬底上处理阵列晶体管和外围晶体管。然而，在Xtacking架构中，包含阵列晶体管的阵列衬底和包含外围晶体管的外围衬底经由键合界面面对面地堆叠，其中晶体管被夹在这两个衬底之间。因此，Xtacking架构可以实现较高的存储密度、较简单的处理流程、以及较短的循环时间。
Xtacking架构还可以包括在阵列衬底或外围衬底的背面的垫出(pad-out)结构。因此，外部电路可以经由焊盘引出结构来向被夹在这两个衬底之间的晶体管提供控制信号。焊盘引出结构可以用贯穿硅触点(TSC)配置来制造。
发明内容
本公开内容的各方面提供了用于Xtacking架构的半导体器件的焊盘引出结构以及形成焊盘引出结构的方法。
根据第一方面，公开了一种具有焊盘引出结构的Xtacking架构的半导体器件。所述半导体器件可以包括面对面键合的第一管芯和第二管芯。所述第一管芯可以包括在所述第一管芯的背面的绝缘层、从所述第一管芯的正面延伸穿过所述绝缘层的第一部分的第一接触结构、在所述绝缘层的第二部分的正面的半导体层、以及在所述半导体层的正面形成的第一晶体管。
在一些实施例中，所述第一晶体管可以包括在所述第一管芯的正面在所述半导体层之上形成的存储单元。所述存储单元可以包括交替的字线层和绝缘层的堆叠体、以及延伸穿过所述堆叠体的多个沟道结构。在一些实施例中，所述第一管芯还可以包括在所述堆叠体的阶梯区域中形成的多个接触结构，所述多个接触结构与所述字线层耦合。所述阶梯区域可以处于所述堆叠体的边界或中间。此外，沟道结构可以包括由一个或多个绝缘层围绕的沟道层。
在一些实施例中，所述第二管芯可以包括衬底和在所述衬底的正面形成的用于所述存储单元的外围电路。
所述半导体器件还可以包括被设置在所述第一管芯的背面的第一焊盘引出结构，其中所述第一焊盘引出结构与所述第一接触结构电耦合。所述半导体器件还可以包括被设置在所述第一管芯的背面的第二焊盘引出结构，其中所述第二焊盘引出结构经由接触孔与所述半导体层电耦合，并且所述第二焊盘引出结构填充所述接触孔。
所述第一焊盘引出结构可以包括第一导电层的第一部分，并且所述第二焊盘引出结构可以包括所述第一导电层的第二部分。所述第一导电层的所述第一部分可以与所述第一导电层的所述第二部分间隔开。所述第一导电层可以由第一金属材料制成。在一些实施例中，所述第一焊盘引出结构还可以包括第二导电层的被设置在所述第一接触结构与第一垫层之间的第一部分。所述第二焊盘引出结构还可以包括所述第二导电层的被设置在所述半导体层与第二垫层之间的第二部分。所述第二导电层的所述第一部分可以与所述第二导电层的所述第二部分间隔开。所述第二导电层可以由第二金属材料制成。在一示例中，所述第一金属材料由铝制成，并且所述第二金属材料由钛制成。
在一些实施例中，所述第一焊盘引出结构可以经由所述第一接触结构、所述第一管芯与所述第二管芯之间的键合界面、以及所述第二管芯中的对应第二接触结构来与所述外围电路的输入/输出电路耦合。所述外围电路可以经由所述第一管芯中的对应第三接触结构、所述键合界面、以及所述第二管芯中的对应第四接触结构来与所述存储单元耦合。所述第二焊盘引出结构可以被配置为提供用于所述存储单元的阵列共源极。
在替代实施例中，所述第二管芯还可以包括在所述衬底的正面形成的存储单元，并且所述第一晶体管可以包括在所述衬底的正面形成的用于所述存储单元的外围电路。此外，所述第一焊盘引出结构可以经由所述第一接触结构来与所述外围电路的输入/输出电路耦合，并且所述外围电路可以经由所述第一管芯中的对应接触结构、所述第一管芯与所述第二管芯之间的键合界面、以及所述第二管芯中的对应接触结构来与所述存储单元耦合。
根据本公开内容的第二方面，提供了一种用于制造具有焊盘引出结构的Xtacking架构的半导体器件的方法。所述方法可以包括：面对面地键合第一管芯和第二管芯，其中所述第一管芯包括第一衬底、在所述第一衬底的正面的绝缘层、在所述第一管芯的正面的延伸穿过所述绝缘层的第一部分的第一接触结构、以及在所述绝缘层的第二部分的正面的半导体层。
在一些实施例中，所述第一管芯还可以包括在所述半导体层的正面形成的存储单元，并且所述第二管芯可以包括在第二衬底的正面的用于所述存储单元的外围电路。在一些实施例中，面对面地键合所述第一管芯和所述第二管芯包括：将与所述第一管芯中的所述第一接触结构连接的第一键合结构与连接到所述第二管芯中的所述外围电路中的输入/输出电路的第二键合结构进行键合。
在替代实施例中，所述第二管芯可以包括被设置在所述第二管芯的正面的存储单元，并且所述第一管芯还可以包括用于所述存储单元的外围电路。
所述方法还可以包括：通过将所述第一衬底从所述第一管芯的背面移除来使所述第一接触结构从所述第一管芯的背面暴露。在一些实施例中，所述方法可以包括：在移除所述第一衬底之后移除蚀刻停止层，其中所述蚀刻停止层被夹在所述第一衬底与所述绝缘层之间。
所述方法还可以包括：从所述第一管芯的背面在所述绝缘层的所述第二部分中形成接触孔，其中所述接触孔使所述半导体层暴露；以及在所述第一管芯的背面形成与所述第一接触结构导电地连接的第一焊盘引出结构和在所述接触孔上与所述半导体层导电地连接的第二焊盘引出结构。在一些实施例中，所述第二焊盘引出结构可以被配置为提供用于所述存储单元的阵列共源极。
此外，形成所述第一焊盘引出结构和所述第二焊盘引出结构可以包括：从所述第一管芯的背面在所述第一接触结构和所述半导体层之上形成第一导电层，并且所述第一导电层填充所述接触孔；以及从所述第一管芯的背面对所述第一导电层进行图案化，以形成与所述第一接触结构导电地连接的所述第一焊盘引出结构和与所述半导体层导电地连接的所述第二焊盘引出结构。在一些实施例中，可以在所述绝缘层的背面形成第二导电层，其中所述第二导电层与所述第一导电层和所述第一接触结构通过界面接合，并与所述第一导电层和所述半导体层通过界面接合，并且所述第二导电层是使用与所述第一导电层相同的光掩模来进行图案化的。
在一些实施例中，所述第一导电层可以由第一金属材料制成，并且所述第二导电层可以由第二金属材料制成。在一示例中，所述第一导电层至少包括钛，并且所述第二导电层至少包括铝。
附图说明
通过与附图一起阅读以下具体实施方式最佳地理解本公开内容的各方面。注意，根据行业中的标准实践，各个特征未按比例绘制。事实上，为讨论清晰起见，各个特征的尺寸可以增大或缩小。
图1是根据本公开内容的示例性实施例的半导体器件的横截面视图。
图2-图8是根据本公开内容的示例性实施例的在各个中间制造步骤处半导体器件的横截面视图。
图9是根据本公开内容的各实施例的用于制造示例性半导体器件的示例性过程的流程图。
具体实施方式
以下公开内容提供了用于实现所提供主题内容的不同特征的许多不同实施例或示例。以下描述组件和布置的特定示例以简化本公开内容。当然，这些仅仅是示例而并非旨在限制。例如，在以下描述中在第二特征之上或在第二特征上形成第一特征可以包括其中第一和第二特征可以直接接触的实施例，并且还可以包括其中可以在第一和第二特征之间形成另外的特征以使得第一和第二特征可能不直接接触的实施例。另外，本公开内容可以在各个示例中重复附图标记和/或字母。该重复是出于简化和清晰的目的，并且自身并不指定所讨论的各个实施例和/或配置之间的关系。
此外，在本文中可以使用空间相对术语(例如“下方”、“之下”、“下部”、“之上”、“上部”等等)以简化描述，以便描述一个元素或特征与另外元素或特征的关系，如附图中所示出的。空间相对术语旨在涵盖除了附图中所描绘的取向之外器件在使用或操作中的不同取向。装置可以以其它方式取向(旋转90度或处于其它取向)并且本文所使用的空间相对描述符同样可以相应地解读。
本公开内容提供了一种形成用于Xtacking架构的3D存储器件的焊盘引出结构的方法。该方法可以包括：键合第一管芯和第二管芯，移除第一管芯的衬底，形成接触孔，以及形成焊盘引出结构。与用于Xtacking架构的贯穿硅触点(TSC)垫相比，所公开的方法消除了沉积和蚀刻另外的介电质层和TSC金属的需要，从而简化了制造过程。
图1是根据本公开内容的示例性实施例的半导体器件100的横截面视图。如图所示，器件100可以包括第一管芯D1和第二管芯D2，这两个管芯以面对面的方式经由键合界面140键合在一起(电路侧是正面，并且衬底侧是背面)。第一管芯D1和第二管芯D2可以分别包括相应地彼此对准的键合结构141和142。此外，键合结构141可以与对应的键合结构142电耦合。
如图1中所示，第一管芯D1可以包括绝缘层103(例如，氧化硅)、在绝缘层103的正面的半导体层105(例如，掺杂多晶硅)、以及在绝缘层103的正面形成并延伸穿过绝缘层103的第一接触结构121(例如，钨)。
第一管芯D1还可以包括3D NAND存储单元。例如，交替的绝缘层111和字线层112(也被称为栅极层)的堆叠体也可以被设置在半导体层105的正面。该堆叠体可以包括阵列区域110，在该区域中形成至少一个沟道结构130并通过该堆叠体延伸到半导体层105。绝缘层111和字线层112的堆叠体以及沟道结构120可以形成晶体管的堆叠体，例如垂直存储单元串的阵列。在一些示例中，晶体管的堆叠体可以包括存储单元和选择晶体管，例如一个或多个底部选择晶体管、一个或多个顶部选择晶体管等等。在一些示例中，晶体管的堆叠体还可以包括一个或多个虚设选择晶体管。
绝缘层111可以由绝缘材料制成，例如氮化硅、二氧化硅等等。字线层112可以由栅极堆叠体材料制成，例如高介电常数(高k)栅极绝缘层、金属栅极电极等等。沟道结构130可以包括沟道层131(例如，多晶硅)，该沟道层被一个或多个绝缘层132围绕，例如遂穿层(例如，氧化硅)、电荷捕获层(例如，氮化硅)和阻隔层(例如，氧化硅)，这些层一起形成围绕沟道层131的氧化物-氮化物-氧化物结构。
此外，该堆叠体可以具有阶梯区域120，在该区域中形成多个第二接触结构122和第三接触结构123。第二接触结构122连接到字线层112，该字线层112可以充当垂直存储单元串的栅极和虚设栅极。第三接触结构123连接到半导体层105。注意，器件100可以具有各种阶梯配置，例如中心阶梯实现方式、侧部阶梯实现方式等等。
仍然在图1中，第一管芯D1还可以包括第一导电层171(也被称为垫层(padlayer))，该第一导电层171在第二导电层161(也被称为衬层(liner layer))的背面，该第二导电层161具有覆盖第一接触结构121的背面的第一部分161a和覆盖绝缘层103的孔的第二部分161b。第一导电层的第一部分171a和第一导电层的第二部分171b可以分别被设置在第二导电层的第一部分161a和第二部分161b的背面，以形成第一焊盘引出结构和第二焊盘引出结构。第一导电层的第一部分171a可以与第一接触结构121电耦合，并且第一导电层的第二部分171b可以与半导体层105电耦合。在该示例中，第一导电层171是铝，并且半导体层105是多晶硅。第二导电层161可以是粘合层，例如被设置在铝和多晶硅之间的具有10-20nm范围中的厚度的钛层。在一些实施例中，第二导电层161可以由在相对高温(例如，高于500℃)下的硅化钛形成。在其它示例中，第一导电层171可以由其它导电材料制成，并且第二导电层161可以是阻隔层、晶种层和/或粘合层。第二导电层161还可以用于减小接触电阻。在一些实施例中，第二导电层161可能不是必需的。
在图1的示例中，第一管芯D1可以包括3D存储单元，并且第二管芯D2可以包括外围电路(例如，地址解码器、驱动电路、感测放大器等等)。通常，第二管芯D2的外围电路可以将存储单元与外部电路对接。例如，外围电路经由第一焊盘引出结构(171a和161a)从外部电路接收指令，向存储单元提供控制信号，从存储单元接收数据，以及经由第一焊盘引出结构(171a和161a)向外部电路输出数据。此外，在一些实施例中，半导体层105耦合到用于存储单元阵列的阵列共源极(ACS)，以使得第二焊盘引出结构(171b和161b)可以提供用于ACS的输入/输出焊盘引出结构。
为简单起见，在第二管芯D2中示出了衬底191和在该衬底上形成的两个晶体管180。例如，晶体管180可以形成互补金属氧化物半导体(CMOS)。衬底191可以是任何合适的衬底，例如硅(Si)衬底、锗(Ge)衬底、硅锗(SiGe)衬底和/或绝缘体上硅(SOI)衬底。衬底可以包括半导体材料，例如，IV族半导体、III-V族化合物半导体或II-VI族氧化物半导体。IV族半导体可以包括Si、Ge或SiGe。衬底191可以是体晶片或外延层。注意，第一管芯D1初始地包括衬底，其中半导体层105和绝缘层103被设置在该衬底上。在形成焊盘引出结构(171和161)之前移除衬底。
在一些实施例中，半导体存储器件可以包括多个阵列管芯(例如，第一管芯D1)和CMOS管芯(例如，第二管芯D2)。多个阵列管芯和CMOS管芯可以堆叠并键合在一起。每个阵列管芯耦合到CMOS管芯的一部分，并且CMOS管芯可以以类似的方式单独或一起驱动阵列管芯。此外，在一些示例中，半导体器件100至少包括面对面键合的第一晶片和第二晶片。第一管芯D1与类似D1的其它阵列管芯一起被设置在第一晶片上，并且第二管芯D2与类似D2的其它CMOS管芯一起被设置在第二晶片上。第一晶片和第二晶片被键合在一起，以使得第一晶片上的阵列管芯与第二晶片上的对应CMOS管芯键合。
在替代实施例中，第一管芯D1可以包括外围电路，并且第二管芯D2可以包括3D存储单元(未示出)。焊盘引出结构(171和161)仍然可以被设置在第一管芯D1的背面。由于输入/输出信号不需要路由通过存储单元阵列管芯，因此输入/输出信号路径可以比图1中的信号路径短。
图2-图9是根据本公开内容的示例性实施例的半导体器件(例如器件100等等)在各个中间制造步骤处的横截面视图。器件100可以指任何适当的器件，例如，存储器电路、半导体芯片(或管芯)(其中在该半导体芯片上形成存储器电路)、半导体晶片(其中在该半导体晶片上形成多个半导体管芯)、半导体芯片的堆叠体、包括被组装在封装衬底上的一个或多个半导体芯片的半导体封装等等。
图2示出了最终将成为器件100的半导体器件200的横截面视图。应该理解，图2仅示出了器件200的一部分。类似于器件100，器件200可以包括第一管芯D1’(其对应于第一管芯D1)和第二管芯(未示出)(其对应于第二管芯D2)，这两个管芯经由键合界面(未示出)(其对应于键合界面140)键合在一起。为简单起见，图1中的第一管芯D1的键合结构141和覆盖层106在图2中省略。
如图所示，器件200可以包括在第一管芯D1’的背面的衬底201(例如，硅)以及在衬底201的正面的蚀刻停止层202(例如，氮化硅)。器件200还可以包括在蚀刻停止层202的正面的绝缘层203(例如，氧化硅)，该绝缘层203最终将成为图1中的绝缘层103。在一些实施例中，蚀刻停止层202可能不是必需的。
如图2中所示出的，器件200具有与图1中的器件100的对应组件类似地配置的组件。例如，第一接触结构221、半导体层205、交替的绝缘层211和字线层212的堆叠体、阵列区域210、阶梯区域220、沟道结构230、多个第二接触结构222、以及第三接触结构223分别与第一接触结构121、半导体层105、交替的绝缘层111和字线层112的堆叠体、阵列区域110、阶梯区域120、沟道结构130、多个第二接触结构122、以及第三接触结构123类似地配置。对这些组件的描述已在上文提供并且此处出于清晰目的将省略。
图3示出了在将衬底201从背面移除之后图2中的器件200。移除衬底201可以通过化学机械抛光(CMP)和/或湿法蚀刻来完成。蚀刻停止层202可以用于确定何时应该停止CMP和/或湿法蚀刻过程。
图4示出了在移除蚀刻停止层202和第一接触结构221的一部分之后图3中的器件200。因此，剩余的第一接触结构221和绝缘层203从背面暴露。类似于图3，移除蚀刻停止层202和第一接触结构221的该部分可以通过CMP过程来完成。替代地，可以通过第一蚀刻过程来移除蚀刻停止层202，并且可以通过第二蚀刻过程来移除第一接触结构221的该部分。在一些实施例中，移除第一接触结构221的该部分可能不是必需的。因此，第一接触结构221的该部分将被暴露(未示出)。此外，虽然被示为延伸到蚀刻停止层202，但在一些实施例中，第一接触结构221仅延伸到绝缘层203的背面203’(未示出)。因此，移除第一接触结构221的任何部分可能不是必需的。
在图5中，可以在器件200的绝缘层203中形成接触孔251，以使得半导体层205的一部分被暴露。接触孔251可以具有底部251’和两个侧壁251”。在图5的示例中，两个接触孔251被示为具有从正面扩展到背面的梯形横截面。要理解，可以形成任何数量的接触孔251，并且接触孔251可以具有其他形状，例如矩形。可以使用光阻剂作为由光刻过程定义的蚀刻掩模，通过蚀刻过程来形成接触孔251。
在图6中，可以形成第二导电层261(其最终将成为图1中的第二导电层161)以共形地涂覆暴露的第一接触结构221、绝缘层203、以及半导体层205的暴露部分。因此，第二导电层261覆盖接触孔251的底部251’和侧壁251”。第二导电层261可以由钛制成并通过化学气相沉积形成。第二导电层261可以具有10-20nm范围中的厚度。在一些实施例中，第二导电层261可能不是必需的，因此该步骤可以跳过。
在图7中，可以从背面在第二导电层261之上形成第一导电层271(其最终将成为图1中的第一导电层171)，以使得接触孔251可以填充有第一导电层271。第一导电层271可以是由铝制成的导电层并通过化学气相沉积形成。在第二导电层261是钛并且半导体层205是多晶硅的示例中，钛可以是铝和多晶硅之间的粘合层。另外，由于接触孔251，因此可以在第一导电层271的背侧形成凹陷结构272。
图8示出了在移除第一导电271的各部分和第二导电层261的各部分之后图7中的器件100。移除第一导电层271的各部分和第二导电层261的各部分可以通过用光阻剂和/或硬掩模层进行蚀刻来完成。因此，第一导电层的第一部分271a可以被设置在第二导电层的第一部分261a之上以形成第一焊盘引出结构，并且第一导电层的第二部分271b可以被设置在第二导电层的第二部分261b之上以形成第二焊盘引出结构。类似于器件100，外部电路(未示出)可以经由第一焊盘引出结构(271a和261a)向器件200的第二管芯D2’的外围电路(未示出)提供控制信号并从该外围电路接收数据，该第一焊盘引出结构经由第一接触结构221与外围电路耦合。外围电路随后可以与第一管芯D1’的晶体管相互作用。
图9是根据本公开内容的各实施例的用于制造示例性半导体器件(例如图1中的器件100，图8中的器件200等等)的示例性过程900的流程图。过程900开始于步骤S901，在步骤S901中面对面地键合第一管芯和第二管芯(电路侧是正面，并且衬底侧是背面)。第一管芯可以包括第一衬底、在半导体层中在第一管芯的正面形成的第一晶体管(其中在第一衬底和半导体层之间具有绝缘层)、以及在第一管芯的正面的延伸穿过绝缘层的第一接触结构。第二管芯可以包括第二衬底，该第二衬底具有在第二管芯的正面形成的结构。
为了将第一管芯键合到第二管芯，可以在第一管芯的正面形成多个第一键合结构(例如柱)，并且可以在第二管芯的正面形成多个第二键合结构。键合结构可以包括Cu、Ni和SnAg。可以在220℃以上的温度下操作键合过程以使键合结构融化，以使得第一键合结构可以形成与对应第二键合结构的连接。因此，第一管芯中的第一晶体管可以经由键合界面处的对应键合结构和这两个管芯中的接触结构来与第二管芯中的结构耦合。
此外，第一晶体管可以形成垂直存储单元串，并且第二管芯可以包括外围电路，如图1的示例中所示出的。在替代实施例中，第一晶体管可以包括外围电路，并且第二管芯可以包括存储单元。
在步骤S902处，将第一衬底从第一管芯的背面移除以使第一接触结构从第一管芯的背面暴露。因此，绝缘层也从第一管芯的背面暴露。在蚀刻停止层被夹在第一衬底与绝缘层之间的示例中，该蚀刻停止层也可以从第一管芯的背面移除。移除第一衬底和蚀刻停止层可以通过CMP和/或蚀刻来完成。
在步骤S903处，从第一管芯的背面在绝缘层中形成使半导体层的一部分暴露的接触孔。接触孔具有底部和两个侧壁。可以使用光刻技术来定义光阻剂和/或硬掩模层中的沟道孔图案，并且可以使用蚀刻技术将该图案转移到绝缘层并且随后移除该光阻剂和/或硬掩模层。
在步骤S904处，可以通过两个沉积过程、光刻过程和两个蚀刻过程在第一管芯的背面形成第一焊盘引出结构和第二焊盘引出结构。刚开始，可以通过第一沉积过程来形成共形的衬层，以使得衬层覆盖暴露的第一接触结构、绝缘层和半导体层的暴露部分。衬层还可以覆盖接触孔的底部和侧壁。随后，可以通过第二沉积过程从背面在衬层之上形成垫层。垫层可以填充接触孔并由于接触孔而在背面形成凹陷结构。之后，可以执行光刻过程以定义充当蚀刻掩模的光阻剂和/或硬掩模层的垫出图案。接着，可以执行两个蚀刻过程以将垫出图案转移到垫层和衬层以形成第一焊盘引出结构和第二焊盘引出结构。在一些实施例中，可以用单个蚀刻过程来代替这两个蚀刻过程。另外，将移除光阻剂和/或硬掩模层。
因此，第一焊盘引出结构导电地连接到第一接触结构，其中衬层的第一部分被夹在两者之间。外部电路可以经由第一焊盘引出结构和第一接触结构来与器件的外围电路耦合。类似地，在接触孔上形成第二焊盘引出结构并导电地耦合到半导体层，其中衬层的第二部分被夹在两者之间。第二焊盘引出结构可以被配置为提供用于存储单元的共源极阵列。
此外，在焊盘引出结构是铝并且半导体层是多晶硅的示例中，衬层可以由粘合材料(例如钛)制成。在其它示例中，焊盘引出结构可以由其它导电材料制成，并且衬层可以是阻隔层、晶种层和/或粘合层。衬层还可以用于减小接触电阻。在一些实施例中，衬层可能不是必需的。
应该注意，可以在过程900之前、之间和之后提供另外的步骤，并且对于过程900的另外实施例，所描述的一些步骤可以被代替、消除、或以不同顺序执行。例如，衬层的形成可能不是必需的。具体而言在步骤S904处，可以在定义蚀刻掩模的光刻过程之前，通过CMP过程来平面化具有凹陷结构的垫层。因此，焊盘引出结构在背面将具有平坦表面。另外，还可以使用剥离(lift-off)过程(其中在沉积衬层和垫层之前执行光刻过程)来形成焊盘引出结构。
本文所描述的各个实施例提供若干优点。例如，在相关的3D NAND存储器件中，用TSC配置形成焊盘引出结构，这需要在第一衬底的背面沉积和蚀刻层间介电质层(例如，氧化硅、氮化硅等等)和TSC金属(例如，钨)。所公开的方法可以简化制造过程并形成无TSC的焊盘引出结构。
前述内容概括了若干实施例的特征以使得本领域技术人员可以更好地理解本公开内容的各方面。本领域技术人员将意识到，他们可以容易地使用本公开内容作为用于设计或修改其它过程和结构以执行相同目的和/或实现本文所引入的实施例的相同优点的基础。本领域技术人员还将认识到，此类等效构造不会偏离本公开内容的精神和范围，并且他们可以对其作出各种改变、替换和更改而不会偏离本公开内容的精神和范围。

Claims (20)

1.一种用于制造半导体器件的方法，包括：
面对面地键合第一管芯和第二管芯，所述第一管芯包括第一衬底、在所述第一衬底的正面的绝缘层、在所述第一管芯的正面的延伸穿过所述绝缘层的第一部分的第一接触结构、以及在所述绝缘层的第二部分的正面的半导体层，所述绝缘层的一部分设置在所述第一接触结构与所述半导体层之间，并且所述绝缘层的所述一部分与所述第一接触结构和所述半导体层的面对所述第一接触结构的侧面直接接触；
通过将所述第一衬底从所述第一管芯的背面移除来使所述第一接触结构从所述第一管芯的背面暴露；
从所述第一管芯的背面在所述绝缘层的所述第二部分中形成接触孔，所述接触孔使所述半导体层暴露；以及
在所述第一管芯的背面形成与所述第一接触结构导电地连接的第一焊盘引出结构和在所述接触孔上与所述半导体层导电地连接的第二焊盘引出结构。
2.根据权利要求1所述的方法，其中，形成所述第一焊盘引出结构和所述第二焊盘引出结构还包括：
从所述第一管芯的背面在所述第一接触结构和所述半导体层之上形成第一导电层，所述第一导电层填充所述接触孔；以及
从所述第一管芯的背面对所述第一导电层进行图案化，以形成与所述第一接触结构导电地连接的所述第一焊盘引出结构和与所述半导体层导电地连接的所述第二焊盘引出结构。
3.根据权利要求2所述的方法，其中，形成所述第一焊盘引出结构和所述第二焊盘引出结构还包括：
在所述绝缘层的背面形成第二导电层，所述第二导电层与所述第一导电层和所述第一接触结构通过界面接合并且与所述第一导电层和所述半导体层通过界面接合；以及
使用与所述第一导电层相同的光掩模来对所述第二导电层进行图案化。
4.根据权利要求3所述的方法，其中：
所述第一导电层由第一金属材料制成；并且
所述第二导电层由第二金属材料制成。
5.根据权利要求4所述的方法，其中：
所述第一导电层至少包括铝；并且
所述第二导电层至少包括钛。
6.根据权利要求1所述的方法，其中，使所述第一接触结构从所述第一管芯的背面暴露还包括：
在移除所述第一衬底之后移除蚀刻停止层，所述蚀刻停止层被夹在所述第一衬底与所述绝缘层之间。
7.根据权利要求1所述的方法，其中：
所述第一管芯还包括形成在所述半导体层的正面的存储单元；并且
所述第二管芯包括在第二衬底的正面的用于所述存储单元的外围电路。
8.根据权利要求7所述的方法，其中，面对面地键合所述第一管芯和所述第二管芯还包括：
将与所述第一管芯中的所述第一接触结构连接的第一键合结构与连接到所述第二管芯中的所述外围电路中的输入/输出电路的第二键合结构键合。
9.根据权利要求7所述的方法，其中，所述第二焊盘引出结构被配置为提供用于所述存储单元的阵列共源极。
10.根据权利要求1所述的方法，其中：
所述第二管芯包括被设置在所述第二管芯的正面的存储单元；并且
所述第一管芯还包括用于所述存储单元的外围电路。
11.一种半导体器件，包括：
面对面键合的第一管芯和第二管芯，所述第一管芯包括在所述第一管芯的背面的绝缘层、从所述第一管芯的正面延伸穿过所述绝缘层的第一部分的第一接触结构、在所述绝缘层的第二部分的正面的半导体层、以及形成在所述半导体层的正面的第一晶体管，所述绝缘层的一部分设置在所述第一接触结构与所述半导体层之间，并且所述绝缘层的所述一部分与所述第一接触结构和所述半导体层的面对所述第一接触结构的侧面直接接触；
设置在所述第一管芯的背面的第一焊盘引出结构，所述第一焊盘引出结构与所述第一接触结构电耦合；以及
设置在所述第一管芯的背面的第二焊盘引出结构，所述第二焊盘引出结构与所述半导体层电耦合。
12.根据权利要求11所述的半导体器件，其中：
所述第一晶体管包括在所述第一管芯的正面在所述半导体层之上形成的存储单元；并且
所述第二管芯包括衬底和在所述衬底的正面形成的用于所述存储单元的外围电路。
13.根据权利要求12所述的半导体器件，其中，所述存储单元包括：
交替的字线层和绝缘层的堆叠体；以及
延伸穿过所述堆叠体的多个沟道结构，沟道结构包括由一个或多个绝缘层围绕的沟道层。
14.根据权利要求13所述的半导体器件，其中：
所述第一管芯还包括形成在所述堆叠体的阶梯区域中的多个接触结构，所述多个接触结构与所述字线层耦合，所述阶梯区域处于所述堆叠体的边界或中间。
15.根据权利要求12所述的半导体器件，其中：
所述第一焊盘引出结构经由所述第一接触结构、所述第一管芯与所述第二管芯之间的键合界面、以及所述第二管芯中的对应第二接触结构来与所述外围电路的输入/输出电路耦合；并且
所述外围电路经由所述第一管芯中的对应第三接触结构、所述键合界面、以及所述第二管芯中的对应第四接触结构来与所述存储单元耦合。
16.根据权利要求12所述的半导体器件，其中，所述第二焊盘出结构被配置为提供用于所述存储单元的阵列共源极。
17.根据权利要求11所述的半导体器件，其中：
所述第二管芯还包括形成在衬底的正面的存储单元；
所述第一晶体管包括形成在所述第一管芯的正面的用于所述存储单元的外围电路；
所述第一焊盘引出结构经由所述第一接触结构与所述外围电路的输入/输出电路耦合；并且
所述外围电路经由所述第一管芯中的对应接触结构、所述第一管芯与所述第二管芯之间的键合界面、以及所述第二管芯中的对应接触结构来与所述存储单元耦合。
18.根据权利要求11所述的半导体器件，其中：
所述第一焊盘引出结构包括第一导电层的第一部分；
所述第二焊盘引出结构包括所述第一导电层的第二部分；
所述第一导电层的所述第一部分与所述第一导电层的所述第二部分间隔开；并且
所述第一导电层由第一金属材料制成。
19.根据权利要求18所述的半导体器件，其中：
所述第一焊盘引出结构还包括第二导电层的设置在所述第一接触结构与所述第一导电层的所述第一部分之间的第一部分；
所述第二焊盘引出结构还包括所述第二导电层的设置在所述半导体层与所述第二导电层的所述第二部分之间的第二部分；
所述第二导电层的所述第一部分与所述第二导电层的所述第二部分间隔开；并且
所述第二导电层由第二金属材料制成。
20.根据权利要求19所述的半导体器件，其中：
所述第一金属材料由铝制成；并且
所述第二金属材料由钛制成。
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