TW202211457A - 半導體元件及用於製造半導體元件的方法 - Google Patents

半導體元件及用於製造半導體元件的方法 Download PDF

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TW202211457A
TW202211457A TW109138036A TW109138036A TW202211457A TW 202211457 A TW202211457 A TW 202211457A TW 109138036 A TW109138036 A TW 109138036A TW 109138036 A TW109138036 A TW 109138036A TW 202211457 A TW202211457 A TW 202211457A
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die
layer
conductive layer
pad
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TW109138036A
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TWI757946B (zh
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肖亮
術 伍
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大陸商長江存儲科技有限責任公司
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Abstract

本揭露內容提供了一種製造半導體元件的方法。該方法可以包括面對面地鍵合第一裸晶和第二裸晶，其中第一裸晶包括基底；在第一裸晶的正面形成的在半導體層之上的電晶體，其中在基底與半導體層之間具有絕緣層；以及在第一裸晶正面的延伸穿過絕緣層的第一接觸結構。該方法還可以包括：使第一接觸結構從第一裸晶的背面暴露；從第一裸晶的背面在絕緣層中形成接觸孔以使半導體層暴露；以及在第一裸晶的背面形成與第一接觸結構連接的第一焊墊引出結構和在接觸孔上與半導體層電連接的第二焊墊引出結構。

Description

半導體元件及其用於Xtacking架構的焊墊引出結構
概括地說，本申請描述了與半導體記憶體元件有關的實施例。
已開發了三維（3D）NAND快閃記憶體儲存技術以實現較高的資料儲存密度而不需要較小的儲存單元。3D NAND記憶體元件通常包括形成垂直儲存單元串的陣列電晶體和形成周邊電路的周邊電晶體。在常規的3D NAND元件中，在相同基底上處理陣列電晶體和周邊電晶體。然而，在Xtacking架構中，包含陣列電晶體的陣列基底和包含周邊電晶體的周邊基底經由鍵合介面面對面地堆疊，其中電晶體被夾在這兩個基底之間。因此，Xtacking架構可以實現較高的儲存密度、較簡單的處理流程、以及較短的迴圈時間。
Xtacking架構還可以包括在陣列基底或周邊基底的背面的墊出（pad-out）結構。因此，外部電路可以經由焊墊引出結構來向被夾在這兩個基底之間的電晶體提供控制訊號。焊墊引出結構可以用貫穿矽觸點（TSC）配置來製造。
本揭露內容的各方面提供了用於Xtacking架構的半導體元件的焊墊引出結構以及形成焊墊引出結構的方法。
根據第一方面，揭露了一種具有焊墊引出結構的Xtacking架構的半導體元件。所述半導體元件可以包括面對面鍵合的第一裸晶和第二裸晶。所述第一裸晶可以包括在所述第一裸晶的背面的絕緣層、從所述第一裸晶的正面延伸穿過所述絕緣層的第一部分的第一接觸結構、在所述絕緣層的第二部分的正面的半導體層、以及在所述半導體層的正面形成的第一電晶體。
在一些實施例中，所述第一電晶體可以包括在所述第一裸晶的正面在所述半導體層之上形成的儲存單元。所述儲存單元可以包括交替的字元線層和絕緣層的堆疊體、以及延伸穿過所述堆疊體的複數個通道結構。在一些實施例中，所述第一裸晶還可以包括在所述堆疊體的階梯區域中形成的複數個接觸結構，所述複數個接觸結構與所述字元線層耦合。所述階梯區域可以處於所述堆疊體的邊界或中間。此外，通道結構可以包括由一個或複數個絕緣層圍繞的通道層。
在一些實施例中，所述第二裸晶可以包括基底和在所述基底的正面形成的用於所述儲存單元的周邊電路。
所述半導體元件還可以包括被設置在所述第一裸晶的背面的第一焊墊引出結構，其中所述第一焊墊引出結構與所述第一接觸結構電耦合。所述半導體元件還可以包括被設置在所述第一裸晶的背面的第二焊墊引出結構，其中所述第二焊墊引出結構經由接觸孔與所述半導體層電耦合，並且所述第二焊墊引出結構填充所述接觸孔。
所述第一焊墊引出結構可以包括第一導電層的第一部分，並且所述第二焊墊引出結構可以包括所述第一導電層的第二部分。所述第一導電層的所述第一部分可以與所述第一導電層的所述第二部分間隔開。所述第一導電層可以由第一金屬材料製成。在一些實施例中，所述第一焊墊引出結構還可以包括第二導電層的被設置在所述第一接觸結構與第一墊層之間的第一部分。所述第二焊墊引出結構還可以包括所述第二導電層的被設置在所述半導體層與第二墊層之間的第二部分。所述第二導電層的所述第一部分可以與所述第二導電層的所述第二部分間隔開。所述第二導電層可以由第二金屬材料製成。在一示例中，所述第一金屬材料由鋁製成，並且所述第二金屬材料由鈦製成。
在一些實施例中，所述第一焊墊引出結構可以經由所述第一接觸結構、所述第一裸晶與所述第二裸晶之間的鍵合介面、以及所述第二裸晶中的對應第二接觸結構來與所述周邊電路的輸入/輸出電路耦合。所述周邊電路可以經由所述第一裸晶中的對應第三接觸結構、所述鍵合介面、以及所述第二裸晶中的對應第四接觸結構來與所述儲存單元耦合。所述第二焊墊引出結構可以被配置為提供用於所述儲存單元的陣列共源極。
在替代實施例中，所述第二裸晶還可以包括在所述基底的正面形成的儲存單元，並且所述第一電晶體可以包括在所述基底的正面形成的用於所述儲存單元的周邊電路。此外，所述第一焊墊引出結構可以經由所述第一接觸結構來與所述周邊電路的輸入/輸出電路耦合，並且所述周邊電路可以經由所述第一裸晶中的對應接觸結構、所述第一裸晶與所述第二裸晶之間的鍵合介面、以及所述第二裸晶中的對應接觸結構來與所述儲存單元耦合。
根據本揭露內容的第二方面，提供了一種用於製造具有焊墊引出結構的Xtacking架構的半導體元件的方法。所述方法可以包括：面對面地鍵合第一裸晶和第二裸晶，其中所述第一裸晶包括第一基底、在所述第一基底的正面的絕緣層、在所述第一裸晶的正面的延伸穿過所述絕緣層的第一部分的第一接觸結構、以及在所述絕緣層的第二部分的正面的半導體層。
在一些實施例中，所述第一裸晶還可以包括在所述半導體層的正面形成的儲存單元，並且所述第二裸晶可以包括在第二基底的正面的用於所述儲存單元的周邊電路。在一些實施例中，面對面地鍵合所述第一裸晶和所述第二裸晶包括：將與所述第一裸晶中的所述第一接觸結構連接的第一鍵合結構與連接到所述第二裸晶中的所述周邊電路中的輸入/輸出電路的第二鍵合結構進行鍵合。
在替代實施例中，所述第二裸晶可以包括被設置在所述第二裸晶的正面的儲存單元，並且所述第一裸晶還可以包括用於所述儲存單元的周邊電路。
所述方法還可以包括：透過將所述第一基底從所述第一裸晶的背面移除來使所述第一接觸結構從所述第一裸晶的背面暴露。在一些實施例中，所述方法可以包括：在移除所述第一基底之後移除蝕刻停止層，其中所述蝕刻停止層被夾在所述第一基底與所述絕緣層之間。
所述方法還可以包括：從所述第一裸晶的背面在所述絕緣層的所述第二部分中形成接觸孔，其中所述接觸孔使所述半導體層暴露；以及在所述第一裸晶的背面形成與所述第一接觸結構電連接的第一焊墊引出結構和在所述接觸孔上與所述半導體層電連接的第二焊墊引出結構。在一些實施例中，所述第二焊墊引出結構可以被配置為提供用於所述儲存單元的陣列共源極。
此外，形成所述第一焊墊引出結構和所述第二焊墊引出結構可以包括：從所述第一裸晶的背面在所述第一接觸結構和所述半導體層之上形成第一導電層，並且所述第一導電層填充所述接觸孔；以及從所述第一裸晶的背面對所述第一導電層進行圖案化，以形成與所述第一接觸結構電連接的所述第一焊墊引出結構和與所述半導體層電連接的所述第二焊墊引出結構。在一些實施例中，可以在所述絕緣層的背面形成第二導電層，其中所述第二導電層與所述第一導電層和所述第一接觸結構透過介面接合，並與所述第一導電層和所述半導體層透過介面接合，並且所述第二導電層是使用與所述第一導電層相同的光罩來進行圖案化的。
在一些實施例中，所述第一導電層可以由第一金屬材料製成，並且所述第二導電層可以由第二金屬材料製成。在一示例中，所述第一導電層至少包括鈦，並且所述第二導電層至少包括鋁。
以下揭露內容提供了用於實現所提供主題內容的不同特徵的許多不同實施例或示例。以下描述組件和佈置的特定示例以簡化本揭露內容。當然，這些僅僅是示例而並非旨在限制。例如，在以下描述中在第二特徵之上或在第二特徵上形成第一特徵可以包括其中第一和第二特徵可以直接接觸的實施例，並且還可以包括其中可以在第一和第二特徵之間形成另外的特徵以使得第一和第二特徵可能不直接接觸的實施例。另外，本揭露內容可以在各個示例中重複圖式標記和/或字母。該重複是出於簡化和清晰的目的，並且自身並不指定所討論的各個實施例和/或配置之間的關係。
此外，在本文中可以使用空間相對術語（例如“下方”、“之下”、“下部”、“之上”、“上部”等等）以簡化描述，以便描述一個元素或特徵與另外元素或特徵的關係，如圖式中所示出的。空間相對術語旨在涵蓋除了圖式中所描繪的取向之外元件在使用或操作中的不同取向。裝置可以以其它方式取向（旋轉90度或處於其它取向）並且本文所使用的空間相對描述符同樣可以相應地解讀。
本揭露內容提供了一種形成用於Xtacking架構的3D記憶體元件的焊墊引出結構的方法。該方法可以包括：鍵合第一裸晶和第二裸晶，移除第一裸晶的基底，形成接觸孔，以及形成焊墊引出結構。與用於Xtacking架構的貫穿矽觸點（TSC）墊相比，所揭露的方法消除了沉積和蝕刻另外的介電質層和TSC金屬的需要，從而簡化了製造過程。
圖1是根據本揭露內容的示例性實施例的半導體元件100的橫截面視圖。如圖所示，元件100可以包括第一裸晶D1和第二裸晶D2，這兩個裸晶以面對面的方式經由鍵合介面140鍵合在一起（電路側是正面，並且基底側是背面）。第一裸晶D1和第二裸晶D2可以分別包括相應地彼此對準的鍵合結構141和142。此外，鍵合結構141可以與對應的鍵合結構142電耦合。
如圖1中所示，第一裸晶D1可以包括絕緣層103（例如，氧化矽）、在絕緣層103的正面的半導體層105（例如，摻雜多晶矽）、以及在絕緣層103的正面形成並延伸穿過絕緣層103的第一接觸結構121（例如，鎢）。
第一裸晶D1還可以包括3D NAND儲存單元。例如，交替的絕緣層111和字元線層112（也被稱為閘極層）的堆疊體也可以被設置在半導體層105的正面。該堆疊體可以包括陣列區域110，在該區域中形成至少一個通道結構130並透過該堆疊體延伸到半導體層105。絕緣層111和字元線層112的堆疊體以及通道結構130可以形成電晶體的堆疊體，例如垂直儲存單元串的陣列。在一些示例中，電晶體的堆疊體可以包括儲存單元和選擇電晶體，例如一個或複數個底部選擇電晶體、一個或複數個頂部選擇電晶體等等。在一些示例中，電晶體的堆疊體還可以包括一個或複數個虛設選擇電晶體。
絕緣層111可以由絕緣材料製成，例如氮化矽、二氧化矽等等。字元線層112可以由閘極堆疊體材料製成，例如高介電常數（高k）閘極絕緣層、金屬閘極電極等等。通道結構130可以包括通道層131（例如，多晶矽），該通道層被一個或複數個絕緣層132圍繞，例如遂穿層（例如，氧化矽）、電荷捕獲層（例如，氮化矽）和阻隔層（例如，氧化矽），這些層一起形成圍繞通道層131的氧化物-氮化物-氧化物結構。
此外，該堆疊體可以具有階梯區域120，在該區域中形成複數個第二接觸結構122和第三接觸結構123。第二接觸結構122連接到字元線層112，該字元線層112可以充當垂直儲存單元串的閘極和虛設閘極。第三接觸結構123連接到半導體層105。注意，元件100可以具有各種階梯配置，例如中心階梯實現方式、側部階梯實現方式等等。
仍然在圖1中，第一裸晶D1還可以包括第一導電層171（也被稱為墊層（pad layer）），該第一導電層171在第二導電層161（也被稱為襯層（liner layer））的背面，該第二導電層161具有覆蓋第一接觸結構121的背面的第一部分161a和覆蓋絕緣層103的孔的第二部分161b。第一導電層的第一部分171a和第一導電層的第二部分171b可以分別被設置在第二導電層的第一部分161a和第二部分161b的背面，以形成第一焊墊引出結構和第二焊墊引出結構。第一導電層的第一部分171a可以與第一接觸結構121電耦合，並且第一導電層的第二部分171b可以與半導體層105電耦合。在該示例中，第一導電層171是鋁，並且半導體層105是多晶矽。第二導電層161可以是黏合層，例如被設置在鋁和多晶矽之間的具有10-20 nm範圍中的厚度的鈦層。在一些實施例中，第二導電層161可以由在相對高溫（例如，高於500 ºC）下的矽化鈦形成。在其它示例中，第一導電層171可以由其它導電材料製成，並且第二導電層161可以是阻隔層、晶種層和/或黏合層。第二導電層161還可以用於減小接觸電阻。在一些實施例中，第二導電層161可能不是必需的。
在圖1的示例中，第一裸晶D1可以包括3D儲存單元，並且第二裸晶D2可以包括周邊電路（例如，位址解碼器、驅動電路、感測放大器等等）。通常，第二裸晶D2的周邊電路可以將儲存單元與外部電路對接。例如，周邊電路經由第一焊墊引出結構（171a和161a）從外部電路接收指令，向儲存單元提供控制訊號，從儲存單元接收資料，以及經由第一焊墊引出結構（171a和161a）向外部電路輸出資料。此外，在一些實施例中，半導體層105耦合到用於儲存單元陣列的陣列共源極（ACS），以使得第二焊墊引出結構（171b和161b）可以提供用於ACS的輸入/輸出焊墊引出結構。
為簡單起見，在第二裸晶D2中示出了基底191和在該基底上形成的兩個電晶體180。例如，電晶體180可以形成互補金屬氧化物半導體（CMOS）。基底191可以是任何合適的基底，例如矽（Si）基底、鍺（Ge）基底、矽鍺（SiGe）基底和/或絕緣體上矽（SOI）基底。基底可以包括半導體材料，例如，IV族半導體、III-V族化合物半導體或II-VI族氧化物半導體。IV族半導體可以包括Si、Ge或SiGe。基底191可以是體晶片或磊晶層。注意，第一裸晶D1初始地包括基底，其中半導體層105和絕緣層103被設置在該基底上。在形成焊墊引出結構（171和161）之前移除基底。
在一些實施例中，半導體記憶體元件可以包括複數個陣列裸晶（例如，第一裸晶D1）和CMOS裸晶（例如，第二裸晶D2）。複數個陣列裸晶和CMOS裸晶可以堆疊並鍵合在一起。每個陣列裸晶耦合到CMOS裸晶的一部分，並且CMOS裸晶可以以類似的方式單獨或一起驅動陣列裸晶。此外，在一些示例中，半導體元件100至少包括面對面鍵合的第一晶片和第二晶片。第一裸晶D1與類似D1的其它陣列裸晶一起被設置在第一晶片上，並且第二裸晶D2與類似D2的其它CMOS裸晶一起被設置在第二晶片上。第一晶片和第二晶片被鍵合在一起，以使得第一晶片上的陣列裸晶與第二晶片上的對應CMOS裸晶鍵合。
在替代實施例中，第一裸晶D1可以包括周邊電路，並且第二裸晶D2可以包括3D儲存單元（未示出）。焊墊引出結構（171和161）仍然可以被設置在第一裸晶D1的背面。由於輸入/輸出訊號不需要路由透過儲存單元陣列裸晶，因此輸入/輸出訊號路徑可以比圖1中的訊號路徑短。
圖2到圖9是根據本揭露內容的示例性實施例的半導體元件（例如元件100等等）在各個中間製造步驟處的橫截面視圖。元件100可以指任何適當的元件，例如，記憶體電路、半導體晶片（或裸晶）（其中在該半導體晶片上形成記憶體電路）、半導體晶片（其中在該半導體晶片上形成複數個半導體裸晶）、半導體晶片的堆疊體、包括被組裝在封裝基底上的一個或複數個半導體晶片的半導體封裝等等。
圖2示出了最終將成為元件100的半導體元件200的橫截面視圖。應該理解，圖2僅示出了元件200的一部分。類似於元件100，元件200可以包括第一裸晶D1’（其對應於第一裸晶D1）和第二裸晶（未示出）（其對應於第二裸晶D2），這兩個裸晶經由鍵合介面（未示出）（其對應於鍵合介面140）鍵合在一起。為簡單起見，圖1中的第一裸晶D1的鍵合結構141和覆蓋層106在圖2中省略。
如圖所示，元件200可以包括在第一裸晶D1’的背面的基底201（例如，矽）以及在基底201的正面的蝕刻停止層202（例如，氮化矽）。元件200還可以包括在蝕刻停止層202的正面的絕緣層203（例如，氧化矽），該絕緣層203最終將成為圖1中的絕緣層103。在一些實施例中，蝕刻停止層202可能不是必需的。
如圖2中所示出的，元件200具有與圖1中的元件100的對應元件類似地配置的元件。例如，第一接觸結構221、半導體層205、交替的絕緣層211和字元線層212的堆疊體、陣列區域210、階梯區域220、通道結構230、複數個第二接觸結構222、以及第三接觸結構223分別與第一接觸結構121、半導體層105、交替的絕緣層111和字元線層112的堆疊體、陣列區域110、階梯區域120、通道結構130、複數個第二接觸結構122、以及第三接觸結構123類似地配置。對這些元件的描述已在上文提供並且此處出於清晰目的將省略。
圖3示出了在將基底201從背面移除之後圖2中的元件200。移除基底201可以透過化學機械拋光（CMP）和/或濕式蝕刻來完成。蝕刻停止層202可以用於確定何時應該停止CMP和/或濕式蝕刻製程。
圖4示出了在移除蝕刻停止層202和第一接觸結構221的一部分之後圖3中的元件200。因此，剩餘的第一接觸結構221和絕緣層203從背面暴露。類似於圖3，移除蝕刻停止層202和第一接觸結構221的該部分可以透過CMP製程來完成。替代地，可以透過第一蝕刻製程來移除蝕刻停止層202，並且可以透過第二蝕刻製程來移除第一接觸結構221的該部分。在一些實施例中，移除第一接觸結構221的該部分可能不是必需的。因此，第一接觸結構221的該部分將被暴露（未示出）。此外，雖然被示為延伸到蝕刻停止層202，但在一些實施例中，第一接觸結構221僅延伸到絕緣層203的背面203’（未示出）。因此，移除第一接觸結構221的任何部分可能不是必需的。
在圖5中，可以在元件200的絕緣層203中形成接觸孔251，以使得半導體層205的一部分被暴露。接觸孔251可以具有底部251’和兩個側壁251’’。在圖5的示例中，兩個接觸孔251被示為具有從正面擴展到背面的梯形橫截面。要理解，可以形成任何數量的接觸孔251，並且接觸孔251可以具有其他形狀，例如矩形。可以使用光阻劑作為由微影程序定義的蝕刻遮罩，透過蝕刻製程來形成接觸孔251。
在圖6中，可以形成第二導電層261（其最終將成為圖1中的第二導電層161）以共形地塗覆暴露的第一接觸結構221、絕緣層203、以及半導體層205的暴露部分。因此，第二導電層261覆蓋接觸孔251的底部251’和側壁251’’。第二導電層261可以由鈦製成並透過化學氣相沉積形成。第二導電層261可以具有10-20 nm範圍中的厚度。在一些實施例中，第二導電層261可能不是必需的，因此該步驟可以跳過。
在圖7中，可以從背面在第二導電層261之上形成第一導電層271（其最終將成為圖1中的第一導電層171），以使得接觸孔251可以填充有第一導電層271。第一導電層271可以是由鋁製成的導電層並透過化學氣相沉積形成。在第二導電層261是鈦並且半導體層205是多晶矽的示例中，鈦可以是鋁和多晶矽之間的黏合層。另外，由於接觸孔251，因此可以在第一導電層271的背側形成凹陷結構272。
圖8示出了在移除第一導電271的各部分和第二導電層261的各部分之後圖7中的元件200。移除第一導電層271的各部分和第二導電層261的各部分可以透過用光阻劑和/或硬遮罩層進行蝕刻來完成。因此，第一導電層的第一部分271a可以被設置在第二導電層的第一部分261a之上以形成第一焊墊引出結構，並且第一導電層的第二部分271b可以被設置在第二導電層的第二部分261b之上以形成第二焊墊引出結構。類似於元件100，外部電路（未示出）可以經由第一焊墊引出結構（271a和261a）向元件200的第二裸晶D2的周邊電路（未示出）提供控制訊號並從該周邊電路接收資料，該第一焊墊引出結構經由第一接觸結構221與周邊電路耦合。周邊電路隨後可以與第一裸晶D1’的電晶體相互作用。
圖9是根據本揭露內容的各實施例的用於製造示例性半導體元件（例如圖1中的元件100，圖8中的元件200等等）的示例性製程900的流程圖。製程900開始於步驟S901，在步驟S901中面對面地鍵合第一裸晶和第二裸晶（電路側是正面，並且基底側是背面）。第一裸晶可以包括第一基底、在半導體層中在第一裸晶的正面形成的第一電晶體（其中在第一基底和半導體層之間具有絕緣層）、以及在第一裸晶的正面的延伸穿過絕緣層的第一接觸結構。第二裸晶可以包括第二基底，該第二基底具有在第二裸晶的正面形成的結構。
為了將第一裸晶鍵合到第二裸晶，可以在第一裸晶的正面形成複數個第一鍵合結構（例如柱），並且可以在第二裸晶的正面形成複數個第二鍵合結構。鍵合結構可以包括Cu、Ni和SnAg。可以在220°C以上的溫度下操作鍵合製程以使鍵合結構融化，以使得第一鍵合結構可以形成與對應第二鍵合結構的連接。因此，第一裸晶中的第一電晶體可以經由鍵合介面處的對應鍵合結構和這兩個裸晶中的接觸結構來與第二裸晶中的結構耦合。
此外，第一電晶體可以形成垂直儲存單元串，並且第二裸晶可以包括周邊電路，如圖1的示例中所示出的。在替代實施例中，第一電晶體可以包括周邊電路，並且第二裸晶可以包括儲存單元。
在步驟S902中，將第一基底從第一裸晶的背面移除以使第一接觸結構從第一裸晶的背面暴露。因此，絕緣層也從第一裸晶的背面暴露。在蝕刻停止層被夾在第一基底與絕緣層之間的示例中，該蝕刻停止層也可以從第一裸晶的背面移除。移除第一基底和蝕刻停止層可以透過CMP和/或蝕刻來完成。
在步驟S903中，從第一裸晶的背面在絕緣層中形成使半導體層的一部分暴露的接觸孔。接觸孔具有底部和兩個側壁。可以使用微影技術來定義光阻劑和/或硬遮罩層中的通道孔圖案，並且可以使用蝕刻技術將該圖案轉移到絕緣層並且隨後移除該光阻劑和/或硬遮罩層。
在步驟S904中，可以透過兩個沉積製程、微影製程和兩個蝕刻製程在第一裸晶的背面形成第一焊墊引出結構和第二焊墊引出結構。剛開始，可以透過第一沉積製程來形成共形的襯層，以使得襯層覆蓋暴露的第一接觸結構、絕緣層和半導體層的暴露部分。襯層還可以覆蓋接觸孔的底部和側壁。隨後，可以透過第二沉積製程從背面在襯層之上形成墊層。墊層可以填充接觸孔並由於接觸孔而在背面形成凹陷結構。之後，可以進行微影製程以定義充當蝕刻遮罩的光阻劑和/或硬遮罩層的墊出圖案。接著，可以進行兩個蝕刻製程以將墊出圖案轉移到墊層和襯層以形成第一焊墊引出結構和第二焊墊引出結構。在一些實施例中，可以用單個蝕刻製程來代替這兩個蝕刻製程。另外，將移除光阻劑和/或硬遮罩層。
因此，第一焊墊引出結構電連接到第一接觸結構，其中襯層的第一部分被夾在兩者之間。外部電路可以經由第一焊墊引出結構和第一接觸結構來與元件的周邊電路耦合。類似地，在接觸孔上形成第二焊墊引出結構並電耦合到半導體層，其中襯層的第二部分被夾在兩者之間。第二焊墊引出結構可以被配置為提供用於儲存單元的共源極陣列。
此外，在焊墊引出結構是鋁並且半導體層是多晶矽的示例中，襯層可以由黏黏合材料（例如鈦）製成。在其它示例中，焊墊引出結構可以由其它導電材料製成，並且襯層可以是阻隔層、晶種層和/或黏合層。襯層還可以用於減小接觸電阻。在一些實施例中，襯層可能不是必需的。
應該注意，可以在製程900之前、之間和之後提供另外的步驟，並且對於製程900的另外實施例，所描述的一些步驟可以被代替、消除、或以不同順序執行。例如，襯層的形成可能不是必需的。具體而言在步驟S904中，可以在定義蝕刻遮罩的微影製程之前，透過CMP製程來平面化具有凹陷結構的墊層。因此，焊墊引出結構在背面將具有平坦表面。另外，還可以使用剝離（lift-off）製程（其中在沉積襯層和墊層之前進行微影製程）來形成焊墊引出結構。
本文所描述的各個實施例提供若干優點。例如，在相關的3D NAND記憶體元件中，用TSC配置形成焊墊引出結構，這需要在第一基底的背面沉積和蝕刻層間介電質層（例如，氧化矽、氮化矽等等）和TSC金屬（例如，鎢）。所公開的方法可以簡化製造過程並形成無TSC的焊墊引出結構。
前述內容概括了若干實施例的特徵以使得本領域技術人員可以更好地理解本揭露內容的各方面。本領域技術人員將意識到，他們可以容易地使用本揭露內容作為用於設計或修改其它製程和結構以進行相同目的和/或實現本文所引入的實施例的相同優點的基礎。本領域技術人員還將認識到，此類等效構造不會偏離本揭露內容的精神和範圍，並且他們可以對其作出各種改變、替換和更改而不會偏離本揭露內容的精神和範圍。
100,200:元件 103,111,132,203,211:絕緣層 105,205:半導體層 106:覆蓋層 110,210:陣列區域 112,212:字元線層 120,220:階梯區域 121,221:第一接觸結構 122,222:第二接觸結構 123,223:第三接觸結構 130,230:通道結構 131:通道層 140:鍵合介面 141,142:鍵合結構 161,261:第二導電層 161a,171a,271a,261a:第一部分 161b,171b,271b,261b:第二部分 171,271:第一導電層 180:電晶體 191,201:基底 202:蝕刻停止層 203:背面 251:接觸孔 251':底部 251":側壁 272:凹陷結構 900:過程 D1,D1':第一裸晶 D2:第二裸晶 S901～S904:步驟 X,Y,Z:方向
透過與圖式一起閱讀以下具體實施方式最佳地理解本揭露內容的各方面。注意，根據行業中的標準實踐，各個特徵未按比例繪製。事實上，為討論清晰起見，各個特徵的尺寸可以增大或縮小。 圖1是根據本揭露內容的示例性實施例的半導體元件的橫截面視圖。 圖2到圖8是根據本揭露內容的示例性實施例的在各個中間製造步驟的半導體元件的橫截面視圖。 圖9是根據本揭露內容的各實施例的用於製造示例性半導體元件的示例性製程的流程圖。
100:元件
103,111,132:絕緣層
105:半導體層
106:覆蓋層
110:陣列區域
112:字元線層
120:階梯區域
121:第一接觸結構
122:第二接觸結構
123:第三接觸結構
130:通道結構
131:通道層
140:鍵合介面
141,142:鍵合結構
161:第二導電層
161a,171a:第一部分
161b,171b:第二部分
171:第一導電層
180:電晶體
191:基底
D1,D1:第一裸晶
D2:第二裸晶

Claims (20)

  1. 一種用於製造半導體元件的方法，包括： 面對面地鍵合第一裸晶和第二裸晶，所述第一裸晶包括第一基底、在所述第一基底的正面的絕緣層、在所述第一裸晶的正面的延伸穿過所述絕緣層的第一部分的第一接觸結構、以及在所述絕緣層的第二部分的正面的半導體層； 透過將所述第一基底從所述第一裸晶的背面移除來使所述第一接觸結構從所述第一裸晶的背面暴露； 從所述第一裸晶的背面在所述絕緣層的所述第二部分中形成接觸孔，其中所述接觸孔使所述半導體層暴露；以及 在所述第一裸晶的背面形成與所述第一接觸結構電連接的第一焊墊引出結構和在所述接觸孔上與所述半導體層電連接的第二焊墊引出結構。
  2. 根據請求項1所述的方法，其中，形成所述第一焊墊引出結構和所述第二焊墊引出結構還包括： 從所述第一裸晶的背面在所述第一接觸結構和所述半導體層之上形成第一導電層，其中所述第一導電層填充所述接觸孔；以及 從所述第一裸晶的背面對所述第一導電層進行圖案化，以形成與所述第一接觸結構電連接的所述第一焊墊引出結構和與所述半導體層電連接的所述第二焊墊引出結構。
  3. 根據請求項2所述的方法，其中，形成所述第一焊墊引出結構和所述第二焊墊引出結構還包括： 在所述絕緣層的背面形成第二導電層，使所述第二導電層與所述第一導電層和所述第一接觸結構透過介面接合，並且與所述第一導電層和所述半導體層透過介面接合；以及 使用與所述第一導電層相同的光罩來對所述第二導電層進行圖案化。
  4. 根據請求項3所述的方法，其中： 所述第一導電層由第一金屬材料製成；並且 所述第二導電層由第二金屬材料製成。
  5. 根據請求項4所述的方法，其中： 所述第一導電層至少包括鋁；並且 所述第二導電層至少包括鈦。
  6. 根據請求項1所述的方法，其中，使所述第一接觸結構從所述第一裸晶的背面暴露還包括： 在移除所述第一基底之後移除蝕刻停止層，所述蝕刻停止層被夾在所述第一基底與所述絕緣層之間。
  7. 根據請求項1所述的方法，其中： 所述第一裸晶還包括形成在所述半導體層的正面的儲存單元；並且 所述第二裸晶包括在第二基底的正面的用於所述儲存單元的周邊電路。
  8. 根據請求項7所述的方法，其中，面對面地鍵合所述第一裸晶和所述第二裸晶還包括： 將與所述第一裸晶中的所述第一接觸結構連接的第一鍵合結構與連接到所述第二裸晶中的所述周邊電路中的輸入/輸出電路的第二鍵合結構鍵合。
  9. 根據請求項7所述的方法，其中，所述第二焊墊引出結構被配置為提供用於所述儲存單元的陣列共源極。
  10. 根據請求項1所述的方法，其中： 所述第二裸晶包括被設置在所述第二裸晶的正面的儲存單元；並且 所述第一裸晶還包括用於所述儲存單元的周邊電路。
  11. 一種半導體元件，包括： 面對面鍵合的第一裸晶和第二裸晶，所述第一裸晶包括在所述第一裸晶的背面的絕緣層、從所述第一裸晶的正面延伸穿過所述絕緣層的第一部分的第一接觸結構、在所述絕緣層的第二部分的正面的半導體層、以及形成在所述半導體層的正面的第一電晶體； 設置在所述第一裸晶的背面的第一焊墊引出結構，所述第一焊墊引出結構與所述第一接觸結構電耦合；以及 設置在所述第一裸晶的背面的第二焊墊引出結構，所述第二焊墊引出結構經由接觸孔與所述半導體層電耦合，所述第二焊墊引出結構填充所述接觸孔。
  12. 根據請求項11所述的半導體元件，其中： 所述第一電晶體包括在所述第一裸晶的正面且在所述半導體層之上形成的儲存單元；並且 所述第二裸晶包括基底和在所述基底的正面形成的用於所述儲存單元的周邊電路。
  13. 根據請求項12所述的半導體元件，其中，所述儲存單元包括： 交替的字元線層和絕緣層的堆疊體；以及 延伸穿過所述堆疊體的複數個通道結構，通道結構包括由一個或複數個絕緣層圍繞的通道層。
  14. 根據請求項13所述的半導體元件，其中： 所述第一裸晶還包括形成在所述堆疊體的階梯區域中的複數個接觸結構，所述複數個接觸結構與所述字元線層耦合，所述階梯區域處於所述堆疊體的邊界或中間。
  15. 根據請求項12所述的半導體元件，其中： 所述第一焊墊引出結構經由所述第一接觸結構、所述第一裸晶與所述第二裸晶之間的鍵合介面、以及所述第二裸晶中的對應第二接觸結構來與所述周邊電路的輸入/輸出電路耦合；並且 所述周邊電路經由所述第一裸晶中的對應第三接觸結構、所述鍵合介面、以及所述第二裸晶中的對應第四接觸結構來與所述儲存單元耦合。
  16. 根據請求項12所述的半導體元件，其中，所述第二焊墊出結構被配置為提供用於所述儲存單元的陣列共源極。
  17. 根據請求項11所述的半導體元件，其中： 所述第二裸晶還包括形成在所述基底的正面的儲存單元； 所述第一電晶體包括形成在所述基底的正面的用於所述儲存單元的周邊電路； 所述第一焊墊引出結構經由所述第一接觸結構與所述周邊電路的輸入/輸出電路耦合；並且 所述周邊電路經由所述第一裸晶中的對應接觸結構、所述第一裸晶與所述第二裸晶之間的鍵合介面、以及所述第二裸晶中的對應接觸結構來與所述儲存單元耦合。
  18. 根據請求項11所述的半導體元件，其中： 所述第一焊墊引出結構包括第一導電層的第一部分； 所述第二焊墊引出結構包括所述第一導電層的第二部分； 所述第一導電層的所述第一部分與所述第一導電層的所述第二部分間隔開；並且 所述第一導電層由第一金屬材料製成。
  19. 根據請求項18所述的半導體元件，其中： 所述第一焊墊引出結構還包括第二導電層的第一部分，且所述第一部分設置在所述第一接觸結構與第一焊墊層之間； 所述第二焊墊引出結構還包括所述第二導電層的第二部分，且所述第二部分設置在所述半導體層與第二焊墊引層之間； 所述第二導電層的所述第一部分與所述第二導電層的所述第二部分間隔開；並且 所述第二導電層由第二金屬材料製成。
  20. 根據請求項19所述的半導體元件，其中： 所述第一金屬材料由鋁製成；並且 所述第二金屬材料由鈦製成。
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