TW202347624A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202347624A
TW202347624A TW112129312A TW112129312A TW202347624A TW 202347624 A TW202347624 A TW 202347624A TW 112129312 A TW112129312 A TW 112129312A TW 112129312 A TW112129312 A TW 112129312A TW 202347624 A TW202347624 A TW 202347624A
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layer
wiring layer
mentioned
semiconductor device
plug
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TW112129312A
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内山泰宏
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日商鎧俠股份有限公司
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Abstract

本發明之實施形態提供一種能夠容易地將基板上之元件與記憶胞陣列內之電極層連接之半導體裝置及其製造方法。  根據實施形態，半導體裝置具備：第1基板；邏輯電路，其設置於上述第1基板上；及記憶胞陣列，其設置於上述邏輯電路之上方，且包含被積層之複數個電極層及設置於上述複數個電極層上方之半導體層。上述裝置還具備：第1及第2插塞，其等設置於上述邏輯電路之上方，且電性連接於上述邏輯電路；焊墊，其設置於上述第1插塞上；及金屬配線層，其設置於上述記憶胞陣列上，電性連接於上述半導體層，且電性連接於上述第2插塞。

Description

半導體裝置
本發明之實施形態係關於一種半導體裝置及其製造方法。
當於基板上方之較高之位置配置記憶胞陣列之情形時，存在難以將基板上之元件與記憶胞陣列內之電極層連接之情況。
實施形態提供一種能夠容易地將基板上之元件與記憶胞陣列內之電極層連接之半導體裝置及其製造方法。
根據實施形態，半導體裝置具備：第1基板；邏輯電路，其設置於上述第1基板上；及記憶胞陣列，其設置於上述邏輯電路上方，且包含被積層之複數個電極層、及設置於上述複數個電極層上方之半導體層。上述裝置還具備：第1及第2插塞，其等設置於上述邏輯電路之上方，且電性連接於上述邏輯電路；焊墊，其設置於上述第1插塞上；及金屬配線層，其設置於上述記憶胞陣列上，電性連接於上述半導體層，且電性連接於上述第2插塞。
以下，參考圖式對本發明之實施形態進行說明。於圖1至圖14中，對相同之構成附註相同之符號，並省略重複之說明。
(第1實施形態)  圖1係表示第1實施形態之半導體裝置之構造之剖視圖。圖1之半導體裝置係將陣列晶片1與電路晶片2貼合所得之三維記憶體。
陣列晶片1具備包含複數個記憶胞之記憶胞陣列11、記憶胞陣列11上之絕緣膜12、及記憶胞陣列11下之層間絕緣膜13。絕緣膜12係第1絕緣膜之例子。絕緣膜12例如係氧化矽膜或氮化矽膜。層間絕緣膜13例如係氧化矽膜或包含氧化矽膜及其他絕緣膜之積層膜。
電路晶片2設置於陣列晶片1下。符號S表示陣列晶片1與電路晶片2之貼合面。電路晶片2具備層間絕緣膜14、及層間絕緣膜14下之基板15。基板15係第1基板之例子。層間絕緣膜14例如係氧化矽膜、或包含氧化矽膜及其他絕緣膜之積層膜。基板15例如係矽基板等半導體基板。
圖1表示與基板15之表面平行且相互垂直之X方向及Y方向、及與基板15之表面垂直之Z方向。於本說明書中，將+Z方向作為上方向，將-Z方向作為下方向。-Z方向可以與重力方向一致，亦可不一致。
陣列晶片1具備複數條字元線WL、及源極線SL作為記憶胞陣列11內之複數個電極層。圖1表示記憶胞陣列11之階梯構造部21。各字元線WL經由接觸插塞22而與字元線層23電性連接。貫通複數條字元線WL之各柱狀部CL經由通孔插塞24而與位線BL電性連接，且與源極線SL電性連接。源極線SL設置於該等字元線WL上，且與下述源極配線層46電性連接。源極線SL包含作為半導體層之第1層SL1、及作為金屬層之第2層SL2。第2層SL2設置於第1層SL1上，作為障壁金屬層發揮功能。第1層SL1例如係n+型多晶矽層。第2層SL2例如係鈦(Ti)層、或包含鈦層及氮化鈦膜之積層膜。
電路晶片2具備複數個電晶體31。各電晶體31具備介隔閘極絕緣膜而設置於基板15上之閘極電極32、及設置於基板15內之未圖示之源極擴散層及汲極擴散層。又，電路晶片2具備：複數個接觸插塞33，其等設置於該等電晶體31之源極擴散層或汲極擴散層上；配線層34，其設置於該等接觸插塞33上，且包含複數條配線；及複數個配線層35，其等設置於配線層34上，且各包含複數條配線。
電路晶片2還具備：複數個通孔插塞36，其等設置於配線層35上；及複數個金屬墊37，其等設置於該等通孔插塞36上。金屬墊37例如係銅(Cu)層或鋁(Al)層。金屬墊37係第1墊之例子。本實施形態之電路晶片2作為控制陣列晶片1之動作之控制電路(邏輯電路)發揮功能。該控制電路由電晶體31等構成，且電性連接於金屬墊37。該控制電路例如包含記憶胞陣列11之周邊電路。
陣列晶片1具備：複數個金屬墊41，其等設置於金屬墊37上；複數個通孔插塞42，其等設置於金屬墊41上；及複數個配線層43，其等設置於該等通孔插塞42上，且各包含複數條配線。金屬墊41例如係銅層或鋁層。金屬墊41係第2墊之例子。又，陣列晶片1具備設置於配線層43上之複數個通孔插塞44，該等通孔插塞44包含複數個通孔插塞44a、及複數個通孔插塞44b。通孔插塞44a係第1插塞之例子，通孔插塞44b係第2插塞之例子。該等通孔插塞44在記憶胞陣列11之外部設置於記憶胞陣列11之側方。
陣列晶片1還具備金屬墊45、源極配線層46、及鈍化膜47。
金屬墊45設置於通孔插塞44a及絕緣膜12上，藉由與通孔插塞44a相接而電性連接於通孔插塞44a。本實施形態之金屬墊45作為半導體裝置之外部連接墊(焊墊)發揮功能。
源極配線層46設置於通孔插塞44b、記憶胞陣列11、及絕緣膜12上，藉由與通孔插塞44b相接而電性連接於通孔插塞44b。源極配線層46係金屬配線層之例子。源極配線層46包含：第1部分R1，其介隔絕緣膜12而設置於記憶胞陣列11上；及第2部分R2，其於絕緣膜12內設置於記憶胞陣列11上。其結果為，源極配線層46以與源極線SL相接之方式設置於源極線SL上，且電性連接於源極線SL。
本實施形態之金屬墊45及源極配線層46設置於1個相同之配線層內，分別包含障壁金屬層45a、46a、及障壁金屬層45a、46a上之配線材層45b、46b。障壁金屬層45a、46a例如係氮化鈦膜等之金屬層。配線材層45b、46b例如係鋁層等之金屬層。本實施形態之金屬墊45及源極配線層46如下文所述藉由於記憶胞陣列11及絕緣膜12上形成1個配線層並對該配線層進行加工而形成，於該配線層內形成金屬墊45及源極配線層46。
本實施形態之金屬墊45及源極配線層46分別設置於以貫通絕緣膜12之方式設置之通孔插塞44a、44b上。由此，通孔插塞44a之上端或通孔插塞44b之上端設置於較源極線SL之上表面更高之位置。同樣地，金屬墊45之下表面或源極配線層46之第1部分R1之下表面設置於較源極線SL之上表面更高之位置。另一方面，源極配線層46之第2部分R2之下表面與源極線SL之上表面相接。具體而言，源極配線層46之障壁金屬層46a與源極線SL之第2層SL2相接。
鈍化膜47設置於金屬墊45、源極配線層46、及絕緣膜12上。鈍化膜47例如係氧化矽膜等絕緣膜，且具有使金屬墊45之上表面露出之開口部P。金屬墊45能夠經由該開口部P利用焊接線、焊錫球、金屬凸塊等連接於安裝基板或其他裝置。
如圖1所示，記憶胞陣列11經由記憶胞陣列11下之金屬墊41、37等而與電路晶片2電性連接，例如，與構成邏輯電路之電晶體31等電性連接。對於金屬墊45或源極配線層46亦同樣如此。金屬墊45經由通孔插塞44a或通孔插塞44a下之金屬墊41、37等而與電路晶片2電性連接，源極配線層46經由通孔插塞44b或通孔插塞44b下之金屬墊41、37等而與電路晶片2電性連接。於本實施形態中，於圖1之截面中，記憶胞陣列11與電晶體31電性連接，於與圖1不同之截面中，金屬墊45或源極配線層46與電晶體31電性連接。
圖2係表示第1實施形態之柱狀部CL之構造之剖視圖。
如圖2所示，記憶胞陣列11具備交替地積層於層間絕緣膜13(圖1)上之複數條字元線WL及複數個絕緣層51。字元線WL例如係W(鎢)層。絕緣層51例如係氧化矽膜。
柱狀部CL依次包含阻擋絕緣膜52、電荷儲存層53、隧道絕緣膜54、通道半導體層55、及核心絕緣膜56。電荷儲存層53例如係氮化矽膜，介隔阻擋絕緣膜52而形成於字元線WL及絕緣層51之側面。電荷儲存層53亦可係多晶矽層等半導體層。通道半導體層55例如係多晶矽層，介隔隧道絕緣膜54而形成於電荷儲存層53之側面。阻擋絕緣膜52、隧道絕緣膜54、及核心絕緣膜56例如係氧化矽膜或金屬絕緣膜。
圖3至圖8係表示第1實施形態之半導體裝置之製造方法之剖視圖。
圖3表示包含複數個陣列晶片1之陣列晶圓W1、及包含複數個電路晶片2之電路晶圓W2。陣列晶圓W1亦稱為記憶晶圓，電路晶圓W2亦稱為CMOS晶圓。
請留意圖3之記憶晶圓W1之朝向與圖1之陣列晶片1之朝向相反。於本實施形態中，藉由將陣列晶圓W1與電路晶圓W2貼合而製造半導體裝置。圖3表示為了貼合而翻轉朝向之前之記憶晶圓W1，圖1表示為了貼合而翻轉朝向且被貼合及切割之後之陣列晶片1。請留意記憶晶圓W1具備設置於絕緣膜12下之基板16。基板16例如係矽基板等半導體基板。基板16係第2基板之例子。
於本實施形態中，首先，如圖3所示，於記憶晶圓W1之基板16上形成記憶胞陣列11、絕緣膜12、層間絕緣膜13、階梯構造部21、金屬墊41等，於電路晶圓W2之基板15上形成層間絕緣膜14、電晶體31、金屬墊37等。
例如，當於基板16上形成記憶胞陣列11等時，於基板16上依次形成絕緣膜12、源極線SL之第2層SL2、及源極線SL之第1層SL1，於源極線SL上交替地形成複數個絕緣層51(於圖3未圖示)及複數個犧牲層。接下來，於該等絕緣層51及犧牲層內形成複數個柱狀部CL，然後，將該等犧牲層置換為複數條字元線WL。如此，於基板16上介隔絕緣膜12而形成記憶胞陣列11。又，當於基板16上形成金屬墊41等時，於基板16上依次形成通孔插塞44、配線層43、通孔插塞42、及金屬墊41。此時，通孔插塞44以貫通絕緣膜12而到達至基板16之方式形成。
另一方面，當於基板15上形成電晶體31或金屬墊37時，於基板15上依次形成閘極電極32、接觸插塞33、配線層34、配線層35、通孔插塞36、及金屬墊37。
接下來，如圖4所示，利用機械壓力將陣列晶圓W1與電路晶圓W2貼合。由此，將層間絕緣膜13與層間絕緣膜14接著。接下來，於400℃下將陣列晶圓W1及電路晶圓W2退火。由此，金屬墊41與金屬墊37接合。其結果為，基板15與基板16介隔層間絕緣膜13或層間絕緣膜14而貼合。圖4表示該貼合之結果、配置於基板15之上方之記憶胞陣列11、插塞44、基板16等。
接下來，藉由CMP(Chemical Mechanical Polishing，化學機械研磨)將基板15薄膜化之後，藉由CMP將基板16去除，使絕緣膜12露出(圖5)。接下來，藉由微影術及蝕刻於絕緣膜12形成開口部H1，使記憶胞陣列11之源極線SL於開口部H1內露出(圖5)。
接下來，藉由濺鍍於源極線SL及絕緣膜12上形成配線層48(圖6)。配線層48包含形成於源極線SL及絕緣膜12上之障壁金屬層48a、及形成於障壁金屬層48a上之配線材層48b。障壁金屬層48a例如為氮化鈦膜。配線材層48b例如為鋁層。
接下來，藉由RIE(Reactive Ion Etching，反應式離子刻蝕)對配線層48進行加工(圖7)。其結果為，於配線層48內形成金屬墊45及源極配線層46。金屬墊45形成於通孔插塞44a上，源極配線層46形成於通孔插塞44b及源極線SL上。圖7之源極配線層46包含介隔絕緣膜12而設置於記憶胞陣列11上之第1部分R1、及於絕緣膜12內設置於記憶胞陣列11上之第2部分R2。
如此，本實施形態之金屬墊45及源極配線層46藉由對相同之配線層48進行加工而形成。金屬墊45之障壁金屬層45a及源極配線層46之障壁金屬層46a來自配線層48之障壁金屬層48a，金屬墊45之配線材層45b、及源極配線層46之配線材層46b來自配線層48之配線材層48b。
接下來，於金屬墊45、源極配線層46、及絕緣膜12上形成鈍化膜47(圖8)。然後，於鈍化膜47形成開口部P，使金屬墊45於開口部P內露出(參考圖1)。進而，將陣列晶圓W1及電路晶圓W2切斷為複數個晶片。如此，製造本實施形態之半導體裝置。
以下，再次參考圖1，對本實施形態之源極線SL或源極配線層46進行說明。
當考慮源極配線層46之配置時，考慮將源極配線層46與字元線層23同樣地配置於記憶胞陣列11之下。於此情形時，為了將源極線SL與源極配線層46電性連接，必須將貫通複數條字元線WL之複數個接觸插塞設置於源極線SL與源極配線層46之間。此種接觸插塞之存在會成為提高半導體裝置之積體度之阻礙。
又，源極線SL係於將陣列晶圓W1與電路晶圓W2貼合之前形成，因此，難以使用厚金屬層形成源極線SL。理由在於金屬層會受到用於貼合之退火之影響。因此，考慮源極線SL是僅由半導體層形成還是由半導體層及薄金屬層形成。然而，於該等情形時，源極線SL之電阻會變高，因此，要求於源極線SL與源極配線層46之間配置多數個接觸插塞，抑制源極線SL之電壓效應。然而，此種多數個接觸插塞之存在成為提高半導體裝置之積體度之較大之阻礙。
因此，於本實施形態中，藉由將源極配線層46配置於記憶胞陣列11上、具體而言將源極配線層46配置於源極線SL上而使之與源極線SL電性連接。由此，無需將貫通複數條字元線WL之複數個接觸插塞設置於源極線SL與源極配線層46之間，從而可提高半導體裝置之積體度。
於此情形時，源極配線層46配置於基板15上方之較高之位置，因此，亦認為難以與電晶體31等電性連接。理由在於，本實施形態之半導體裝置藉由陣列晶圓W1與電路晶圓W2之貼合而形成，因此，記憶胞陣列11配置於基板15上方之較高之位置，記憶胞陣列11上之源極配線層46配置於基板15上之更高之位置。若將源極配線層46配置於記憶胞陣列11上，則與將源極配線層46配置於記憶胞陣列11下之情況相比，源極配線層46與電晶體31之距離變遠。
然而，本實施形態之源極配線層46配置於與金屬墊(焊墊)45相同高度，因此，可利用與金屬墊45相同之方法連接於電晶體31。即，與利用通孔插塞44a將金屬墊45連接於電晶體31同樣地，可利用通孔插塞44b將源極配線層46連接於電晶體31。由此，即便源極配線層46配置於基板15上方之較高之位置，亦可容易地將源極配線層46與電晶體31等連接。由此，根據本實施形態，能夠利用此種源極配線層46或通孔插塞44b容易地將源極線SL與電晶體31等連接。
又，由於本實施形態之源極配線層46係於將陣列晶圓W1與電路晶圓W2貼合之後形成，故而可避免源極配線層46受到用於貼合之退火之影響。由此，容易使用厚金屬層形成源極配線層46，從而能夠減少源極線SL及源極配線層46之合計電阻。由此，能夠減少通孔插塞44b之根數，從而提高半導體裝置之積體度。
再者，於本實施形態中，已對將源極線SL與電晶體31電性連接之源極配線層46進行了說明，但本實施形態亦能同樣地應用於將記憶胞陣列11內之其他電極層與基板15上之其他元件電性連接之配線層。此種電極層之例子係字元線WL或選擇線等，此種元件之例子係記憶胞或二極體等。
又，本實施形態之金屬墊45及源極配線層46包含於相同之配線層內，但亦可包含於不同之配線層內。例如，亦可形成某一配線層，對該配線層進行加工而形成金屬墊45，然後，形成另一配線層，對該另一配線層進行加工而形成源極配線層46。但是，於金屬墊45及源極配線層46包含於相同之配線層內之情形時，可獲得能夠同時形成金屬墊45及源極配線層46之優點。
如上所述，本實施形態之半導體裝置具備源極配線層46，該源極配線層46設置於記憶胞陣列11上，電性連接於源極線SL，且電性連接於通孔插塞44b。由此，根據本實施形態，能夠容易地將基板15上之電晶體31等元件與記憶胞陣列11內之源極線SL等電極層連接。
再者，於本實施形態中，將陣列晶圓W1與電路晶圓W2貼合，但亦可取而代之將陣列晶圓W1彼此貼合。參考圖1至圖8而於前文中所述之內容或參考圖9至圖14將於後文中所述之內容亦能應用於陣列晶圓W1彼此之貼合。
又，圖1表示層間絕緣膜13與層間絕緣膜14之交界面或金屬墊41與金屬墊37之交界面，但通常於上述退火後無法觀察到該等交界面。然而，該等交界面所在之位置例如可通過檢測金屬墊41之側面或金屬墊37之側面之斜率或金屬墊41之側面與金屬墊37之位置偏移來推定。
(第2至第7實施形態)  圖9係表示第2實施形態之半導體裝置之構造之剖視圖。
相對於第1實施形態之源極配線層46介隔絕緣膜12而形成於源極線SL上，本實施形態之源極配線層46未介隔絕緣膜12而形成於源極線SL上。此種構造例如能夠藉由在圖3之步驟中省略形成絕緣膜12，或於圖5之步驟中將絕緣膜12全部去除而實現。於此種構造中例如有可減小源極配線層46與源極線SL之接觸電阻之優點。
圖10係表示第3實施形態之半導體裝置之構造之剖視圖。
相對於第1實施形態之源極配線層46具備一個第2部分R2，本實施形態之源極配線層46具備複數個第2部分R2。此種構造例如能夠藉由在圖5之步驟中形成複數個開口部H1而實現。此種構造例如具有可提高源極配線層46與源極線SL之接觸部位之佈局之自由度之優點。
圖11係表示第4實施形態之半導體裝置之構造之剖視圖。
本實施形態之源極線SL形成於通孔插塞44b上，本實施形態之源極配線層46形成於源極線SL上，經由源極線SL而電性連接於通孔插塞44b。即，本實施形態之源極配線層46未與通孔插塞44b接觸，而係經由源極線SL間接連接於通孔插塞44b。此種構造例如能夠藉由在圖3之步驟中於源極線SL上形成通孔插塞44b而實現。於此種構造例如具有可提高源極線SL之佈局之自由度之優點。
圖12係表示第5實施形態之半導體裝置之構造之剖視圖。
相對於第1實施形態之源極線SL包含作為半導體層之第1層SL1、及作為金屬層之第2層SL2，本實施形態之源極線SL僅包含作為半導體層之第1層SL1。此種構造例如能夠藉由在圖3之步驟中省略形成第2層SL2而實現。於此種構造例如具有容易形成源極線SL之優點。另一方面，於如第1實施形態之構造例如具有可減小源極配線層46與源極線SL之接觸電阻之優點。
圖13係表示第6實施形態之半導體裝置之構造之剖視圖。
本實施形態之源極配線層46與源極線SL之上表面及側面接觸。此種構造例如能夠藉由在圖5之步驟中將源極線SL之側方之層間絕緣膜13去除而實現。於此種構造中，例如具有可減小源極配線層46與源極線SL之接觸電阻之優點、或可利用通孔插塞44b消除GIDL(Gate Induced Drain Leakage，閘極誘導汲極漏電流)之優點。
再者，本實施形態之源極線SL之第1層SL1例如相當於圖4所示之基板16之一部分。此種第1層SL1藉由在圖3之步驟中省略於基板16上形成絕緣膜12、第2層SL2、及第1層SL1且於圖5之步驟中將基板16局部去除而形成。由此，基板16之殘餘部分變為第1層SL1。然後，於圖5之步驟中，於第1層SL1上形成第2層SL2。此情形之第1層SL1例如係n-型矽層。於下述第7實施形態中亦同樣如此。
圖14係表示第7實施形態之半導體裝置之構造之剖視圖。
本實施形態之源極配線層46亦與第6實施形態之源極配線層46同樣地，與源極線SL之上表面及側面接觸。但是，於本實施形態中，金屬墊45之高度或源極配線層46之高度僅於通孔插塞44附近變低。此種構造例如能夠藉由在圖5之步驟中僅於通孔插塞44附近將源極線SL之側方之層間絕緣膜13去除而實現。此種構造例如具有可減小源極配線層46與源極線SL之接觸電阻之優點、或可利用通孔插塞44b消除GIDL之優點。
再者，圖14之構造例如具有將層間絕緣膜13去除之區域變窄之優點。另一方面，圖13之構造例如具有金屬墊45內不會產生階差之優點。
以上，對若干個實施形態進行了說明，但該等實施形態係僅作為例子來提示，並非意圖限定發明之範圍。於本說明書中說明之新穎之裝置及方法能夠以其他多種形態實施。又，對於本說明書中說明之裝置及方法之形態，可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。隨附之申請專利範圍及與其均等之範圍意圖包含發明之範圍或主旨所包含之此種形態或變化例。 [相關申請案]
本申請案享有以日本專利申請案2019-169763號(申請日：2019年9月18日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1:陣列晶片 2:電路晶片 11:記憶胞陣列 12:絕緣膜 13:層間絕緣膜 14:層間絕緣膜 15:基板 16:基板 21:階梯構造部 22:接觸插塞 23:字元線層 24:通孔插塞 31:電晶體 32:閘極電極 33:接觸插塞 34:配線層 35:配線層 36:通孔插塞 37:金屬墊 41:金屬墊 42:通孔插塞 43:配線層 44:通孔插塞 44a:通孔插塞 44b:通孔插塞 45:金屬墊 45a:障壁金屬層 45b:配線材層 46:源極配線層 46a:障壁金屬層 46b:配線材層 47:鈍化膜 48:配線層 48a:障壁金屬層 48b:配線材層 51:絕緣層 52:阻擋絕緣膜 53:電荷儲存層 54:隧道絕緣膜 55:通道半導體層 56:核心絕緣膜 BL:位線 CL:柱狀部 H1:開口部 P:開口部 R1:第1部分 R2:第2部分 SL:源極線 SL1:第1層 SL2:第2層 W1:陣列晶圓 W2:電路晶圓 WL:字元線 X:方向 Y:方向 Z:方向
圖1係表示第1實施形態之半導體裝置之構造之剖視圖。  圖2係表示第1實施形態之柱狀部之構造之剖視圖。  圖3～8係表示第1實施形態之半導體裝置之製造方法之剖視圖。  圖9係表示第2實施形態之半導體裝置之構造之剖視圖。  圖10係表示第3實施形態之半導體裝置之構造之剖視圖。  圖11係表示第4實施形態之半導體裝置之構造之剖視圖。  圖12係表示第5實施形態之半導體裝置之構造之剖視圖。  圖13係表示第6實施形態之半導體裝置之構造之剖視圖。  圖14係表示第7實施形態之半導體裝置之構造之剖視圖。
1:陣列晶片
2:電路晶片
11:記憶胞陣列
12:絕緣膜
13:層間絕緣膜
14:層間絕緣膜
15:基板
21:階梯構造部
22:接觸插塞
23:字元線層
24:通孔插塞
31:電晶體
32:閘極電極
33:接觸插塞
34:配線層
35:配線層
36:通孔插塞
37:金屬墊
41:金屬墊
42:通孔插塞
43:配線層
44:通孔插塞
44a:通孔插塞
44b:通孔插塞
45:金屬墊
45a:障壁金屬層
45b:配線材層
46:源極配線層
46a:障壁金屬層
46b:配線材層
47:鈍化膜
BL:位線
CL:柱狀部
P:開口部
R1:第1部分
R2:第2部分
SL:源極線
SL1:第1層
SL2:第2層
WL:字元線
X:方向
Y:方向
Z:方向

Claims (10)

  1. 一種半導體裝置，其包含： 第1基板； 第1電晶體，其設置於上述第1基板上； 記憶胞陣列，其設置於上述第1電晶體之上方，且包含：被積層之複數個電極層、及設置於上述複數個電極層之上方之半導體層； 第1插塞，其設置於上述第1電晶體之上方，且電性連接於上述第1電晶體；及 金屬配線層，其具有：分別相接於上述半導體層之第1部分及第2部分；第3部分，設置於上述第1部分與上述第2部分之間，且底面較上述第1部分及上述第2部分之底面高；設置於上述半導體層之上方，且電性連接於上述第1插塞。
  2. 如請求項1之半導體裝置，其進而包含： 第1絕緣膜，其相接於上述半導體層之上方而設置；且 上述第3部分介隔上述第1絕緣膜相接於上述半導體層之上方而設置。
  3. 如請求項1或2之半導體裝置，其中 上述記憶胞陣列包含：包括通道半導體層之柱； 上述第3部分設置於上述柱之上方。
  4. 如請求項1或2之半導體裝置，其中 上述記憶胞陣列包含：包括通道半導體層之柱； 上述第1部分設置於上述柱之上方。
  5. 如請求項1之半導體裝置，其進而包含： 第2插塞，其設置於上述第1電晶體之上方，且電性連接於上述第1電晶體； 焊墊，其設置於上述第2插塞上；且 上述焊墊與上述金屬配線層設置於相同之配線層內。
  6. 如請求項5之半導體裝置，其中上述第1及第2插塞係在上述記憶胞陣列之外部設置於上述記憶胞陣列之側方。
  7. 如請求項5之半導體裝置，其包含： 複數個第1墊，其等設置於上述第1基板之上方；及 複數個第2墊，其等設置於上述第1墊上；且 上述記憶胞陣列、上述第1插塞、及上述第2插塞各經由任一上述第1墊及任一上述第2墊而電性連接於上述第1電晶體。
  8. 如請求項1之半導體裝置，其中上述金屬配線層設置於上述半導體層之上表面及側面。
  9. 如請求項1或2之半導體裝置，其中上述金屬配線層設置於上述半導體層上及上述第1插塞上。
  10. 如請求項1或2之半導體裝置，其中 上述半導體層設置於上述第1插塞上； 上述金屬配線層設置於上述半導體層上，經由上述半導體層而電性連接於上述第1插塞。
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