JP7421292B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP7421292B2 JP7421292B2 JP2019165648A JP2019165648A JP7421292B2 JP 7421292 B2 JP7421292 B2 JP 7421292B2 JP 2019165648 A JP2019165648 A JP 2019165648A JP 2019165648 A JP2019165648 A JP 2019165648A JP 7421292 B2 JP7421292 B2 JP 7421292B2
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- 239000004065 semiconductor Substances 0.000 title claims description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000000758 substrate Substances 0.000 claims description 218
- 238000000034 method Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 229910052593 corundum Inorganic materials 0.000 claims 1
- 229910001845 yogo sapphire Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 60
- 239000010408 film Substances 0.000 description 34
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021426 porous silicon Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 polycrystal Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/14—Integrated circuits
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Description
図1(A)~図2(C)は、第1実施形態による半導体メモリの製造方法を示す断面図である。本実施形態は、複数のメモリセルを三次元配置した立体型メモリセルアレイと、該メモリセルアレイを制御するCMOS(Complementary Metal-Oxide-Semiconductor)回路とを備えたNAND型フラッシュメモリの製造方法である。メモリセルアレイおよびCMOS回路は、基板10の表面に対して略垂直方向に積層されている。尚、本実施形態は、NAND型フラッシュメモリに限定されず、半導体素子を積層して形成する半導体装置であれば適用可能である。
図8(A)~図8(C)は、第2実施形態による半導体メモリの製造方法を示す断面図である。第2実施形態では、第3基板としての基板40は、基板10に接合された後に薄膜化されている。尚、図8(A)~図8(C)は、図1(A)~図1(C)に続く半導体メモリの製造方法を示している。
図9(A)~図9(C)は、第3実施形態による半導体メモリの製造方法を示す断面図である。第3実施形態では、第3基板としての基板40は、基板10から剥離された後に薄膜化されている。尚、図9(A)~図9(C)は、図1(A)~図1(C)に続く半導体メモリの製造方法を示している。
図10(A)~図10(C)は、第4実施形態による半導体メモリの製造方法を示す断面図である。第4実施形態では、基板40の研磨後、さらに第4基板としての基板70を基板40に接合し、基板70とともに基板10、40を基板20から剥離する。尚、図10(A)~図10(C)は、図8(B)に続く半導体メモリの製造方法を示している。
Claims (9)
- 第1弾性率を有する第1基板を、前記第1弾性率よりも高い第2弾性率を有する第2基板上に接合し、
前記第1基板を前記第2基板に接合した後、前記第1基板を薄膜化し、
薄膜化された前記第1基板上に第1半導体素子を含むデバイス層を形成し、
前記第1基板を前記第2基板から剥離することを具備した半導体装置の製造方法。 - 前記第1基板を前記第2基板に接合する前に、該第1基板を前記第2基板に接合する第1分離可能層を、前記第2基板上に設けることをさらに具備する、請求項1に記載の半導体装置の製造方法。
- 前記第1基板は、シリコン単結晶であり、
前記第2基板は、SiC、AlN、SiNまたはAl2O3の単結晶、多結晶、あるいは、これらの材料の混合である、請求項1または請求項2に記載の半導体装置の製造方法。 - 前記第1分離可能層は、ポーラス構造を有するシリコンまたはシリコン酸化膜である、請求項2に記載の半導体装置の製造方法。
- 前記第1半導体素子は、メモリセルアレイを含む、請求項1から請求項4のいずれか一項に記載の半導体装置の製造方法。
- 第3基板上に第2半導体素子を形成し、
該第2半導体素子を前記第1半導体素子に接続するように、前記第3基板を前記第1基板に接合し、
前記第1および第3基板を前記第2基板から剥離することをさらに具備する、請求項1から請求項5のいずれか一項に記載の半導体装置の製造方法。 - 前記第3基板を前記第1基板に接合した後、
前記第3基板を薄膜化し、
第4基板を前記第3基板に接合し、
前記第1、第3および第4基板を前記第2基板から剥離し、
前記第1および第3基板を前記第4基板からさらに剥離することをさらに具備する、請請求項6に記載の半導体装置の製造方法。 - 前記第2半導体素子は、CMOS(Complementary Metal-Oxide-Semiconductor)を含む、請求項6または請求項7に記載の半導体装置の製造方法。
- 第1弾性率を有する第1基板を、前記第1弾性率よりも高い第2弾性率を有する第2基板上に接合し、
前記第1基板上に第1半導体素子を形成し、
第3基板上に第2半導体素子を形成し、
該第2半導体素子を前記第1半導体素子に接続するように、前記第3基板を前記第1基板に接合し、
前記第3基板を薄膜化し、
第4基板を前記第3基板に接合し、
前記第1、第3および第4基板を前記第2基板から剥離し、
前記第1および第3基板を前記第4基板からさらに剥離することを具備する、半導体装置の製造方法。
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