TWI754993B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TWI754993B
TWI754993B TW109124046A TW109124046A TWI754993B TW I754993 B TWI754993 B TW I754993B TW 109124046 A TW109124046 A TW 109124046A TW 109124046 A TW109124046 A TW 109124046A TW I754993 B TWI754993 B TW I754993B
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substrate
manufacturing
semiconductor device
layer
board
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TW109124046A
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TW202111876A (zh
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松尾美恵
宮島秀史
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日商鎧俠股份有限公司
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Abstract

本實施方式之半導體裝置之製造方法係將具有第1彈性模數之第1基板接合於第2基板上，該第2基板具有較第1彈性模數高之第2彈性模數。於第1基板上形成第1半導體元件。自第2基板剝離第1基板。

Description

半導體裝置之製造方法
本發明之實施方式係關於一種半導體裝置之製造方法。
開發了將複數個記憶胞三維配置而成之立體型記憶胞陣列。為了增大資料儲存容量，會增加此種記憶胞陣列之積層數。若記憶胞陣列之積層數增加，就會存在基板因積層膜之應力而翹曲之情況。若基板翹曲，就會引起製程中之搬送錯誤、基板破損、良率降低、元件特性劣化等問題。
本實施方式之半導體裝置之製造方法係將具有第1彈性模數之第1基板接合於第2基板上，該第2基板具有高於第1彈性模數之第2彈性模數。於第1基板上形成第1半導體元件。自第2基板剝離第1基板。 根據上述構成，能夠提供一種可抑制基板翹曲之半導體裝置。
現在將參考附圖解釋實施例。本發明不限於實施例。於實施例中，“上方向”或“下方向”有時與基於重力加速度方向之上方向或下方向不同。於本說明書和附圖中，與前述附圖中描述之元件相同之元件由相同之附圖標記表示，並且於適當時省略其詳細解釋。
(第1實施方式) 圖1(A)～圖2(C)係表示第1實施方式之半導體記憶體之製造方法之剖視圖。本實施方式係具備將複數個記憶胞三維配置而成之立體型記憶胞陣列及控制該記憶胞陣列之CMOS(Complementary Metal-Oxide-Semiconductor，互補金氧半導體)電路之NAND(Not And，與非)型快閃記憶體之製造方法。記憶胞陣列及CMOS電路於相對於基板10之表面大致垂直之方向積層。再者，本實施方式並不限定於NAND型快閃記憶體，只要為將半導體元件積層形成之半導體裝置則能夠適用。
首先，如圖1(A)所示，於基板20之表面上形成可分離層(第1可分離層)30。其次，如圖1(B)所示，於可分離層30上貼附基板10。將基板10之第1面F11朝向基板20及可分離層30貼附。基板10例如為包含矽單晶等之半導體基板。基板20使用彈性模數較基板10高且較硬之材料。即，若基板10具有第1彈性模數，則基板20具有高於第1彈性模數之第2彈性模數。再者，於本說明書中，所謂彈性模數，係指由楊氏模數表示之彎曲彈性。例如，若使基板10為矽單晶，則基板20亦可為SiC、AlN、SiN或Al2 O3 之單晶(藍寶石)、多晶、或者該等材料之混合(複合體或積層體)。 於基板10為矽單晶之情形時，基板10之彈性模數例如約為190 GPa。另一方面，基板20之彈性模數較佳為約200 GPa以上。例如，於基板20為SiC之情形時，基板20之彈性模數例如約為390 GPa。於基板20為AlN之情形時，基板20之彈性模數例如約為320 GPa。於基板20為SiN之情形時，基板20之彈性模數例如約為290 GPa。於基板20為Al2 O3 之單晶(藍寶石)之情形時，基板20之彈性模數例如約為470 GPa。 又，基板20之厚度較佳為較基板10之厚度厚。由此，基板20能夠支持、加強基板10。 可分離層30例如使用像多孔矽膜、氧化矽膜等能夠將基板10、20接合且密度較基板10、20低之較弱(較脆)之材料。例如，於可分離層30為多孔矽膜之情形時，可分離層30之多孔度較佳為20%～80%，以能夠將基板10、20接著且能夠相對較容易地分離。由此，可分離層30於之後之步驟中，能夠將基板10、20分離，而不會損傷基板10、20。可分離層30之表面藉由CMP(Chemical Mechanical Polishing，化學機械拋光)來平坦化，以能夠將基板10與20之間接合。
其次，如圖1(C)所示，使用研削法(Back Side Grinding，背面研磨)或CMP(Chemical Mechanical Polishing)法對處於與第1面F11相反側之基板10之第2面F12進行研磨，進而，使用濕式蝕刻法，對基板10之第2面F12進行蝕刻。由此，使基板10薄膜化。
其次，如圖2(A)所示，於基板10之第2面F12上，形成作為第1半導體元件之記憶胞陣列11。記憶胞陣列11可以為將複數個記憶胞三維配置而成之立體型記憶胞陣列。
此處，對記憶胞陣列11之構成詳細地進行說明。
圖3係表示記憶胞陣列11之一部分及其周邊之結構之剖視圖。圖4係記憶胞陣列11之柱狀部CL部分之放大剖視圖。再者，圖3表示了記憶胞陣列11之階梯結構部21。
如圖3所示，於基板10上形成有包含複數個記憶胞之記憶胞陣列11。記憶胞陣列11包含於Z方向(相對於第2面F12垂直之方向)交替地積層之複數個導電層(圖4之WL)與複數個絕緣層(圖4之51)。如圖4所示，複數個導電層作為複數條字元線WL而設置。複數個絕緣層51設置於在Z方向相鄰之複數條字元線WL間，且將上述複數條字元線WL間電性地絕緣。各字元線WL經由接觸插塞22而與字元線配線層23電性地連接。字元線WL例如包含鎢等導電性材料。絕緣層51例如包含氧化矽膜等絕緣材料。
於字元線WL及絕緣層51之積層體上，設置有選擇閘極SG。選擇閘極SG經由接觸插塞26而與選擇閘極配線層27電性地連接。選擇閘極SG亦包含例如鎢等導電性材料。於選擇閘極SG上，設置有層間絕緣膜15。進而，於層間絕緣膜15內或者層間絕緣膜15之上，形成有配線層24、接觸插塞25及金屬焊墊28。於最上層之金屬焊墊28間，設置有層間絕緣膜16。
又，柱狀部CL貫通字元線WL及選擇閘極SG，與位元線BL電性地連接。如圖4所示，柱狀部CL具備於Z方向延伸之記憶體絕緣膜57、通道半導體層55、及芯絕緣膜56。記憶體絕緣膜57包含阻擋絕緣膜52、電荷儲存層53及隧道絕緣膜54。電荷儲存層53例如包含氮化矽膜等絕緣材料，且介隔阻擋絕緣膜52形成於積層體58之側面。通道半導體層55例如包含多晶矽，且介隔隧道絕緣膜54形成於電荷儲存層53之側面。阻擋絕緣膜52、隧道絕緣膜54、及芯絕緣膜56例如包含氧化矽膜或金屬絕緣膜等絕緣材料。電荷儲存層53只要能夠儲存電荷則亦可為絕緣膜以外之層。
藉由使選擇閘極SG為導通狀態，來將柱狀部CL選擇性地連接於位元線BL，接收來自位元線BL之電壓。於該選擇之柱狀部CL中，電荷於通道半導體層55與電荷儲存層53之間經由隧道絕緣膜54注入/放出。由此，將資料寫入或刪除。阻擋絕緣膜52係為了阻擋電荷儲存層53之電荷向字元線WL洩漏而設置。字元線WL與記憶體絕緣膜57之交叉位置之構成成為記憶胞。具有此種構成及功能之記憶胞陣列11形成於基板10上。
如此，將基板20用作支持基板，於基板20上使基板10薄膜化，於該基板10上形成記憶胞陣列11。由此，即便將如記憶胞陣列11般之使複數種材料積層多層而成之積層體形成於薄膜化之基板10上，亦由於基板10由基板20支持故而幾乎不會翹曲，由基板20之表面支持而維持大致平坦狀態。
再次參照圖2，其次，如圖2(B)所示，將作為具有作為第2半導體元件之CMOS電路50之第3基板之基板40接合(貼合)於基板10之第2面F12上。基板40已經被薄膜化，於基板40之第3面F41上形成CMOS電路50。此時，以將CMOS電路50連接於記憶胞陣列11之方式，將CMOS電路50朝向第2面F12向基板10接合。CMOS電路50例如為構成記憶胞陣列11之控制器之CMOS電路(邏輯電路)。
圖5係表示CMOS電路50之一部分及其周邊之結構之剖視圖。於基板40之第3面F41上，設置有複數個電晶體31。各電晶體31具備介隔閘極絕緣膜設置於基板40之第3面F41上之閘極電極32、以及設置於基板40內之未圖示之源極擴散層及汲極擴散層。複數個電晶體31構成CMOS電路50，以控制記憶胞陣列11之方式發揮功能。
進而，複數個插塞33設置於電晶體31之源極擴散層或汲極擴散層上，多層配線結構35設置於插塞33上。進而，接觸插塞36設置於多層配線結構35上，金屬焊墊37設置於接觸插塞36上。金屬焊墊37例如包含銅、鎢等導電性材料。具有此種構成之CMOS電路50形成於基板40之第3面F41上。
如圖2(B)所示，若將具有CMOS電路50之基板40接合於具有記憶胞陣列11之基板10上，則如圖6所示，記憶胞陣列11及CMOS電路50積層於基板10與基板40之間。
圖6係表示將圖5所示之基板40接合於圖3所示之基板10之情況之剖視圖。若使基板40反轉將第3面F41朝向基板10之第2面F12接合，則設置於基板10上之金屬焊墊28與設置於基板40上之金屬焊墊37相互電性地連接。藉由將CMOS電路50與記憶胞陣列11電性地連接，能夠控制記憶胞陣列11。如此，於使CMOS電路50及記憶胞陣列11對向時，金屬焊墊28與金屬焊墊37以相互對應之方式配置。
再次參照圖2。於將基板10與基板40接合之後，如圖2(C)所示，自基板20剝離基板10。如上所述，由於可分離層30係較基板10、20脆之材料，故而能夠不損傷基板10、20，而自基板20剝離基板10。
其次，亦可對基板10或基板40進行加工而形成配線等。例如，圖7係表示背閘極電極形成後之半導體記憶體之構成之剖視圖。於圖7中，對基板10進行研磨，於記憶胞陣列11上，形成半導體層61、背閘極絕緣膜62、背閘極電極63、及保護膜64。半導體層61例如包含多晶矽等。背閘極絕緣膜62例如包含氧化矽膜。背閘極電極63例如包含導電性金屬。保護膜64例如包含聚醯亞胺等絕緣膜。半導體層61由背閘極絕緣膜62與背閘極電極63而覆蓋。半導體層61、背閘極絕緣膜62及背閘極電極63構成MOSFET(MOS Field Effect Transistor，MOS場效應電晶體)。背閘極電極63接收來自配線層24之電壓而於半導體層61形成通道，將複數個柱狀部CL之一端電性地連接於源極線(未圖示)。
於圖2(C)中，將基板10剝離之後，可將基板20洗淨並再利用。即，將使用過之可分離層30去除之後，將新的可分離層30形成於基板20，重複圖1(A)～圖2(C)之步驟。由此，能夠將基板20不浪費地重複利用，如此有助於降低製造成本。
經過以上之步驟，完成本實施方式之半導體記憶體。再者，上述實施方式之構成只不過為一例，本實施方式能夠應用於其他積層型半導體裝置。
根據本實施方式，將基板10以能夠剝離之方式由可分離層30接合於彈性模數較其為高之基板20上。而且，於基板20上將基板10薄膜化之後，將半導體元件形成於基板10。基板20由彈性模數相對較高且剛性較高(較硬)之材料構成。因此，基板20例如於如立體型記憶胞陣列般之積層體之製程中不太會翹曲，維持大致平坦狀態。由此，即便於經薄膜化之基板10形成具有多層膜之積層體，基板10亦接合於基板20並受其支持，故而幾乎不翹曲而維持大致平坦狀態。例如，立體型記憶胞陣列具有將複數條字元線WL與複數個絕緣層51交替地積層而成之積層體，會對基板10施加應力。然而，由於基板10受彈性模數較高之基板20支持，故而幾乎不翹曲，順著基板20之表面維持大致平坦狀態。其結果，能夠抑制基板10於製程中之加工錯誤、搬送錯誤、破損等。
又，半導體記憶體完成之後，可於不施加熱負載之狀態下，自基板20剝離基板10。因此，亦可抑制半導體記憶體完成後之基板10之翹曲。
(第2實施方式) 圖8(A)～圖8(C)係表示第2實施方式之半導體記憶體之製造方法之剖視圖。於第2實施方式中，作為第3基板之基板40於接合於基板10之後被薄膜化。再者，圖8(A)～圖8(C)表示了接著圖1(A)～圖2(A)之後之半導體記憶體之製造方法。
於經過圖1(A)～圖2(A)所示之步驟之後，如圖8(A)所示，將具有CMOS電路50之基板40接合(貼合)於基板10之第2面F12上。此時，以將CMOS電路50連接於記憶胞陣列11之方式，將基板40之第3面F41(設置有CMOS電路50之面)朝向第2面F12向基板10接合。
其次，如圖8(B)所示，使用研削法(Back Side Grinding)或CMP法對處於與第3面F41相反側之基板40之第4面F42進行研磨。由此，將基板40薄膜化。圖8(B)成為與圖2(B)實質上相同之構成。
其次，如圖2(C)所示，自基板20剝離基板10。如上所述，由於可分離層30係較基板10、20脆之材料，故而能夠不損傷基板10、20地，自基板20剝離將基板10。然後，對基板10或基板40進行加工而形成配線等。由此，與第1實施方式相同之半導體記憶體完成。第2實施方式能夠獲得與第1實施方式相同之效果。
(第3實施方式) 圖9(A)～圖9(C)係表示第3實施方式之半導體記憶體之製造方法之剖視圖。於第3實施方式中，作為第3基板之基板40於自基板10剝離之後被薄膜化。再者，圖9(A)～圖9(C)表示了接著圖1(A)～圖2(A)之後之半導體記憶體之製造方法。
經過圖1(A)～圖2(A)所示之步驟之後，如圖9(A)所示，將具有CMOS電路50之基板40接合(貼合)於基板10之第2面F12上。此時，以將CMOS電路50連接於記憶胞陣列11之方式，將基板40之第3面F41(設置有CMOS電路50之面)朝向第2面F12向基板10接合。
其次，如圖9(B)所示，自基板20剝離基板10。如上所述，由於可分離層30係較基板10、20脆之材料，故而能夠不損傷基板10、20地，自基板20剝離基板10。
其次，如圖9(C)所示，使用CMP法對處於與第3面F41相反側之基板40之第4面F42進行研磨。此時，第3面F41側之半導體元件由樹脂帶等保護。由此，將基板40薄膜化。然後，對基板10或基板40進行加工而形成配線等，與第1實施方式相同之半導體記憶體完成。
於第3實施方式中，基板40於自基板20剝離之後被薄膜化。然而，由於此時立體型記憶胞陣列等之積層體已經完成，然後不施加熱負載，故而即便於第3實施方式中，基板10、40亦不那麼翹曲，能夠獲得與第1實施方式相同之效果。又，於基板40之薄膜化之前，自基板20剝離基板10。因此，於自基板20剝離時，相對較厚之基板40支持基板10，能夠抑制基板10之裂痕等。
(第4實施方式) 圖10(A)～圖10(C)係表示第4實施方式之半導體記憶體之製造方法之剖視圖。於第4實施方式中，於基板40之研磨後，進而將作為第4基板之基板70接合於基板40，自基板20一起剝離基板10、40與基板70。再者，圖10(A)～圖10(C)表示了接著圖8(B)之後之半導體記憶體之製造方法。
經過圖1(A)～圖2(A)及圖8(A)～圖8(B)所示之步驟之後，如圖10(A)所示，將形成有可分離層80之基板70接合(貼合)於基板40之第4面F42上。基板70可以為與基板20相同之材料。可分離層80設置於基板70之第5面F71。基板70將第5面F71朝向基板40而接合。可分離層80較佳為與可分離層30相同之材料或者較可分離層30硬之材料。例如，於可分離層30、80均為多孔矽之情形時，較佳為可分離層80中所含之孔隙少於可分離層30中所含之孔隙。由此，於圖10(B)所示之步驟中，能夠保持使基板70接合於基板40之狀態，自基板20剝離基板10。
其次，如圖10(B)所示，自基板20剝離基板10、40、70。如上所述，可分離層80係較基板10、20、40、70脆(弱)但較可分離層30硬之材料。因此，能夠不損傷基板10、20、40、70地，自基板20剝離基板10。
其次，如圖10(C)所示，自基板40剝離基板70。可分離層80係較基板10、20、40、70脆之材料。因此，能夠不損傷基板10、40、70地，自基板20剝離基板70。然後，對基板10或基板40進行加工而形成配線等，與第1實施方式相同之半導體記憶體完成。於第4實施方式中，基板10、40亦不那麼翹曲，能夠獲得與第1實施方式相同之效果。
再者，基板20、70可洗淨並再利用。即，於將已經使用之可分離層30、80去除之後，將新之可分離層30、80形成於基板20、70，重複第4實施方式之步驟。由此，能夠將基板20、70不浪費地重複利用。
儘管已經描述了某些實施例，但是該等實施例僅係藉由示例之方式給出，並且不意圖限制本發明之範圍。實際上，本文描述之新穎之方法和系統能夠以多種其他形式來體現；再者，於不背離本發明之精神之情形時，可以對本文所述之方法和系統之形式進行各種省略、替代和改變。所附申請專利範圍及其等同物旨在覆蓋該等形式或修改，其等屬於本發明之範圍和精神內。相關申請案之引用
本申請案基於並主張2019年9月11日申請之先行日本專利申請案第2019-165648號之優先權之利益，該申請案之所有內容藉由引用包含於本文中。
10:基板 11:記憶胞陣列 15:層間絕緣膜 16:層間絕緣膜 20:基板 21:階梯結構部 22:接觸插塞 23:字元線配線層 24:配線層 25:接觸插塞 26:接觸插塞 27:選擇閘極配線層 28:金屬焊墊 30:可分離層 31:電晶體 32:閘極電極 33:插塞 35:多層配線結構 36:接觸插塞 37:金屬焊墊 40:基板 50:CMOS電路 51:絕緣層 52:阻擋絕緣膜 53:電荷儲存層 54:隧道絕緣膜 55:通道半導體層 56:芯絕緣膜 57:記憶體絕緣膜 58:積層體 61:半導體層 62:背閘極絕緣膜 63:背閘極電極 64:保護膜 70:基板 80:可分離層 BL:位元線 CL:柱狀部 F11:第1面 F12:第2面 F41:第3面 F42:第4面 F71:第5面 SG:選擇閘極 WL:字元線
圖1A～C係表示第1實施方式之半導體記憶體之製造方法之剖視圖。 圖2A～C係接著圖1表示半導體記憶體之製造方法之剖視圖。 圖3係表示記憶胞陣列之一部分及其周邊之結構之剖視圖。
圖4係記憶胞陣列之柱狀部部分之放大剖視圖。 圖5係表示CMOS(complementary metal oxide semiconductor，互補金屬氧化物半導體)電路之一部分及其周邊之結構之剖視圖。 圖6係表示將圖5所示之基板接合於圖3所示之基板之情況之剖視圖。 圖7係表示背閘極電極形成後之半導體記憶體之構成之剖視圖。
圖8A～C係表示第2實施方式之半導體記憶體之製造方法之剖視圖。 圖9A～C係表示第3實施方式之半導體記憶體之製造方法之剖視圖。 圖10A～C係表示第4實施方式之半導體記憶體之製造方法之剖視圖。
10:基板
20:基板
30:可分離層
F11:第1面
F12:第2面

Claims (15)

  1. 一種半導體裝置之製造方法，其具備：將具有第1彈性模數之第1基板(10)接合於第2基板(20)上，上述第2基板(20)具有較上述第1彈性模數高之第2彈性模數；於上述第1基板上形成第1半導體元件；將上述第1基板自上述第2基板剝離；於第3基板上形成第2半導體元件；以將該第2半導體元件連接於上述第1半導體元件之方式，將上述第3基板接合於上述第1基板；及自上述第2基板剝離上述第1及第3基板。
  2. 如請求項1之半導體裝置之製造方法，其進而具備：將上述第1基板接合於上述第2基板之後，將上述第1基板薄膜化。
  3. 如請求項1之半導體裝置之製造方法，其進而具備：於將上述第1基板接合於上述第2基板之前，於上述第2基板上設置第1可分離層(30)，上述第1可分離層(30)將該第1基板接合於上述第2基板。
  4. 如請求項2之半導體裝置之製造方法，其進而具備：於將上述第1基板接合於上述第2基板之前，於上述第2基板上設置第1可分離層(30)，上述第1可分離層(30)將該第1基板接合於上述第2基板。
  5. 如請求項1之半導體裝置之製造方法，其中上述第1基板為矽單晶，上述第2基板為SiC、AlN、SiN或Al2O3之單晶、多晶、或者該等材料之混合。
  6. 如請求項2之半導體裝置之製造方法，其中上述第1基板為矽單晶，上述第2基板為SiC、AlN、SiN或Al2O3之單晶、多晶、或者該等材料之混合。
  7. 如請求項3之半導體裝置之製造方法，其中上述第1基板為矽單晶，上述第2基板為SiC、AlN、SiN或Al2O3之單晶、多晶、或者該等材料之混合。
  8. 如請求項3之半導體裝置之製造方法，其中上述第1可分離層為具有多孔結構之矽或氧化矽膜。
  9. 如請求項1之半導體裝置之製造方法，其中上述第1半導體元件包含CMOS及形成於該CMOS上之記憶胞陣列。
  10. 如請求項1之半導體裝置之製造方法，其進而具備：於將上述第3基板接合於上述第1基板之後，且自上述第2基板剝離之前，對上述第3基板進行研磨。
  11. 如請求項1之半導體裝置之製造方法，其進而具備：自上述第2基板剝離之後，對上述第3基板進行研磨。
  12. 如請求項1之半導體裝置之製造方法，其進而具備：將上述第3基板接合於上述第1基板之後，將上述第3基板薄膜化，將第4基板(70)接合於上述第3基板，自上述第2基板剝離上述第1、第3及第4基板，及進而自上述第4基板剝離上述第1及第3基板。
  13. 如請求項1之半導體裝置之製造方法，其中上述第1半導體元件為記憶胞陣列，上述第2半導體元件為CMOS。
  14. 如請求項12之半導體裝置之製造方法，其中將上述第4基板(70)與上述第3基板之間接合之第2可分離層(80)為多孔矽或氧化矽膜。
  15. 如請求項14之半導體裝置之製造方法，其中上述第2可分離層(80)為孔隙較上述第1可分離層少之多孔矽。
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