TWI832156B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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TWI832156B
TWI832156B TW111105248A TW111105248A TWI832156B TW I832156 B TWI832156 B TW I832156B TW 111105248 A TW111105248 A TW 111105248A TW 111105248 A TW111105248 A TW 111105248A TW I832156 B TWI832156 B TW I832156B
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Taiwan
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wafer
film
protective film
oxide film
semiconductor device
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TW111105248A
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TW202314832A (zh
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豊田現
本郷悟史
右田達夫
山本進
藤田努
秦栄一
片村幸雄
松重英希
高橋一橋
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日商鎧俠股份有限公司
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Abstract

本發明係一種半導體裝置，其具備包含配線層之基底基板B、及設置於基底基板B上之晶片C1、C2、C3、C4、C5、C6，且於晶片C1、C2、C3、C4、C5、C6之側面設置有保護膜P。

Description

半導體裝置及半導體裝置之製造方法
本發明係關於一種半導體裝置及半導體裝置之製造方法。
作為半導體裝置及半導體裝置之製造方法之一例，已知有一種積層元件晶片及積層元件晶片之製造方法。
一實施方式抑制半導體裝置之製造步驟中之局部研磨。
本發明之實施方式係一種半導體裝置，其具備包含配線層之基底基板、及設置於基底基板上之晶片，且於晶片之側面設置有保護膜。
本發明之實施方式係一種半導體裝置之製造方法，其準備包含配線層之基底基板，於基底基板上接合包含電極之晶片，於晶片形成保護膜，對晶片進行電極露頭加工。
根據上述構成，可抑制半導體裝置之製造步驟中之局部研磨。
以下，參照隨附圖式對本實施方式進行說明。為了容易理解說明，於各圖式中對相同之構成要素儘量標註相同之符號，並省略重複之說明。
圖1係用以說明第1實施方式中之半導體記憶裝置E之構造之剖視圖。半導體記憶裝置E包含基底基板B及晶片C1、C2、C3、C4、C5、C6。於基底基板B上接合有晶片C1。基底基板B中，於與接合有晶片C1之面為相反側之面接合有複數個金屬球BE。
晶片C1中，於與接合於基底基板B之面為相反側之面接合有晶片C2。晶片C2中，於與接合於晶片C1之面為相反側之面接合有晶片C3。晶片C3中，於與接合於晶片C2之面為相反側之面接合有晶片C4。晶片C4中，於與接合於晶片C3之面為相反側之面接合有晶片C5。晶片C5中，於與接合於晶片C4之面為相反側之面接合有晶片C6。如此，於基底基板B上積層有晶片C1、C2、C3、C4、C5、C6。
以覆蓋晶片C1、C2、C3、C4、C5、C6之側面之方式設置有保護膜P。保護膜P亦覆蓋基底基板B之至少一部分。本實施方式中，作為一例，保護膜P以於晶片C1側相對性地變厚，而於晶片C6側相對性地變薄之方式設置。保護膜P之厚度並不限定於此，亦可按照成為均勻之方式設置。保護膜P亦可按照於晶片C6側相對性地變厚，而於晶片C1側相對性地變薄之方式設置。保護膜P亦可被去除。以覆蓋保護膜P之方式設置有塑模樹脂層M。
繼而，參照圖2至圖11，對半導體記憶裝置E之製造方法進行說明。圖2至圖11成為製造2個半導體記憶裝置E之圖，但可同時製造3個以上之多數之半導體記憶裝置E。
如圖2所示，準備於支持基板SB上貼合基底基板B而成者。此外，亦可藉由於支持基板SB上形成配線層來形成為基底基板B。於基底基板B上之特定之位置接合(bonding)特定數量之經單片化之晶片C1。於各晶片C1中矽C1a成為較厚之狀態。自晶片C1延伸之貫通電極(TSV：Through-Silicon Via，矽通孔)T1成為嵌入至矽C1a內之狀態。
繼而，如圖3所示，以覆蓋晶片C1、矽C1a、及基底基板B之方式形成保護膜P1。保護膜P1係機械性強度較高之膜，例如，使用氧化矽、氮化矽、碳化矽、氮化硼之類之膜。另外，例如亦可使用DLC(Diamond-like carbon，類鑽碳)等各種無機絕緣膜。
繼而，如圖4所示，利用背面研磨機來研磨矽C1a。利用背面研磨機研磨後之矽C1a之表面粗糙度為較粗之狀態。
繼而，如圖5所示，利用CMP(Chemical Mechanical Polishing，化學機械拋光)來將矽C1a薄膜化。利用CMP去除結晶缺陷並改善表面粗糙度。保護膜P1不易利用CMP去除，而矽C1a較多地被去除。
繼而，如圖6所示，對矽C1a進行乾式蝕刻，貫通電極T1露頭。繼而，如圖7所示，將成為貼合面之氧化膜C1b共形地成膜。氧化膜C1b例如使用氧化矽之類之膜。
繼而，如圖8所示，利用CMP以貼合面成為平面之方式將保護膜P1、氧化膜C1b、貫通電極T1薄化。 此時，將形成於晶片C1之側面之氧化膜C1b設為第1氧化膜，將形成於晶片C1之背面之氧化膜C1b設為第2氧化膜。第2氧化膜之晶片C1之周緣部之厚度較第2氧化膜之晶片C1之中央部側之厚度薄。晶片C1之側面之保護膜P1之上端部處於第1氧化膜與第2氧化膜之間，進而，保護膜P1之上端部自第1氧化膜與第2氧化膜露出。
繼而，如圖9所示，於晶片C1之貼合面接合下一個晶片C2。 對晶片C2之處理與晶片C1相同。即，於晶片C2製膜保護膜P2。該保護膜P2亦形成於晶片C2之背面與側面、及晶片C1之側面。當於晶片C1之側面殘留保護膜P1或氧化膜C1b時，則形成於該膜之上。然後，自背面使晶片C2薄化，使貫通電極露頭。 然後，將成為貼合面之氧化膜C2b成膜於晶片C2之背面。氧化膜C2b亦形成於晶片C2之側面與晶片C1之側面。此時，氧化膜C2b亦可形成於保護膜P2之上。 然後，利用CMP以使保護膜、氧化膜、貫通電極成為平坦面之方式薄化。以後，重複參照圖3至圖8所說明之順序，將晶片C3、C4、C5、C6堆積而形成晶片積層體。如圖10所示，由於每次積層晶片時都形成保護膜，故而積層晶片C6時之保護膜P於晶片C1之側面較於晶片C6之側面厚。
圖11表示將圖10之XI部放大之圖。如圖11所示，依次積層保護膜P1、氧化膜C1b、保護膜P2、氧化膜C2b、保護膜P3、氧化膜C3b、保護膜P4、氧化膜C4b、保護膜P5、氧化膜C5b、保護膜P6、氧化膜C6b。保護膜P1及氧化膜C1b如上所述係於設置晶片C1時積層之積層膜。保護膜P2及氧化膜C2b係於晶片C1上設置晶片C2時積層之積層膜。保護膜P3及氧化膜C3b係於晶片C2上設置晶片C3時積層之積層膜。保護膜P4及氧化膜C4b係於晶片C3上設置晶片C4時積層之積層膜。保護膜P5及氧化膜C5b係於晶片C4上設置晶片C5時積層之積層膜。保護膜P6及氧化膜C6b係於晶片C5上設置晶片C6時積層之積層膜。
於晶片C1之側面中，如圖11所示，將保護膜及氧化膜積層而成之積層膜設置6層。於基底基板B之上亦同樣地，將保護膜及氧化膜積層而成之積層膜設置6層。
於晶片C2之側面，未形成保護膜P1及氧化膜C1b，係自保護膜P2及氧化膜C2b起積層，故而將保護膜及氧化膜積層而成之積層膜設置5層。於晶片C3之側面，除了未形成保護膜P1及氧化膜C1b以外還未形成保護膜P2及氧化膜C2b，係自保護膜P3及氧化膜C3b起積層，故而將保護膜及氧化膜積層而成之積層膜設置4層。
於晶片C4之側面，未形成保護膜P1、P2、P3及氧化膜C1b、C2b、C3b，係自保護膜P4及氧化膜C4b起積層，故而將保護膜及氧化膜積層而成之積層膜設置3層。於晶片C5之側面，未形成保護膜P1、P2、P3、P4及氧化膜C1b、C2b、C3b、C4b，係自保護膜P5及氧化膜C5b起積層，故而將保護膜及氧化膜積層而成之積層膜設置2層。於晶片C6之側面，未形成保護膜P1、P2、P3、P4、P5及氧化膜C1b、C2b、C3b、C4b、C5b，積層有保護膜P6及氧化膜C6b，故而將保護膜及氧化膜積層而成之積層膜設置1層。
此時，由於在最上層之晶片C6中沒有連接貫通電極T1者，故而亦有時無須使晶片C6薄化。於該情形時，於晶片C6之側面中未設置積層膜。因此，未形成圖11所示之保護膜P6及氧化膜C6b。於晶片C1之側面中，保護膜與氧化膜之積層膜設置5層。於該情形時，於基底基板B上保護膜與氧化膜之積層膜設置5層。
繼而，如圖12所示，形成塑模樹脂層M。然後，藉由將支持基板SB去除並單片化，而成為圖1所示之半導體記憶裝置E。保護膜P自塑模樹脂M之側面露出一部分。露出之保護膜P係沿著與基底基板B之表面垂直之方向，將氮化矽與氧化矽交替地重複複數次而成之積層膜。重複之次數與所積層之晶片之數量相等或者亦可較其少一次。亦可於形成塑模樹脂層M之前去除基底基板B之上之保護膜P。此時，保護膜P未自塑模樹脂層M之側面露出。
繼而，參照圖13對晶片C1進行進一步說明。圖13係晶片C1之剖視圖，係參照圖2所說明之狀態之剖視圖。如圖13所示，晶片C1為陣列晶片1與電路晶片2貼合而成之三維記憶體。陣列晶片1具備記憶胞陣列11、絕緣膜12、基板13、及絕緣膜14。記憶胞陣列11包含複數個記憶胞。絕緣膜12設置於記憶胞陣列11下。基板13設置於絕緣膜12下。絕緣膜14設置於基板13下。
陣列晶片1進而具備層間絕緣膜15及絕緣膜16。層間絕緣膜15設置於記憶胞陣列11上。絕緣膜16設置於層間絕緣膜15上。絕緣膜12、14、16例如為氧化矽膜或氮化矽膜。基板13例如為矽基板等半導體基板。
電路晶片2設置於陣列晶片1上。符號S表示陣列晶片1與電路晶片2之貼合面。將陣列晶片1與電路晶片2分別形成之後相互貼合。電路晶片2具備絕緣膜17、層間絕緣膜18、及半導體19。層間絕緣膜18設置於絕緣膜17上。半導體19設置於層間絕緣膜18上。絕緣膜17例如為氧化矽膜或氮化矽膜。
圖13表示了與基板13之表面S1、S2、半導體19之表面S3、基板60之表面S4平行且相互垂直之X方向及Y方向，及與表面S1、S2、表面S3、S4垂直之Z方向。本說明書中，將+Z方向作為上方向處理，將-Z方向作為下方向處理。例如，記憶胞陣列11位於基板60之下方，且位於基板13之上方。-Z方向既可與重力方向一致，亦可不與重力方向一致。
陣列晶片1具備複數個字元線WL、背閘極BG、及選擇閘極SG，作為記憶胞陣列11內之電極層。圖13表示了記憶胞陣列11之階梯構造部21。陣列晶片1與電路晶片2相互接合。
如圖13所示，各字元線WL經由接觸插塞22而與字元線配線層23電性地連接。背閘極BG經由接觸插塞24而與背閘極配線層25電性地連接。選擇閘極SG經由接觸插塞26而與選擇閘極配線層27電性地連接。以貫通選擇閘極SG之方式設置有柱狀部CL。字元線WL、背閘極BG、及柱狀部CL經由插塞28而與位元線BL電性地連接，且與基板13電性地連接。
電路晶片2具備複數個電晶體31。各電晶體31具備閘極電極32、未圖示之源極擴散層、及未圖示之汲極擴散層。閘極電極32隔著未圖示之閘極絕緣膜而設置於半導體19上。源極擴散層及汲極擴散層設置於半導體19內。
電路晶片2進而具備插塞33、配線層34、及配線層35。複數個插塞33設置於各電晶體31之源極擴散層或汲極擴散層上。複數個配線層34設置於該等插塞33上，且包含複數個配線。複數個配線層35設置於該等配線層34上，且包含複數個配線。
電路晶片2進而具備介層插塞36、及金屬焊墊37。複數個介層插塞36設置於配線層35上。複數個金屬焊墊37於絕緣膜17內設置於該等介層插塞36上。
電路晶片2進而具備基板60及貫通電極61。基板60設置於半導體19之表面S4上。基板60例如為氧化矽膜或矽等半導體基板。貫通電極61設置於層間絕緣膜18、半導體19及基板60內，且設置於配線層34上。基板60相當於圖2等中之矽C1a。貫通電極61相當於圖2等中之貫通電極T1。貫通電極61例如於形成配線層34之前以嵌入至基板60之方式形成。電路晶片2包含控制陣列晶片1之CMOS(complementary metal oxide semiconductor，互補金屬氧化物半導體)控制電路(邏輯電路)。
陣列晶片1具備金屬焊墊41、介層插塞42、及配線層43。複數個金屬焊墊41於絕緣膜16內設置於金屬焊墊37上。複數個介層插塞42設置於金屬焊墊41上。複數個配線層43設置於該等介層插塞42上，且包含複數個配線。各字元線WL或各位元線BL與配線層43內之對應之配線電性地連接。
陣列晶片1進而具備插塞44、插塞46、及金屬焊墊47。插塞44設置於層間絕緣膜15或絕緣膜12內，且設置於配線層43上。插塞46介隔絕緣膜45而設置於基板13或絕緣膜14內，且設置於插塞44上。金屬焊墊47設置於絕緣膜14內，且設置於插塞46上。金屬焊墊47以與絕緣膜14之下表面成為同一面之方式設置。金屬焊墊47為晶片C1之外部連接焊墊。
圖14係表示將晶片C1藉由接合(bonding)而接合於基底基板B之狀態之剖視圖。基底基板B具備外部端子70、配線層71、插塞72、及金屬焊墊73。外部端子70於基底基板B下設置複數個。外部端子7係用以進行外部連接之金屬端子，發揮與參照圖1所說明之金屬球BE相同之作用。
配線層71設置於基底基板B內部，且包含複數個配線。插塞72設置於基底基板B內部，且設置於配線層71上。金屬焊墊73設置於插塞72上。金屬焊墊73設置於基底基板B內部，且以與基底基板B之上表面成為同一面之方式設置。
晶片C1之金屬焊墊47與基底基板B之金屬焊墊73，配置於對應之位置之焊墊彼此對向配置，且藉由接合(bonding)而接合。
亦可於基底基板內部設置控制器。圖15係將控制器74設置於內部之基底基板Ba之例。控制器74係控制晶片C1等之控制器。控制器74與金屬焊墊73利用插塞72連接。
圖16係表示於圖14所示之晶片C1進而利用接合(bonding)而接合有晶片C2之狀態之剖視圖。自圖14所示之狀態，利用參照圖3至圖9所說明之方法使晶片C1之貫通電極61露頭，將晶片C2置於晶片C1上。晶片C1之貫通電極61與晶片C2之金屬焊墊47，配置於對應之位置之焊墊彼此對向配置，藉由接合(bonding)而接合。晶片C2之朝向晶片C1側之面例如由氧化矽膜等絕緣膜形成，亦可與焊墊47形成為同一面。晶片C1之朝向晶片C2側之面例如由氧化矽膜等絕緣膜形成，亦可與貫通電極61形成為同一面。
如圖17所示，列舉配置有晶片C1之貫通電極61與晶片C2之金屬焊墊47之情況為例進行說明。於圖17中，表示了晶片C1之上表面與晶片C2之下表面。於圖17所例示之情形時，貫通電極61a與金屬焊墊47a對應，貫通電極61b與金屬焊墊47b對應。以該等對應之元件彼此對向配置之方式，將晶片C2置於晶片C1來進行接合。
於圖18中，對將晶片C1接合於基底基板B之情況進行說明。於圖18中，表示了基底基板B之上表面與晶片C1之下表面。於圖18所例示之情形時，金屬焊墊73a與金屬焊墊47a對應，金屬焊墊73b與金屬焊墊47b對應。以該等對應之焊墊彼此對向配置之方式，將晶片C1置於基底基板B來進行接合。
於圖18中，對金屬焊墊73沿著基底基板B之短邊直線地配置，金屬焊墊47亦沿著晶片C1之短邊直線地配置之例子進行了說明，但金屬焊墊73及金屬焊墊47之配置態樣並不限定於此。
如圖19所示，金屬焊墊亦可為無規則性之配置態樣。於圖19中，表示基底基板BD之上表面與晶片C1D之下表面。於圖19所例示之情形時，金屬焊墊73Da與金屬焊墊47Da對應，金屬焊墊73Db與金屬焊墊47Db對應。以該等對應之焊墊彼此對向配置之方式，將晶片C1D置於基底基板BD來進行接合。此外，如圖19所例示，亦可根據基底基板BD中之金屬焊墊之配置態樣來改變晶片C1中之金屬焊墊之配置態樣，亦可保持圖18所例示之晶片C1中之金屬焊墊之配置態樣進行再配線後對應。
圖20係用以說明使用參照圖15所說明之基底基板Ba之半導體記憶裝置E1之圖。如圖20所示，基底基板Ba於內部具備控制器74。於基底基板Ba之內部設置有配線層71。於基底基板Ba上，積層有晶片C。晶片C如參照圖13等所說明之晶片C1般並不限定於將記憶體基板與CMOS(Complementary Metal-oxide Semiconductor)接合之態樣，例如亦可僅由記憶體基板構成。於所積層之複數個晶片C之外周設置有保護膜P。於保護膜P之周圍設置有塑模樹脂層M。
圖21係用以說明第2實施方式中之半導體記憶裝置E2之構造之剖視圖。半導體記憶裝置E2包含基底基板B及複數個晶片C。於基底基板B上，晶片C由接著部81支撐並保持。基底基板B與晶片C利用連接電極82電性地連接。基底基板B中，於與接合有晶片C之面為相反側之面接合有複數個金屬球BE。
於複數個晶片C分別設置有貫通電極T。以覆蓋複數個晶片C之側面之方式設置有保護膜P。保護膜P亦可被去除。以覆蓋保護膜P之方式設置有塑模樹脂層M。
繼而，參照圖22至圖31，對半導體記憶裝置E2之製造方法進行說明。圖22至圖31對搭載2個晶片C之例子進行說明。
如圖22所示，準備支持基板SB。支持基板SB係於製造中途被去除之基板。
繼而，如圖23所示，於支持基板SB上利用接著劑等接合晶片C。於晶片C內部設置有貫通電極T。
繼而，如圖24所示，於接合於支持基板SB上之晶片C設置保護膜P，露頭後使貫通電極T露出，接合下一個晶片C。所接合之晶片C之貫通電極T相互接合。晶片C彼此之接合藉由接合(bonding)而進行。
繼而，如圖25所示，於配置於上方之晶片C設置保護膜P，露頭之後使貫通電極T露出。
繼而，如圖26所示，於配置於上方之晶片C連接控制晶片CT。控制晶片CT與配置於上方之晶片C之貫通電極T接合。
繼而，如圖27所示，準備基底基板B。基底基板B具備未圖示之配線層。基底基板B於上方具備金屬焊墊83。使圖26所示之支持基板SB及晶片C上下反轉，接著於基底基板B。接著係利用接著部81來進行。接著部81亦可係相對於基底基板B隔開特定間隔保持晶片C之支撐件。晶片C與基底基板B利用電極82電性地連接。電極82連接於貫通電極T及金屬焊墊83。
繼而，如圖28所示，去除支持基板SB。繼而，如圖29所示，以覆蓋基底基板B上之晶片C之方式填充塑模樹脂，形成塑模樹脂層M。
繼而，如圖30所示，於基底基板B之下方接合金屬球BE。金屬球BE接合於設置於基底基板B之下表面之金屬焊墊83。繼而，如圖31所示，藉由沿著切斷線L切斷，進行單片化而成為半導體記憶裝置E2。此時，保護膜P亦可自塑模樹脂層M之側面露出一部分。與圖1中之半導體裝置E不同，保護膜P自最遠離基底基板B之晶片C之端部附近露出。亦可於形成塑模樹脂層M之前去除保護膜P。於該情形時，保護膜P不自塑模樹脂層M露出。
上述實施方式之半導體裝置E、E1、E2具備包含配線層之基底基板B、Ba、及設置於基底基板B、Ba上之晶片C、C1、C2、C3、C4、C5、C6，且於晶片C、C1、C2、C3、C4、C5、C6之側面設置有保護膜P。於用以將單片化之晶片C、C1、C2、C3、C4、C5、C6薄化及形成接合電極之CMP步驟中，於晶片C、C1、C2、C3、C4、C5、C6側壁殘存氮化矽膜之類之保護膜P，藉此即便CMP加工壓力集中局部研磨亦不會進展，可抑制晶片C、C1、C2、C3、C4、C5、C6端變薄之塌邊(roll off)現象。藉此，可改善晶片C、C1、C2、C3、C4、C5、C6端之接合不良。
保護膜P包含氧化矽、氮化矽、碳化矽、氮化硼中之至少一種。保護膜P於基底基板B、Ba側之厚度與於晶片C、C1、C2、C3、C4、C5、C6上端側之厚度不同。
上述實施方式之半導體裝置E、E1之製造方法中，準備包含配線層之基底基板B、Ba，於基底基板B、Ba上接合包含電極之晶片C、C1、C2、C3、C4、C5、C6，於晶片C、C1、C2、C3、C4、C5、C6形成保護膜P，對晶片C、C1、C2、C3、C4、C5、C6進行電極露頭加工。於用以將單片化之晶片C、C1、C2、C3、C4、C5、C6薄化及形成接合電極之CMP步驟中，於晶片C、C1、C2、C3、C4、C5、C6側壁殘存氮化矽膜之類之保護膜P，藉此即便CMP加工壓力集中局部研磨亦不會進展，可抑制晶片C、C1、C2、C3、C4、C5、C6端變薄之塌邊現象。藉此，可改善晶片C、C1、C2、C3、C4、C5、C6端之接合不良。
上述實施方式之半導體裝置E2之製造方法中，準備支持基板SB，於支持基板SB上接著包含電極之晶片C，於晶片C形成保護膜P，對晶片C進行露頭加工，於接著於支持基板SB之相反側之晶片C接合包含配線層之基底基板B，去除支持基板SB。於用以將單片化之晶片C薄化及形成接合電極之CMP步驟中，於晶片C側壁殘存氮化矽膜之類之保護膜P，藉此即便CMP加工壓力集中局部研磨亦不會進展，可抑制晶片C端變薄之塌邊現象。藉此，可改善晶片C端之接合不良。
於上述各實施方式之製造方法中，可於晶片C、C1、C2、C3、C4、C5、C6形成保護膜P之後進行晶片C、C1、C2、C3、C4、C5、C6之薄化加工，對晶片C、C1、C2、C3、C4、C5、C6進行電極露頭加工。
於上述各實施方式之製造方法中，可使保護膜P之厚度為20 nm－3000 nm。於上述各實施方式之製造方法中，保護膜P包含氮化矽、碳化矽、氮化硼中之至少一種。保護膜P亦可為氮化矽、碳化矽、氮化硼中之至少一種與氧化矽之積層膜。(其他實施方式)
於保護膜P為積層膜時，例如亦可將氮化矽與氧化矽之積層構造重複複數次。於該情形時，重複之次數於C1、C2、C3、C4、C5、C6之側面亦可不同。
半導體裝置E及E1中，重複之次數於C1之側面最多，隨著自C2朝向C6，重複次數逐個減少一次。於半導體裝置E2中，重複之次數於最遠離基底基板B之晶片最多，隨著接近基底基板B，重複次數逐個減少一次。
於圖7中，氧化膜C1b形成於晶片C1之側面、背面、及基底基板B之上。然而，此時，亦可使氧化膜C1b僅形成於晶片C1之背面且矽C1a之上。此時，由於在晶片C1之側面及基底基板B之上未形成氧化膜C1b，故而保護膜P不具有如上所述之積層膜之重複構造，例如僅由氮化矽形成。然而，更詳細而言氮化矽形成有複數層。
圖28中，去除了支持基板SB，但亦可不去除支持基板SB。於該情形時，亦可於半導體裝置E2之上表面直接使用支持基板SB。或者，於連同支持基板SB一起嵌入至塑模樹脂層M之情形時，支持基板SB之剖面自塑模樹脂層M之側面露出。
以上，參照具體例對本實施方式進行了說明。然而，本發明並不限定於該等具體例。業者對該等具體例適當增加設計變更而成之內容只要具備本發明之特徵則亦包含於本發明之範圍中。上述各具體例所具備之各要素及其配置、條件、形狀等並不應限定於例示之內容，能夠適當變更。上述各具體例所具備之各要素只要不產生技術性之矛盾，則能夠適當改變組合。  [相關申請案之引用]
本申請案基於2021年09月22日提出申請之在先日本專利申請案第2021-154227號之優先權而主張優先權利益，藉由引用將其全部內容併入本文中。
1:陣列晶片 2:電路晶片 11:記憶胞陣列 12:絕緣膜 13:基板 14:絕緣膜 15:層間絕緣膜 16:絕緣膜 17:絕緣膜 18:層間絕緣膜 19:半導體 21:階梯構造部 22:接觸插塞 23:字元線配線層 24:接觸插塞 25:背閘極配線層 26:接觸插塞 27:選擇閘極配線層 28:插塞 31:電晶體 32:閘極電極 33:插塞 34:配線層 35:配線層 36:介層插塞 37:金屬焊墊 41:金屬焊墊 42:介層插塞 43:配線層 44:插塞 45:絕緣膜 46:插塞 47:金屬焊墊 47a:金屬焊墊 47b:金屬焊墊 47Da:金屬焊墊 47Db:金屬焊墊 60:基板 61:貫通電極 61a:貫通電極 61b:貫通電極 70:外部端子 71:配線層 72:插塞 73:金屬焊墊 73a:金屬焊墊 73b:金屬焊墊 73Da:金屬焊墊 73Db:金屬焊墊 74:控制器 81:接著部 82:連接電極 83:金屬焊墊 B:基底基板 Ba:基底基板 BE:金屬球 BG:背閘極 BL:位元線 C:晶片 C1,C2,C3,C4,C5,C6:晶片 C1a:矽 C1b:氧化膜 C1D:晶片 C2b:氧化膜 C3b:氧化膜 C4b:氧化膜 C5b:氧化膜 C6b:氧化膜 CL:柱狀部 CT:控制晶片 E:半導體記憶裝置 E1:半導體記憶裝置 M:塑模樹脂層 P:保護膜 P1:保護膜 P2:保護膜 P3:保護膜 P4:保護膜 P5:保護膜 P6:保護膜 S:貼合面 S1:表面 S2:表面 S3:表面 S4:表面 SB:支持基板 SG:選擇閘極 T:貫通電極 T1:貫通電極 WL:字元線
圖1係用以說明第1實施方式中之半導體記憶裝置之構成之圖。  圖2係用以說明圖1所示之半導體記憶裝置之製造方法之圖。  圖3係用以說明圖1所示之半導體記憶裝置之製造方法之圖。  圖4係用以說明圖1所示之半導體記憶裝置之製造方法之圖。  圖5係用以說明圖1所示之半導體記憶裝置之製造方法之圖。  圖6係用以說明圖1所示之半導體記憶裝置之製造方法之圖。  圖7係用以說明圖1所示之半導體記憶裝置之製造方法之圖。  圖8係用以說明圖1所示之半導體記憶裝置之製造方法之圖。  圖9係用以說明圖1所示之半導體記憶裝置之製造方法之圖。  圖10係用以說明圖1所示之半導體記憶裝置之製造方法之圖。  圖11係將圖10之XI部放大表示之圖。  圖12係用以說明圖1所示之半導體記憶裝置之製造方法之圖。  圖13係用以說明圖1所示之半導體記憶裝置中所包含之晶片之圖。  圖14係用以說明將圖13所示之晶片接合於基底基板之狀態之圖。  圖15係用以說明圖14所示之基底基板之變化例之圖。  圖16係用以說明於圖14所示之晶片進而接合晶片之狀態之圖。  圖17係用以說明於晶片接合晶片之狀態之圖。  圖18係用以說明於基板接合晶片之狀態之圖。  圖19係用以說明於基板接合晶片之狀態之圖。  圖20係用以說明變化例之半導體記憶裝置之構成之圖。  圖21係用以說明第2實施方式中之半導體記憶裝置之構成之圖。  圖22係用以說明圖21所示之半導體記憶裝置之製造方法之圖。  圖23係用以說明圖21所示之半導體記憶裝置之製造方法之圖。  圖24係用以說明圖21所示之半導體記憶裝置之製造方法之圖。  圖25係用以說明圖21所示之半導體記憶裝置之製造方法之圖。  圖26係用以說明圖21所示之半導體記憶裝置之製造方法之圖。  圖27係用以說明圖21所示之半導體記憶裝置之製造方法之圖。  圖28係用以說明圖21所示之半導體記憶裝置之製造方法之圖。  圖29係用以說明圖21所示之半導體記憶裝置之製造方法之圖。  圖30係用以說明圖21所示之半導體記憶裝置之製造方法之圖。  圖31係用以說明圖21所示之半導體記憶裝置之製造方法之圖。
B:基底基板
BE:金屬球
C1,C2,C3,C4,C5,C6:晶片
E:半導體記憶裝置
M:塑模樹脂層
P:保護膜

Claims (13)

  1. 一種半導體裝置之製造方法，其係於支持基板設置第1晶片，該第1晶片具有：第1面、作為與上述第1面為相反側之面之第2面及設置於上述第2面之第1電極；於上述第2面與上述第1晶片之側面形成第1保護膜；將上述第1晶片自上述第2面側薄化，以使上述第1電極露出；將具有第3面、設置於上述第3面之第2電極、作為與上述第3面為相反側之面之第4面、及第3電極之第2晶片以使所露出之上述第1電極與上述第2電極連接之方式接合於上述第1晶片。
  2. 如請求項1之半導體裝置之製造方法，其中於上述第4面、上述第2晶片之側面及上述第1晶片之側面形成第2保護膜；將上述第2晶片自上述第4面側薄化，以使上述第3電極露出；將具有第5面及設置於上述第5面之第4電極之第3晶片以使所露出之上述第3電極與上述第4電極連接之方式接合於上述第2晶片。
  3. 如請求項1或2之半導體裝置之製造方法，其中於上述第1晶片與上述第2晶片之接合後形成樹脂層，自上述第1晶片去除上述支持基板。
  4. 如請求項1或2之半導體裝置之製造方法，其中於將上述第1晶片薄化 之後，於上述第1晶片之上述第1面之相反側之面形成氧化膜。
  5. 如請求項4之半導體裝置之製造方法，其中於形成上述氧化膜之後研磨上述氧化膜之一部分。
  6. 如請求項4之半導體裝置之製造方法，其中上述第1保護膜包含氮化矽、碳化矽、類鑽碳中之至少一種，上述氧化膜包含氧化矽。
  7. 一種半導體裝置，其具備：基底基板，其包含配線層；第1晶片，其設置於上述基底基板之上；第2晶片，其設置於上述第1晶片之上；絕緣膜，其設置於上述第1晶片之側面與上述第2晶片之側面；及樹脂層，其覆蓋上述第2晶片與上述絕緣膜；其中與上述第1晶片之側面垂直之方向之上述絕緣膜之厚度較與上述第2晶片之側面垂直之方向之上述絕緣膜之厚度厚。
  8. 如請求項7之半導體裝置，其中上述絕緣膜包含氧化矽、氮化矽、碳化矽、氮化硼、類鑽碳中之至少一種。
  9. 如請求項7或8之半導體裝置，其中上述絕緣膜為保護膜與第1氧化膜 之積層膜。
  10. 如請求項9之半導體裝置，其中上述第1晶片之側面之上述保護膜之層數較上述第2晶片之側面之上述保護膜之層數多。
  11. 如請求項9之半導體裝置，其中於上述第1晶片之上述基底基板之相反方向之面，設置有第2氧化膜，上述第2氧化膜之上述第1晶片之周緣部之厚度較上述第2氧化膜之上述第1晶片之中央部之厚度薄。
  12. 如請求項11之半導體裝置，其中上述第1晶片之側面之上述保護膜之上端部自上述第1氧化膜及上述第2氧化膜露出。
  13. 如請求項11之半導體裝置，其中上述第1晶片之側面之上述保護膜之上端部處於上述第1氧化膜與上述第2氧化膜之間。
TW111105248A 2021-09-22 2022-02-14 半導體裝置及半導體裝置之製造方法 TWI832156B (zh)

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Citations (2)

* Cited by examiner, † Cited by third party
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US20100314749A1 (en) * 2004-06-30 2010-12-16 Nec Electronics Corporation Semiconductor device having a sealing resin and method of manufacturing the same
US20200161203A1 (en) * 2018-11-19 2020-05-21 Samsung Electronics Co., Ltd. Semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100314749A1 (en) * 2004-06-30 2010-12-16 Nec Electronics Corporation Semiconductor device having a sealing resin and method of manufacturing the same
US20200161203A1 (en) * 2018-11-19 2020-05-21 Samsung Electronics Co., Ltd. Semiconductor package

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