CN114639648A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN114639648A
CN114639648A CN202110676488.XA CN202110676488A CN114639648A CN 114639648 A CN114639648 A CN 114639648A CN 202110676488 A CN202110676488 A CN 202110676488A CN 114639648 A CN114639648 A CN 114639648A
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China
Prior art keywords
insulating film
layer
pad
metal
semiconductor device
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CN202110676488.XA
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Inventor
泽田元气
田上政由
饭岛纯
久米一平
吉田树誉满
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Kioxia Corp
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Kioxia Corp
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Publication of CN114639648A publication Critical patent/CN114639648A/zh
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Abstract

本发明的实施方式提供能够形成适宜的衬垫的半导体装置及其制造方法。根据一个实施方式，半导体装置具备第1衬垫，其是设置于第1绝缘膜内的第1衬垫，包含设置于第1绝缘膜的侧面及下表面的第1层、和介由第1层设置于第1绝缘膜的侧面及下表面的第2层。上述装置进一步具备第2衬垫，其是在第1绝缘膜上的第2绝缘膜内设置于第1衬垫上的第2衬垫，包含设置于第2绝缘膜的侧面及上表面的第3层、和介由第3层设置于第2绝缘膜的侧面及上表面的第4层。上述装置进一步具备第1部分，其设置于第1衬垫的上表面与第2绝缘膜的下表面之间、或第2衬垫的下表面与第1绝缘膜的上表面之间，包含与第1层或第3层中所含的金属元素相同的金属元素。

Description

半导体装置及其制造方法
关联申请
本申请享有以日本专利申请2020-208637号(申请日：2020年12月16日)作为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体装置及其制造方法。
背景技术
在将某基板上的金属衬垫(pad)及绝缘膜与另一基板上的金属衬垫及绝缘膜贴合来制造半导体装置的情况下，有时一个基板上的金属衬垫的表面露出到另一基板上的绝缘膜的表面。这种情况下，有可能产生金属原子(例如铜原子)从露出于绝缘膜的表面的金属衬垫的表面扩散等问题。
发明内容
实施方式提供能够形成适宜的衬垫的半导体装置及其制造方法。
根据一个实施方式，半导体装置具备第1绝缘膜和第1衬垫，所述第1衬垫设置于上述第1绝缘膜内，且包含设置于上述第1绝缘膜的侧面及下表面的第1层和介由上述第1层而设置于上述第1绝缘膜的侧面及下表面的第2层。上述装置进一步具备设置于上述第1绝缘膜上的第2绝缘膜和第2衬垫，所述第2衬垫在上述第2绝缘膜内设置于上述第1衬垫上，且包含设置于上述第2绝缘膜的侧面及上表面的第3层和介由上述第3层而设置于上述第2绝缘膜的侧面及上表面的第4层。上述装置进一步具备第1部分，所述第1部分设置于上述第1衬垫的上表面与上述第2绝缘膜的下表面之间、或上述第2衬垫的下表面与上述第1绝缘膜的上表面之间，包含与上述第1层或上述第3层中所含的金属元素相同的金属元素。
附图说明
图1是表示第1实施方式的半导体装置的结构的截面图。
图2是表示第1实施方式的柱状部CL的结构的截面图。
图3～图4是表示第1实施方式的半导体装置的制造方法的截面图。
图5是表示第1实施方式的比较例的半导体装置的结构的截面图。
图6是表示第1实施方式的半导体装置的结构的截面图。
图7～图11是表示第1实施方式的半导体装置的制造方法的截面图。
图12是表示第2实施方式的半导体装置的结构的截面图。
图13～图16是表示第2实施方式的半导体装置的制造方法的截面图。
图17是表示第3实施方式的半导体装置的结构的截面图。
图18是表示第4实施方式的半导体装置的结构的截面图。
图19是表示第5实施方式的半导体装置的结构的截面图。
图20是表示第6实施方式的半导体装置的结构的截面图。
符号的说明
1：阵列芯片、2：电路芯片、
11：存储单元阵列、12：绝缘膜、13：层间绝缘膜、13a：绝缘膜、13b：绝缘膜、13c：绝缘膜、13d：绝缘膜、13e：绝缘膜、14：层间绝缘膜、14a：绝缘膜、14b：绝缘膜、14c：绝缘膜、
14d：绝缘膜、14e：绝缘膜、15：基板、16：基板、
21：台阶结构部、22：接触插塞、
23：字布线层、24：通孔插塞、
31：晶体管、32：栅极电极、33：接触插塞、
34：布线层、35：布线层、36：布线层、
37：通孔插塞、37a：阻挡金属层、37b：插塞材层、
38：金属衬垫、38a：阻挡金属层、38b：衬垫材层、
41：金属衬垫、41a：阻挡金属层、41b：衬垫材层、
42：通孔插塞、42a：阻挡金属层、42b：插塞材层、
43：布线层、44：布线层、
45：通孔插塞、46：金属衬垫、47：钝化膜、
51：绝缘层、52：阻挡绝缘膜、53：电荷蓄积层、54：隧道绝缘膜、
55：沟道半导体层、56：芯绝缘膜、61：金属层
具体实施方式
以下，参照附图对本发明的实施方式进行说明。在图1～图20中，对相同的构成标注相同的符号，重复的说明省略。
(第1实施方式)
图1是表示第1实施方式的半导体装置的结构的截面图。图1的半导体装置是阵列芯片1与电路芯片2贴合而成的三维存储器。
阵列芯片1具备包含多个存储单元的存储单元阵列11、存储单元阵列11上的绝缘膜12和存储单元阵列11下的层间绝缘膜13。绝缘膜12例如为硅氧化膜或硅氮化膜。层间绝缘膜13例如为硅氧化膜、或包含硅氧化膜和其他绝缘膜的层叠膜。层间绝缘膜13为第2绝缘膜的例子。
电路芯片2设置于阵列芯片1下。符号S表示阵列芯片1与电路芯片2的贴合面。电路芯片2具备层间绝缘膜14和层间绝缘膜14下的基板15。层间绝缘膜14例如为硅氧化膜、或包含硅氧化膜和其他绝缘膜的层叠膜。层间绝缘膜14为第1绝缘膜的例子。基板15例如为硅基板等半导体基板。
图1表示与基板15的表面平行且相互垂直的X方向及Y方向和与基板15的表面垂直的Z方向。在本说明书中，将+Z方向作为上方向处理，将-Z方向作为下方向处理。-Z方向可以与重力方向一致，也可以不一致。
阵列芯片1具备多个字线WL和源线SL作为存储单元阵列11内的多个电极层。图1示出存储单元阵列11的台阶结构部21。各字线WL介由接触插塞22而与字布线层23电连接。贯穿多个字线WL的各柱状部CL介由通孔插塞24而与位线BL电连接，并且与源线SL电连接。源线SL包含作为半导体层的第1层SL1和作为金属层的第2层SL2。
电路芯片2具备多个晶体管31。各晶体管31具备介由栅极绝缘膜而设置于基板15上的栅极电极32和设置于基板15内的未图示的源极扩散层及漏极扩散层。另外，电路芯片2具备设置于这些晶体管31的栅极电极32、源极扩散层或漏极扩散层上的多个接触插塞33、设置于这些接触插塞33上且包含多个布线的布线层34和设置于布线层34上且包含多个布线的布线层35。
电路芯片2进一步具备设置于布线层35上且包含多个布线的布线层36、设置于布线层36上的多个通孔插塞37和设置于这些通孔插塞37上的多个金属衬垫38。金属衬垫38例如为包含Cu(铜)层的金属层。金属衬垫38为第1衬垫的例子，通孔插塞37为第1插塞的例子。电路芯片2作为控制阵列芯片1的动作的控制电路(逻辑电路)发挥功能。该控制电路由晶体管31等构成，与金属衬垫38电连接。
阵列芯片1具备设置于金属衬垫38上的多个金属衬垫41和设置于金属衬垫41上的多个通孔插塞42。另外，阵列芯片1具备设置于这些通孔插塞42上且包含多个布线的布线层43、和设置于布线层43上且包含多个布线的布线层44。金属衬垫41例如为包含Cu层的金属层。金属衬垫41为第2衬垫的例子，通孔插塞42为第2插塞的例子。上述的位线BL包含于布线层44中。上述的控制电路介由金属衬垫41、38等而与存储单元阵列11电连接，介由金属衬垫41、38等而控制存储单元阵列11的动作。
阵列芯片1进一步具备设置于布线层44上的多个通孔插塞45、设置于这些通孔插塞45上或绝缘膜12上的金属衬垫46、和设置于金属衬垫46上或绝缘膜12上的钝化膜47。金属衬垫46例如为包含Cu层的金属层，作为图1的半导体装置的外部连接衬垫(焊盘)发挥功能。钝化膜47例如为硅氧化膜等绝缘膜，具有使金属衬垫46的上表面露出的开口部P。金属衬垫46介由该开口部P通过接合线、焊锡球、金属凸块等而能够与安装基板或其他的装置连接。
图2是表示第1实施方式的柱状部CL的结构的截面图。
如图2中所示的那样，存储单元阵列11具备交替地层叠于层间绝缘膜13(图1)上的多个字线WL和多个绝缘层51。字线WL例如为W(钨)层。绝缘层51例如为硅氧化膜。
柱状部CL依次包含阻挡绝缘膜52、电荷蓄积层53、隧道绝缘膜54、沟道半导体层55及芯绝缘膜56。电荷蓄积层53例如为硅氮化膜，介由阻挡绝缘膜52而形成于字线WL及绝缘层51的侧面。电荷蓄积层53也可以为多晶硅层等半导体层。沟道半导体层55例如为多晶硅层，介由隧道绝缘膜54而形成于电荷蓄积层53的侧面。阻挡绝缘膜52、隧道绝缘膜54及芯绝缘膜56例如为硅氧化膜或金属绝缘膜。
图3及图4是表示第1实施方式的半导体装置的制造方法的截面图。
图3示出包含多个阵列芯片1的阵列晶片W1和包含多个电路芯片2的电路晶片W2。阵列晶片W1也被称为“存储晶片”，电路晶片W2也被称为“CMOS晶片”。
希望注意的是，图3的阵列晶片W1的方向与图1的阵列芯片1的方向相反。在本实施方式中，通过将阵列晶片W1与电路晶片W2贴合来制造半导体装置。图3示出为了贴合而使方向反转之前的阵列晶片W1，图1示出为了贴合而使方向反转并进行了贴合及切割之后的阵列芯片1。
在图3中，符号S1表示阵列晶片W1的上表面，符号S2表示电路晶片W2的上表面。希望注意的是，阵列晶片W1具备设置于绝缘膜12下的基板16。基板16例如为硅基板等半导体基板。
在本实施方式中，首先，如图3中所示的那样，在阵列晶片W1的基板16上形成存储单元阵列11、绝缘膜12、层间绝缘膜13、台阶结构部21、金属衬垫41等，在电路晶片W2的基板15上形成层间绝缘膜14、晶体管31、金属衬垫38等。例如，在基板16上依次形成通孔插塞45、布线层44、布线层43、通孔插塞42、及金属衬垫41。另外，在基板15上依次形成接触插塞33、布线层34、布线层35、布线层36、通孔插塞37、及金属衬垫38。接着，如图4中所示的那样，将阵列晶片W1与电路晶片W2通过机械压力而贴合。由此，层间绝缘膜13与层间绝缘膜14被粘接。接着，将阵列晶片W1及电路晶片W2以400℃退火。由此，金属衬垫41与金属衬垫38被接合。
之后，将基板15通过CMP(Chemical Mechanical Polishing，化学机械抛光)而薄膜化，将基板16通过CMP而除去后，将阵列晶片W1及电路晶片W2切断成多个芯片。像这样操作，制造了图1的半导体装置。图1示出包含金属衬垫38及层间绝缘膜14的电路芯片2、和包含分别配置于金属衬垫38及层间绝缘膜14上的金属衬垫41及层间绝缘膜13的阵列芯片1。需要说明的是，金属衬垫46和钝化膜47例如在基板15的薄膜化及基板16的除去之后形成于绝缘膜12上。
需要说明的是，在本实施方式中，将阵列晶片W1与电路晶片W2贴合，但也可以代替其而将阵列晶片W1彼此贴合。参照图1～图4在前文所述的内容和参照图5～图20在下文所述的内容也可以适用于阵列晶片W1彼此的贴合。
另外，图1示出层间绝缘膜13与层间绝缘膜14的边界面、金属衬垫41与金属衬垫38的边界面，但在上述的退火后，一般变得观察不到这些边界面。然而，这些边界面所在的位置能够通过检测例如金属衬垫41的侧面和金属衬垫38的侧面的倾斜、或金属衬垫41的侧面与金属衬垫38的位置偏移来推定。
另外，本实施方式的半导体装置可以以被切断成多个芯片后的图1的状态成为交易的对象，也可以以被切断成多个芯片之前的图4的状态成为交易的对象。图1示出芯片的状态的半导体装置，图4示出晶片的状态的半导体装置。在本实施方式中，由一个晶片状的半导体装置(图4)制造多个芯片状的半导体装置(图1)。
图5是表示第1实施方式的比较例的半导体装置的结构的截面图。图6是表示第1实施方式的半导体装置的结构的截面图。图5中所示的半导体装置与图6中所示的半导体装置的不同例如为金属层61的有无。金属层61为第1部分的例子。
以下，参照图6对本实施方式的半导体装置的结构进行说明，之后参照图5及图6，将本实施方式的半导体装置与比较例的半导体装置进行比较。
在本实施方式(图6)中，层间绝缘膜14包含依次设置于贴合面S下的绝缘膜14e、14d、14c、14b、14a，层间绝缘膜13包含依次设置于贴合面S上的绝缘膜13e、13d、13c、13b、13a。进而，金属衬垫38包含依次设置于层间绝缘膜14内的阻挡金属层38a和衬垫材层38b，金属衬垫41包含依次设置于层间绝缘膜13内的阻挡金属层41a和衬垫材层41b。本实施方式的半导体装置进一步具备上述的金属层61。
绝缘膜14a、14c、14e、13a、13c、13e例如为SiO2膜(硅氧化膜)。绝缘膜14b、13b例如为SiN膜(硅氮化膜)。本实施方式的绝缘膜14b、13b例如分别在通过蚀刻而在层间绝缘膜14、13内形成用于埋入金属衬垫38、41的孔时，作为蚀刻停止层来使用。绝缘膜14d、13d例如为SiCN膜(硅碳氮化膜)。本实施方式的绝缘膜14d、13d例如分别为了防止金属衬垫38、41内的Cu原子向层间绝缘膜14、13内扩散而形成。绝缘膜14d、13d分别为第3膜和第4膜的例子。另外，绝缘膜14e、13e分别为第1膜和第2膜的例子。
本实施方式的绝缘膜14e、13e为在将阵列晶片W1与电路晶片W2贴合之前，分别通过绝缘膜14d、13d的自然氧化而形成的自然氧化膜。因此，本实施方式的绝缘膜14e的下表面与绝缘膜14d的上表面相接，本实施方式的绝缘膜13e的上表面与绝缘膜13e的下表面相接。另外，本实施方式的绝缘膜14e的上表面与绝缘膜13e的下表面相接。需要说明的是，绝缘膜14e、13e可以通过自然氧化以外的原因而形成，例如也可以通过层间绝缘膜14、13的表面的CMP或等离子体处理而形成。
阻挡金属层38a形成于层间绝缘膜14的侧面和下表面(底面)，与层间绝缘膜14的侧面和下表面相接。衬垫材层38b介由阻挡金属层38a而形成于层间绝缘膜14的侧面和下表面。同样地，阻挡金属层41a形成于层间绝缘膜13的侧面和上表面(底面)，与层间绝缘膜13的侧面和上表面相接。衬垫材层41b介由阻挡金属层41a而形成于层间绝缘膜13的侧面和上表面。阻挡金属层38a、41a分别为第1层和第3层的例子。衬垫材层38b、41b分别为第2层和第4层的例子。
阻挡金属层38a、41a例如为包含Ti(钛)、Al(铝)、或Mn(锰)的金属层，这里为Ti层。本实施方式的阻挡金属层38a、41a例如分别为了防止金属衬垫38、41内的Cu原子向层间绝缘膜14、13内扩散而形成。阻挡金属层38a、41a也可以为包含金属元素和非金属元素的金属化合物层，例如也可以为金属氧化膜、金属氮化膜。另外，阻挡金属层38a、41a也可以为包含两种以上的金属元素的合金层。衬垫材层38b、41b例如为包含Cu的金属层，这里为Cu层。衬垫材层38b、41b也可以为Cu层以外的金属层。
本实施方式的金属衬垫38和金属衬垫41具有相同的平面形状。这些平面形状在这里为具有沿X方向延伸的两边和沿Y方向延伸的两边的正方形或长方形。因而，本实施方式的金属衬垫41的X方向的宽度和Y方向的宽度分别变得与金属衬垫38的X方向的宽度和Y方向的宽度相同。
因此，如果金属衬垫41被配置于金属衬垫38的正上方，则金属衬垫41的下表面变得仅与金属衬垫38的上表面相接，变得不与金属衬垫38以外的层的上表面相接。同样地，金属衬垫38的下表面变得仅与金属衬垫41的下表面相接，变得不与金属衬垫41以外的层的下表面相接。
然而，本实施方式的金属衬垫41未配置于金属衬垫38的正上方。因此，本实施方式的金属衬垫41的下表面不仅与金属衬垫38的上表面相接，而且被设置于层间绝缘膜14的上表面上。同样地，本实施方式的金属衬垫38的上表面不仅与金属衬垫38的下表面相接，而且被设置于层间绝缘膜13的下表面下。并且，在本实施方式中，金属层61被形成于金属衬垫38的上表面与层间绝缘膜13的下表面之间和金属衬垫41的下表面与层间绝缘膜14的上表面之间。
金属层61例如包含与阻挡金属层38a、41a内包含的金属元素相同的金属元素。该金属元素例如为Ti、Al或Mn。金属层61也可以进一步包含氧。在本实施方式中，阻挡金属层38a、41a为Ti层，金属层61为TiOx(氧化钛)层。
本实施方式的金属层61通过阻挡金属层38a、41a内的Ti原子扩散到衬垫材层38b与绝缘膜13e的界面、衬垫材层41b与绝缘膜14e的界面而形成，自整合地形成于这些界面的位置。本实施方式的金属层61成为包含来源于阻挡金属层38a、41a的Ti原子和来源于绝缘膜14e、13e的O原子的TiOx层。因而，本实施方式的金属层61的下表面与绝缘膜14e的上表面、衬垫材层38b的上表面相接，本实施方式的金属层61的上表面与绝缘膜13e的下表面、衬垫材层41b的下表面相接。
需要说明的是，金属层61也可以包含与阻挡金属层38a和阻挡金属层41a中的仅任一者中所含的金属元素相同的金属元素。例如，在阻挡金属层38a、41a中的仅阻挡金属层38a包含Ti原子、通过从阻挡金属层38a扩散的Ti原子而形成金属层61的情况下，变成阻挡金属层38a和金属层61包含Ti，阻挡金属层41a不含Ti。
另外，本实施方式的金属层61也可以以不能称为层的程度的薄的厚度或小的尺寸形成于金属衬垫38与层间绝缘膜13之间、金属衬垫41与层间绝缘膜14之间。对于形成本实施方式的金属层61的过程的进一步的详细情况，在下文叙述。
接着，参照图5及图6，将本实施方式的半导体装置与比较例的半导体装置进行比较。
在比较例(图5)中，阻挡金属层38a、41a不是Ti层而是成为Ta(钽)层。Ta原子与Ti原子相比不易扩散。因此，在比较例中，在金属衬垫38与层间绝缘膜13之间、金属衬垫41与层间绝缘膜14之间，未形成金属层61。
另外，在比较例中，绝缘膜14e、13e(SiO2膜)与本实施方式同样地形成于绝缘膜14d、13d(SiCN膜)间。SiO2膜与SiCN膜相比，防止Cu原子的扩散的作用小。因此，在比较例中，金属衬垫38、41内的Cu原子介由绝缘膜14e、13e而扩散到层间绝缘膜14、13内。Cu原子的扩散例如有可能在制造半导体装置时的退火工序中产生。扩散到层间绝缘膜14、13内的Cu原子例如成为在金属衬垫38彼此之间、金属衬垫41彼此之间、金属衬垫38与金属衬垫41之间等产生漏泄电流的原因。
如果金属衬垫38、41具有相同的平面形状、且金属衬垫41被配置于金属衬垫38的正上方，则Cu原子向层间绝缘膜14、13内的扩散基本不成问题。这种情况下，这是由于，金属衬垫41的下表面变得仅与金属衬垫38的上表面相接，金属衬垫38的上表面也变得仅与金属衬垫41的下表面相接。
然而，在将阵列晶片W1与电路晶片W2贴合时，金属衬垫38与金属衬垫41的对位有时产生误差。这种情况下，金属衬垫41未被配置于金属衬垫38的正上方，金属衬垫41的下表面变得与层间绝缘膜14的上表面也相接，金属衬垫38的上表面变得与层间绝缘膜13的下表面也相接。
即使是这种情况下，只要层间绝缘膜14的上表面由绝缘膜14d(SiCN膜)形成、层间绝缘膜13的下表面由绝缘膜13d(SiCN膜)形成，也能够抑制Cu原子向层间绝缘膜14、13内的扩散。这是由于，SiCN膜防止Cu原子的扩散的作用大。然而，若通过自然氧化等而层间绝缘膜14、13包含绝缘膜14e、13e(SiO2膜)，则金属衬垫38、41内的Cu原子介由绝缘膜14e、13e而扩散到层间绝缘膜14、13内。
另一方面，在本实施方式(图6)中，阻挡金属层38a、41a成为Ti层。Ti原子与Ta原子相比容易扩散。因此，在本实施方式中，在金属衬垫38与层间绝缘膜13之间、金属衬垫41与层间绝缘膜14之间形成有金属层61。因而，根据本实施方式，即使是金属衬垫41未被配置于金属衬垫38的正上方、并且通过自然氧化等而层间绝缘膜14、13包含绝缘膜14e、13e(SiO2膜)的情况下，也能够通过金属层61来抑制Cu原子从金属衬垫38、41向层间绝缘膜14、13的扩散。需要说明的是，带来金属层61的Ti原子的扩散例如在制造半导体装置时的退火工序中产生。
对于使用Ti层作为阻挡金属层38a、41a，存在TiOx层(金属层61)的阻挡性高的优点、形成Ti层的成本便宜即可的优点。需要说明的是，这样的阻挡效应在使用Al层来形成AlOx层的情况下、使用Mn层来形成MnOx层的情况下也能够获得。
需要说明的是，在金属衬垫38的正上方没有本实施方式的金属衬垫41的结构可以通过金属衬垫38与金属衬垫41的对位的误差而产生，也可以在制造半导体装置时有意图地产生。
图7～图11是表示第1实施方式的半导体装置的制造方法的截面图。图7～图11中所示的方法相当于图3及图4中所示的方法的具体例子。
首先，将阵列晶片W1及电路晶片W2加工成图7中所示的结构。具体而言，在基板16(参照图3)的上方形成绝缘膜13a，在绝缘膜13a内形成通孔插塞42，在绝缘膜13a及通孔插塞42上依次形成绝缘膜13b、13c、13d，在绝缘膜13b、13c、13d内依次形成阻挡金属层41a和衬垫材层41b。同样地，在基板15(参照图3)的上方形成绝缘膜14a，在绝缘膜14a内形成通孔插塞37，在绝缘膜14a及通孔插塞37上依次形成绝缘膜14b、14c、14d，在绝缘膜14b、14c、14d内依次形成阻挡金属层38a和衬垫材层38b。其结果是，在层间绝缘膜13、14内分别形成金属衬垫41、38。
接着，在绝缘膜13d、14d的表面，通过氧化而分别形成绝缘膜13e、14e(图8)。绝缘膜13e、14e例如通过自然氧化而形成。
接着，按照金属衬垫41被配置于金属衬垫38上、层间绝缘膜13被配置于层间绝缘膜14上的方式，将阵列晶片W1与电路晶片W2通过机械压力而贴合(图9)。由此，层间绝缘膜13与层间绝缘膜14被粘接。图9中，金属衬垫38与金属衬垫41的对位产生误差，金属衬垫38的上表面的一部分与金属衬垫41的下表面的一部分相接。
接着，将阵列晶片W1及电路晶片W2进行退火(图10)。由此，金属衬垫41与金属衬垫38被接合。图10进一步示出衬垫材层38b、41b内的晶粒间的晶界α、和沿着晶界α或贴合面S扩散的Ti原子组β。在本实施方式中，通过图10中所示的工序中的退火，Ti原子从阻挡金属层38a、41a扩散。
其结果是，阻挡金属层38a、41a内的Ti原子扩散到衬垫材层38b与绝缘膜13e的界面、衬垫材层41b与绝缘膜14e的界面中，在这些界面的位置自整合地形成金属层61(图11)。具体而言，从阻挡金属层38a、41a扩散到这些界面中的Ti原子与绝缘膜14e、13e内的O原子发生反应，形成TiOx层作为金属层61。因而，根据本实施方式，能够通过金属层61来抑制Cu原子从金属衬垫38、41向层间绝缘膜14、13的扩散。
像这样操作，制造了图6的半导体装置。之后，将基板15通过CMP而薄膜化，将基板16通过CMP而除去之后，将阵列晶片W1及电路晶片W2切断成多个芯片。像这样操作，制造了图1的半导体装置。
如以上那样，本实施方式的半导体装置在金属衬垫38的上表面与层间绝缘膜13的下表面之间、金属衬垫41的下表面与层间绝缘膜14的上表面之间具备包含与阻挡金属层38a、41a中所含的金属元素相同的金属元素的金属层61。因而，根据本实施方式，变得能够形成可抑制金属原子(例如Cu原子)从衬垫材层38b、41b向绝缘膜14e、13e的扩散等适宜的金属衬垫38、41。
(第2实施方式)
图12是表示第2实施方式的半导体装置的结构的截面图。
本实施方式的层间绝缘膜13、14不具备绝缘膜13d、14d(SiCN膜)，其结果是，也不具备绝缘膜13e、14e(SiO2膜)。在本实施方式中，层间绝缘膜13内的绝缘膜13c(SiO2膜)与层间绝缘膜14内的绝缘膜14c(SiO2膜)在贴合面S彼此相接。
本实施方式的半导体装置也具备金属层61。本实施方式的金属层61是从阻挡金属层38a、41a扩散的Ti原子与绝缘膜14c、13c内的O原子发生反应而形成的。
根据本实施方式，变得能够省略形成绝缘膜13d、14d的工夫。另外，根据本实施方式，由于在层间绝缘膜13、14的表面附近不存在绝缘膜13d、14d，因此变得能够将层间绝缘膜13、14的表面通过CMP而容易地平坦化。另一方面，根据第1实施方式，不仅能够通过金属层61而抑制Cu原子的扩散，而且也能够通过绝缘膜13d、14d而抑制Cu原子的扩散。
图13～图16是表示第2实施方式的半导体装置的制造方法的截面图。图13～图16中所示的方法相当于图3及图4中所示的方法的具体例子。
首先，将阵列晶片W1及电路晶片W2加工成图13中所示的结构。具体而言，在基板16(参照图3)的上方形成绝缘膜13a，在绝缘膜13a内形成通孔插塞42，在绝缘膜13a及通孔插塞42上依次形成绝缘膜13b、13c，在绝缘膜13b、13c内依次形成阻挡金属层41a和衬垫材层41b。同样地，在基板15(参照图3)的上方形成绝缘膜14a，在绝缘膜14a内形成通孔插塞37，在绝缘膜14a及通孔插塞37上依次形成绝缘膜14b、14c，在绝缘膜14b、14c内依次形成阻挡金属层38a和衬垫材层38b。其结果是，在层间绝缘膜13、14内分别形成金属衬垫41、38。
接着，按照金属衬垫41被配置于金属衬垫38上、层间绝缘膜13被配置于层间绝缘膜14上的方式，将阵列晶片W1与电路晶片W2通过机械压力而贴合(图14)。由此，层间绝缘膜13与层间绝缘膜14被粘接。图14中，金属衬垫38与金属衬垫41的对位产生误差，金属衬垫38的上表面的一部分与金属衬垫41的下表面的一部分相接。
接着，将阵列晶片W1及电路晶片W2进行退火(图15)。由此，金属衬垫41与金属衬垫38被接合。图15进一步示出衬垫材层38b、41b内的晶粒间的晶界α、和沿着晶界α或贴合面S而扩散的Ti原子组β。在本实施方式中，通过图15中所示的工序中的退火，Ti原子从阻挡金属层38a、41a进行扩散。
其结果是，阻挡金属层38a、41a内的Ti原子扩散到衬垫材层38b与绝缘膜13c的界面、衬垫材层41b与绝缘膜14c的界面，在这些界面的位置自整合地形成金属层61(图16)。具体而言，从阻挡金属层38a、41a扩散到这些界面中的Ti原子与绝缘膜14c、13c内的O原子发生反应，形成TiOx层作为金属层61。因而，根据本实施方式，能够通过金属层61而抑制Cu原子从金属衬垫38、41向层间绝缘膜14、13的扩散。
像这样操作，制造了图12的半导体装置。之后，将基板15通过CMP而薄膜化，将基板16通过CMP而除去之后，将阵列晶片W1及电路晶片W2切断成多个芯片。像这样操作，制造了图1的半导体装置。
如以上那样，本实施方式的半导体装置在金属衬垫38的上表面与层间绝缘膜13的下表面之间、金属衬垫41的下表面与层间绝缘膜14的上表面之间具备包含与阻挡金属层38a、41a中所含的金属元素相同的金属元素的金属层61。因而，根据本实施方式，变得能够形成可抑制金属原子(例如Cu原子)从衬垫材层38b、41b向绝缘膜14c、13c的扩散等适宜的金属衬垫38、41。
(第3实施方式)
图17是表示第3实施方式的半导体装置的结构的截面图。
本实施方式的层间绝缘膜13不具备绝缘膜13d(SiCN膜)，其结果是，也不具备绝缘膜13e(SiO2膜)。另一方面，本实施方式的层间绝缘膜14具备绝缘膜14d(SiCN膜)，其结果是，也具备绝缘膜14e(SiO2膜)。在本实施方式中，层间绝缘膜13内的绝缘膜13c(SiO2膜)与层间绝缘膜14内的绝缘膜14e(SiO2膜)在贴合面S彼此相接。
本实施方式的半导体装置也具备金属层61。本实施方式的金属层61是从阻挡金属层38a、41a扩散的Ti原子与绝缘膜14e、13c内的O原子发生反应而形成的。
根据本实施方式，关于层间绝缘膜14可以享受与第1实施方式同样的优点，关于层间绝缘膜13可以享受与第2实施方式同样的优点。本实施方式的半导体装置例如可以通过对于阵列晶片W1应用图13～图16中所示的方法、对于电路晶片W2应用图7～图11中所示的方法来制造。
需要说明的是，本实施方式的半导体装置中，层间绝缘膜13也可以具备绝缘膜13d、13e，层间绝缘膜14也可以不具备绝缘膜14d、14e。
(第4实施方式)
图18是表示第4实施方式的半导体装置的结构的截面图。
第1～第3实施方式的金属衬垫38和通孔插塞37成为单镶嵌布线，与此相对，本实施方式的金属衬垫38和通孔插塞37成为双镶嵌布线。因而，本实施方式的通孔插塞37内的阻挡金属层37a及插塞材层37b分别与金属衬垫38内的阻挡金属层38a及衬垫材层38b相同，通孔插塞37内的插塞材层37b与金属衬垫38内的衬垫材层38b相接。换言之，在衬垫材层38b与插塞材层37b的边界面未设置阻挡金属层38a、37b。阻挡金属层38a和阻挡金属层37b为第1层的例子，衬垫材层38b和插塞材层37b为第2层的例子。
同样地，第1～第3实施方式的金属衬垫41和通孔插塞42成为单镶嵌布线，与此相对，本实施方式的金属衬垫41和通孔插塞42成为双镶嵌布线。因而，本实施方式的通孔插塞42内的阻挡金属层42a及插塞材层42b分别与金属衬垫41内的阻挡金属层41a及衬垫材层41b相同，通孔插塞42内的插塞材层42b与金属衬垫41内的衬垫材层41b相接。换言之，在衬垫材层41b与插塞材层42b的边界面未设置阻挡金属层41a、42b。阻挡金属层41a和阻挡金属层42b为第3层的例子，衬垫材层41b和插塞材层42b为第4层的例子。
根据本实施方式，能够以较少的工序形成金属衬垫38和通孔插塞37，能够以较少的工序形成金属衬垫41和通孔插塞42。本实施方式的半导体装置例如可以通过在应用图7～图11中所示的方法时在图7的工序中使用双镶嵌法来代替单镶嵌而制造。
(第5实施方式)
图19是表示第5实施方式的半导体装置的结构的截面图。
本实施方式的金属衬垫38与金属衬垫41具有不同的平面形状。本实施方式的金属衬垫38与金属衬垫41的平面形状均为正方形或长方形，但金属衬垫41的X方向的宽度与金属衬垫38的X方向的宽度不同，金属衬垫41的Y方向的宽度与金属衬垫38的Y方向的宽度不同。例如，金属衬垫41的X方向的宽度变得比金属衬垫38的X方向的宽度短，金属衬垫41的Y方向的宽度变得比金属衬垫38的Y方向的宽度短，金属衬垫41的下表面的整体与金属衬垫38的上表面的一部分相接。
本实施方式的半导体装置也具备金属层61。本实施方式的金属层61是从阻挡金属层38a、41a扩散的Ti原子主要与绝缘膜13e内的O原子发生反应而形成的。
在第1～第4实施方式中，若在金属衬垫38与金属衬垫41的对位中产生误差，则金属衬垫38与金属衬垫41的接触面积发生变化，金属衬垫38与金属衬垫41的接触电阻发生变化。另一方面，在本实施方式中，即使金属衬垫38与金属衬垫41的对位产生小的误差，金属衬垫38与金属衬垫41的接触面积也不会发生变化，金属衬垫38与金属衬垫41的接触电阻也不会发生变化。因而，根据本实施方式，能够抑制伴随金属衬垫38与金属衬垫41的对位的误差而产生的问题。
本实施方式的金属衬垫38与金属衬垫41由于具有不同的平面形状，因此即使不产生金属衬垫38与金属衬垫41的对位的误差，也会出现金属衬垫38的上表面位于层间绝缘膜13的下表面下的部分、或金属衬垫41的下表面位于层间绝缘膜14的上表面上的部分。在本实施方式中，能够在这样的部分中形成金属层61。因而，根据本实施方式，能够享受金属衬垫38与金属衬垫41具有不同的平面形状的情况的优点，并且能够抑制金属衬垫38与金属衬垫41具有不同的平面形状的情况的缺点。
本实施方式的半导体装置例如可以通过在应用图7～图11中所示的方法时在图7的工序中使金属衬垫38的平面形状与金属衬垫41的平面形状不同来制造。需要说明的是，本实施方式中也可以使用单镶嵌来代替双镶嵌法。
(第6实施方式)
图20是表示第6实施方式的半导体装置的结构的截面图。
本实施方式的半导体装置不仅具备彼此相接的金属衬垫38、41(参照图1等)，而且具备如图20中所示的那样彼此不相接的金属衬垫38、41。这样的金属衬垫38、41例如作为不被用于将阵列晶片W1与电路晶片W2电连接的虚设衬垫而形成。虚设衬垫例如为了调整贴合面S中的金属衬垫38、41的密度而形成。
本实施方式的半导体装置也具备金属层61。本实施方式的金属衬垫38上的金属层61是从阻挡金属层38a扩散的Ti原子主要与绝缘膜13e内的O原子发生反应而形成的。另一方面，本实施方式的金属衬垫41下的金属层61是从阻挡金属层41a扩散的Ti原子主要与绝缘膜14e内的O原子发生反应而形成的。
本实施方式的半导体装置例如可以通过在应用图7～图11中所示的方法时在图9的工序中按照图20中所示的金属衬垫38与金属衬垫41不相接的方式将阵列晶片W1与电路晶片W2贴合来制造。
以上，对几个实施方式进行了说明，但这些实施方式是仅作为例子而提出的，并不意图限定发明的范围。本说明书中说明的新颖的装置及方法可以以其他的各种方式来实施。另外，对于本说明书中说明的装置及方法的方式，在不脱离发明的主旨的范围内，可以进行各种省略、置换、变更。所附的权利要求书及与其同等的范围按照包含发明的范围、主旨中所含的这样的方式和变形例的方式意图。

Claims (15)

1.一种半导体装置，其具备：
第1绝缘膜；
第1衬垫，该第1衬垫是设置于所述第1绝缘膜内的第1衬垫，包含设置于所述第1绝缘膜的侧面及下表面的第1层和介由所述第1层设置于所述第1绝缘膜的侧面及下表面的第2层；
第2绝缘膜，该第2绝缘膜设置于所述第1绝缘膜上；
第2衬垫，该第2衬垫是在所述第2绝缘膜内设置于所述第1衬垫上的第2衬垫，包含设置于所述第2绝缘膜的侧面及上表面的第3层和介由所述第3层设置于所述第2绝缘膜的侧面及上表面的第4层；和
第1部分，该第1部分设置于所述第1衬垫的上表面与所述第2绝缘膜的下表面之间、或所述第2衬垫的下表面与所述第1绝缘膜的上表面之间，包含与所述第1层或所述第3层中所含的金属元素相同的金属元素。
2.根据权利要求1所述的半导体装置，其中，所述第1部分包含所述金属元素和氧。
3.根据权利要求1或2所述的半导体装置，其中，所述金属元素包含钛、铝或锰。
4.根据权利要求1或2所述的半导体装置，其中，所述第1层与所述第1绝缘膜的侧面及下表面相接，或者
所述第3层与所述第2绝缘膜的侧面及上表面相接。
5.根据权利要求1或2所述的半导体装置，其中，所述第1绝缘膜包含含有氧且与所述第1部分的下表面相接的第1膜，或者
所述第2绝缘膜包含含有氧且与所述第1部分的上表面相接的第2膜。
6.根据权利要求5所述的半导体装置，其中，所述第1膜或所述第2膜为自然氧化膜。
7.根据权利要求5所述的半导体装置，其中，所述第1绝缘膜包含所述第1膜、和含有碳及氮且与所述第1膜的下表面相接的第3膜，或者
所述第2绝缘膜包含所述第2膜、和含有碳及氮且与所述第2膜的上表面相接的第4膜。
8.根据权利要求1或2所述的半导体装置，其中，所述第1衬垫与所述第2衬垫具有相同的宽度。
9.根据权利要求1或2所述的半导体装置，其中，所述第1衬垫与所述第2衬垫具有不同的宽度。
10.根据权利要求1或2所述的半导体装置，其中，所述第1衬垫设置于包含所述第1层及所述第2层的第1插塞上，所述第1插塞内的所述第2层与所述第1衬垫内的所述第2层相接，或者
所述第2衬垫设置于包含所述第3层及所述第4层的第2插塞下，所述第2插塞内的所述第4层与所述第2衬垫内的所述第4层相接。
11.一种半导体装置，其具备：
第1绝缘膜；
第1衬垫，该第1衬垫是设置于所述第1绝缘膜内的第1衬垫，包含设置于所述第1绝缘膜的侧面及下表面的第1层、和介由所述第1层设置于所述第1绝缘膜的侧面及下表面的第2层；
第2绝缘膜，该第2绝缘膜设置于所述第1绝缘膜上；
第2衬垫，该第2衬垫是在所述第2绝缘膜内设置于不与所述第1衬垫相接的位置的第2衬垫，包含设置于所述第2绝缘膜的侧面及上表面的第3层、和介由所述第3层设置于所述第2绝缘膜的侧面及上表面的第4层；和
第1部分，该第1部分设置于所述第1衬垫的上表面与所述第2绝缘膜的下表面之间、或所述第2衬垫的下表面与所述第1绝缘膜的上表面之间，包含与所述第1层或所述第3层中所含的金属元素相同的金属元素。
12.根据权利要求11所述的半导体装置，其中，所述第1部分包含所述金属元素和氧。
13.根据权利要求11或12所述的半导体装置，其中，所述金属元素包含钛、铝或锰。
14.一种半导体装置的制造方法，其包括：
在第1绝缘膜内形成第1衬垫，所述第1衬垫包含设置于所述第1绝缘膜的侧面及底面的第1层、和介由所述第1层设置于所述第1绝缘膜的侧面及底面的第2层；
在第2绝缘膜内形成第2衬垫，所述第2衬垫包含设置于所述第2绝缘膜的侧面及底面的第3层、和介由所述第3层设置于所述第2绝缘膜的侧面及底面的第4层；
在所述第1绝缘膜上配置所述第2绝缘膜，并且在所述第1衬垫上配置所述第2衬垫；和
在所述第1衬垫的上表面与所述第2绝缘膜的下表面之间、或所述第2衬垫的下表面与所述第1绝缘膜的上表面之间形成第1部分，所述第1部分包含与所述第1层或所述第3层中所含的金属元素相同的金属元素。
15.根据权利要求14所述的半导体装置的制造方法，其中，所述第1部分通过从所述第1层或所述第3层扩散的所述金属元素而形成。
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