CN114639648A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN114639648A
CN114639648A CN202110676488.XA CN202110676488A CN114639648A CN 114639648 A CN114639648 A CN 114639648A CN 202110676488 A CN202110676488 A CN 202110676488A CN 114639648 A CN114639648 A CN 114639648A
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China
Prior art keywords
insulating film
layer
pad
metal
semiconductor device
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CN202110676488.XA
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Chinese (zh)
Inventor
泽田元气
田上政由
饭岛纯
久米一平
吉田树誉满
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Kioxia Corp
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Kioxia Corp
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Publication of CN114639648A publication Critical patent/CN114639648A/en
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Abstract

Embodiments of the invention provide a semiconductor device capable of forming a suitable pad and a method for manufacturing the same. According to one embodiment, a semiconductor device includes a 1 st pad which is a 1 st pad provided in a 1 st insulating film, and includes a 1 st layer provided on side surfaces and a lower surface of the 1 st insulating film, and a 2 nd layer provided on the side surfaces and the lower surface of the 1 st insulating film via the 1 st layer. The device further includes a 2 nd spacer which is a 2 nd spacer provided on the 1 st spacer within the 2 nd insulating film on the 1 st insulating film, and which includes a 3 rd layer provided on a side surface and an upper surface of the 2 nd insulating film, and a 4 th layer provided on a side surface and an upper surface of the 2 nd insulating film via the 3 rd layer. The device further includes a 1 st portion which is provided between the upper surface of the 1 st pad and the lower surface of the 2 nd insulating film, or between the lower surface of the 2 nd pad and the upper surface of the 1 st insulating film, and which contains the same metal element as that contained in the 1 st layer or the 3 rd layer.

Description

Semiconductor device and method for manufacturing the same
Related application
This application has priority to basic applications in Japanese patent application No. 2020-. The present application incorporates the entire contents of the base application by reference thereto.
Technical Field
Embodiments of the invention relate to a semiconductor device and a method of manufacturing the same.
Background
In the case of manufacturing a semiconductor device by bonding a metal pad (pad) and an insulating film on one substrate to a metal pad and an insulating film on another substrate, the surface of the metal pad on one substrate may be exposed to the surface of the insulating film on the other substrate. In this case, there is a possibility that a problem such as diffusion of metal atoms (for example, copper atoms) from the surface of the metal pad exposed on the surface of the insulating film occurs.
Disclosure of Invention
Embodiments provide a semiconductor device capable of forming an appropriate pad and a method for manufacturing the same.
According to one embodiment, a semiconductor device includes a 1 st insulating film and a 1 st pad, the 1 st pad being provided within the 1 st insulating film and including a 1 st layer provided on a side surface and a lower surface of the 1 st insulating film and a 2 nd layer provided on a side surface and a lower surface of the 1 st insulating film via the 1 st layer. The device further includes a 2 nd insulating film and a 2 nd spacer provided on the 1 st insulating film, the 2 nd spacer being provided on the 1 st spacer within the 2 nd insulating film and including a 3 rd layer provided on a side surface and an upper surface of the 2 nd insulating film and a 4 th layer provided on a side surface and an upper surface of the 2 nd insulating film via the 3 rd layer. The device further includes a 1 st portion, the 1 st portion being provided between the upper surface of the 1 st pad and the lower surface of the 2 nd insulating film or between the lower surface of the 2 nd pad and the upper surface of the 1 st insulating film, and containing the same metal element as that contained in the 1 st layer or the 3 rd layer.
Drawings
Fig. 1 is a sectional view showing the structure of a semiconductor device according to embodiment 1.
Fig. 2 is a sectional view showing the structure of the columnar section CL according to embodiment 1.
Fig. 3 to 4 are sectional views showing a method for manufacturing a semiconductor device according to embodiment 1.
Fig. 5 is a sectional view showing the structure of a semiconductor device according to a comparative example of embodiment 1.
Fig. 6 is a sectional view showing the structure of the semiconductor device according to embodiment 1.
Fig. 7 to 11 are sectional views showing a method for manufacturing the semiconductor device according to embodiment 1.
Fig. 12 is a sectional view showing the structure of the semiconductor device according to embodiment 2.
Fig. 13 to 16 are sectional views showing a method for manufacturing a semiconductor device according to embodiment 2.
Fig. 17 is a sectional view showing the structure of the semiconductor device according to embodiment 3.
Fig. 18 is a sectional view showing the structure of the semiconductor device according to embodiment 4.
Fig. 19 is a sectional view showing the structure of the semiconductor device according to embodiment 5.
Fig. 20 is a sectional view showing the structure of the semiconductor device according to embodiment 6.
Description of the symbols
1: array chip, 2: a circuit chip,
11: memory cell array, 12: insulating film, 13: interlayer insulating film, 13 a: insulating film, 13 b: insulating film, 13 c: insulating film, 13 d: insulating film, 13 e: insulating film, 14: interlayer insulating film, 14 a: insulating film, 14 b: insulating film, 14 c: an insulating film,
14 d: insulating film, 14 e: insulating film, 15: substrate, 16: a substrate,
21: step structure portion, 22: a contact plug,
23: word routing layer, 24: a through hole plug,
31: transistor, 32: gate electrode, 33: a contact plug,
34: wiring layer, 35: wiring layer, 36: a wiring layer,
37: through-hole plug, 37 a: barrier metal layer, 37 b: a plug material layer,
38: metal gasket, 38 a: barrier metal layer, 38 b: a liner material layer,
41: metal gasket, 41 a: barrier metal layer, 41 b: a liner material layer,
42: through-hole plug, 42 a: barrier metal layer, 42 b: a plug material layer,
43: wiring layer, 44: a wiring layer,
45: via plug, 46: metal gasket, 47: a passivation film,
51: insulating layer, 52: barrier insulating film, 53: charge storage layer, 54: a tunnel insulating film,
55: channel semiconductor layer, 56: core insulating film, 61: metal layer
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In fig. 1 to 20, the same components are denoted by the same reference numerals, and redundant description is omitted.
(embodiment 1)
Fig. 1 is a sectional view showing a structure of a semiconductor device according to embodiment 1. The semiconductor device of fig. 1 is a three-dimensional memory in which an array chip 1 and a circuit chip 2 are bonded to each other.
The array chip 1 includes a memory cell array 11 including a plurality of memory cells, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 under the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film. The interlayer insulating film 13 is an example of the 2 nd insulating film.
The circuit chip 2 is disposed under the array chip 1. Symbol S denotes a bonding surface between the array chip 1 and the circuit chip 2. The circuit chip 2 includes an interlayer insulating film 14 and a substrate 15 under the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film. The interlayer insulating film 14 is an example of the 1 st insulating film. The substrate 15 is a semiconductor substrate such as a silicon substrate.
Fig. 1 shows an X direction and a Y direction parallel to and perpendicular to the surface of the substrate 15, and a Z direction perpendicular to the surface of the substrate 15. In this specification, the + Z direction is treated as the up direction, and the-Z direction is treated as the down direction. the-Z direction may or may not coincide with the direction of gravity.
The array chip 1 includes a plurality of word lines WL and source lines SL as a plurality of electrode layers in the memory cell array 11. Fig. 1 shows a step structure portion 21 of the memory cell array 11. Each word line WL is electrically connected to the word line layer 23 through a contact plug 22. Each columnar portion CL penetrating the plurality of word lines WL is electrically connected to the bit line BL via the via plug 24 and is also electrically connected to the source line SL. The source line SL includes a 1 st layer SL1 as a semiconductor layer and a 2 nd layer SL2 as a metal layer.
The circuit chip 2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 provided on the substrate 15 with a gate insulating film interposed therebetween, and a source diffusion layer and a drain diffusion layer, not shown, provided in the substrate 15. The circuit chip 2 includes a plurality of contact plugs 33 provided on the gate electrodes 32, the source diffusion layers, and the drain diffusion layers of the transistors 31, a wiring layer 34 provided on the contact plugs 33 and including a plurality of wirings, and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wirings.
The circuit chip 2 further includes a wiring layer 36 including a plurality of wirings and provided on the wiring layer 35, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metal pads 38 provided on the via plugs 37. The metal pad 38 is, for example, a metal layer including a Cu (copper) layer. The metal pad 38 is an example of the 1 st pad, and the via plug 37 is an example of the 1 st plug. The circuit chip 2 functions as a control circuit (logic circuit) for controlling the operation of the array chip 1. The control circuit is composed of a transistor 31 and the like, and is electrically connected to the metal pad 38.
The array chip 1 includes a plurality of metal pads 41 provided on the metal pad 38 and a plurality of via plugs 42 provided on the metal pads 41. The array chip 1 includes a wiring layer 43 provided on the via plugs 42 and including a plurality of wires, and a wiring layer 44 provided on the wiring layer 43 and including a plurality of wires. The metal pad 41 is, for example, a metal layer including a Cu layer. The metal pad 41 is an example of a 2 nd pad, and the via plug 42 is an example of a 2 nd plug. The bit line BL described above is included in the wiring layer 44. The control circuit is electrically connected to the memory cell array 11 through the metal pads 41 and 38, and controls the operation of the memory cell array 11 through the metal pads 41 and 38.
The array chip 1 further includes a plurality of via plugs 45 provided on the wiring layer 44, metal pads 46 provided on the via plugs 45 or on the insulating film 12, and a passivation film 47 provided on the metal pads 46 or on the insulating film 12. The metal pad 46 is, for example, a metal layer including a Cu layer, and functions as an external connection pad (pad) of the semiconductor device of fig. 1. The passivation film 47 is an insulating film such as a silicon oxide film, and has an opening P for exposing the upper surface of the metal pad 46. The metal pad 46 can be connected to a mounting board or other devices through the opening P by a bonding wire, a solder ball, a metal bump, or the like.
Fig. 2 is a sectional view showing the structure of the columnar section CL according to embodiment 1.
As shown in fig. 2, the memory cell array 11 includes a plurality of word lines WL and a plurality of insulating layers 51 alternately stacked on the interlayer insulating film 13 (fig. 1). The word line WL is, for example, a W (tungsten) layer. The insulating layer 51 is, for example, a silicon oxide film.
The columnar section CL includes a barrier insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56 in this order. The charge storage layer 53 is, for example, a silicon nitride film, and is formed on the side surfaces of the word line WL and the insulating layer 51 through the barrier insulating film 52. The charge storage layer 53 may be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55 is, for example, a polysilicon layer, and is formed on the side surface of the charge storage layer 53 via the tunnel insulating film 54. The barrier insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, a silicon oxide film or a metal insulating film.
Fig. 3 and 4 are sectional views showing a method for manufacturing a semiconductor device according to embodiment 1.
Fig. 3 shows an array wafer W1 containing a plurality of array chips 1 and a circuit wafer W2 containing a plurality of circuit chips 2. The array wafer W1 is also referred to as a "memory wafer", and the circuit wafer W2 is also referred to as a "CMOS wafer".
It is desirable to note that the direction of the array wafer W1 of fig. 3 is opposite to the direction of the array chip 1 of fig. 1. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2. Fig. 3 shows the array wafer W1 before the direction is reversed for bonding, and fig. 1 shows the array chip 1 after bonding and dicing after the direction is reversed for bonding.
In fig. 3, reference numeral S1 denotes the upper surface of the array wafer W1, and reference numeral S2 denotes the upper surface of the circuit wafer W2. It is to be noted that the array wafer W1 includes the substrate 16 disposed under the insulating film 12. The substrate 16 is a semiconductor substrate such as a silicon substrate.
In the present embodiment, first, as shown in fig. 3, the memory cell array 11, the insulating film 12, the interlayer insulating film 13, the step structure portion 21, the metal pad 41, and the like are formed on the substrate 16 of the array wafer W1, and the interlayer insulating film 14, the transistor 31, the metal pad 38, and the like are formed on the substrate 15 of the circuit wafer W2. For example, via plug 45, wiring layer 44, wiring layer 43, via plug 42, and metal pad 41 are formed in this order on substrate 16. Further, a contact plug 33, a wiring layer 34, a wiring layer 35, a wiring layer 36, a via plug 37, and a metal pad 38 are formed in this order on the substrate 15. Next, as shown in fig. 4, the array wafer W1 and the circuit wafer W2 were bonded to each other by mechanical pressure. Thereby, the interlayer insulating film 13 and the interlayer insulating film 14 are bonded. Next, the array wafer W1 and the circuit wafer W2 were annealed at 400 ℃. Thereby, the metal pad 41 and the metal pad 38 are bonded.
Thereafter, the substrate 15 is thinned by CMP (Chemical Mechanical Polishing), the substrate 16 is removed by CMP, and the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor device of fig. 1 is manufactured. Fig. 1 shows a circuit chip 2 including a metal pad 38 and an interlayer insulating film 14, and an array chip 1 including a metal pad 41 and an interlayer insulating film 13 respectively disposed on the metal pad 38 and the interlayer insulating film 14. The metal pad 46 and the passivation film 47 are formed on the insulating film 12 after thinning the substrate 15 and removing the substrate 16, for example.
In the present embodiment, the array wafer W1 and the circuit wafer W2 are bonded, but instead of this, the array wafers W1 may be bonded to each other. The foregoing description with reference to fig. 1 to 4 and the following description with reference to fig. 5 to 20 may also be applied to the bonding of the array wafers W1 to each other.
Fig. 1 shows the boundary surface between interlayer insulating film 13 and interlayer insulating film 14, and the boundary surface between metal pad 41 and metal pad 38, but these boundary surfaces are generally not observed after the above-described annealing. However, the positions of these boundary surfaces can be estimated by detecting, for example, the inclination of the side surface of the metal pad 41 and the side surface of the metal pad 38, or the positional deviation between the side surface of the metal pad 41 and the metal pad 38.
The semiconductor device of the present embodiment may be a target of transaction in the state of fig. 1 after being cut into a plurality of chips, or may be a target of transaction in the state of fig. 4 before being cut into a plurality of chips. Fig. 1 shows a semiconductor device in a chip state, and fig. 4 shows a semiconductor device in a wafer state. In this embodiment, a plurality of chip-shaped semiconductor devices (fig. 1) are manufactured from one wafer-shaped semiconductor device (fig. 4).
Fig. 5 is a sectional view showing the structure of a semiconductor device according to a comparative example of embodiment 1. Fig. 6 is a sectional view showing the structure of the semiconductor device according to embodiment 1. The semiconductor device shown in fig. 5 is different from the semiconductor device shown in fig. 6, for example, in the presence or absence of a metal layer 61. Metal layer 61 is an example of part 1.
The structure of the semiconductor device of the present embodiment will be described below with reference to fig. 6, and then the semiconductor device of the present embodiment is compared with the semiconductor device of the comparative example with reference to fig. 5 and 6.
In this embodiment (fig. 6), the interlayer insulating film 14 includes insulating films 14e, 14d, 14c, 14b, and 14a provided in this order below the bonding surface S, and the interlayer insulating film 13 includes insulating films 13e, 13d, 13c, 13b, and 13a provided in this order above the bonding surface S. Further, the metal spacer 38 includes a barrier metal layer 38a and a spacer layer 38b provided in this order in the interlayer insulating film 14, and the metal spacer 41 includes a barrier metal layer 41a and a spacer layer 41b provided in this order in the interlayer insulating film 13. The semiconductor device of the present embodiment further includes the metal layer 61 described above.
The insulating films 14a, 14c, 14e, 13a, 13c, 13e are, for example, SiO2Film (silicon oxide film). The insulating films 14b and 13b are, for example, SiN films (silicon nitride films). The insulating films 14b and 13b of the present embodiment are used as etching stoppers when holes for embedding the metal pads 38 and 41 are formed in the interlayer insulating films 14 and 13 by etching, respectively. The insulating films 14d and 13d are, for example, SiCN films (silicon carbonitride films). The insulating films 14d and 13d of the present embodiment are formed, for example, to prevent Cu atoms in the metal pads 38 and 41 from diffusing into the interlayer insulating films 14 and 13, respectively. The insulating films 14d, 13d are examples of the 3 rd film and the 4 th film, respectively. The insulating films 14e and 13e are examples of the 1 st film and the 2 nd film, respectively.
The insulating films 14e and 13e of the present embodiment are natural oxide films formed by natural oxidation of the insulating films 14d and 13d, respectively, before the array wafer W1 and the circuit wafer W2 are bonded to each other. Therefore, the lower surface of the insulating film 14e of the present embodiment is in contact with the upper surface of the insulating film 14d, and the upper surface of the insulating film 13e of the present embodiment is in contact with the lower surface of the insulating film 13 e. The upper surface of the insulating film 14e in this embodiment is in contact with the lower surface of the insulating film 13 e. The insulating films 14e and 13e may be formed by a factor other than natural oxidation, and may be formed by CMP or plasma treatment of the surfaces of the interlayer insulating films 14 and 13, for example.
The barrier metal layer 38a is formed on the side surface and the lower surface (bottom surface) of the interlayer insulating film 14, and is in contact with the side surface and the lower surface of the interlayer insulating film 14. The spacer layer 38b is formed on the side surface and the lower surface of the interlayer insulating film 14 via the barrier metal layer 38 a. Similarly, the barrier metal layer 41a is formed on the side surface and the upper surface (bottom surface) of the interlayer insulating film 13, and is in contact with the side surface and the upper surface of the interlayer insulating film 13. The spacer layer 41b is formed on the side surface and the upper surface of the interlayer insulating film 13 via the barrier metal layer 41 a. Barrier metal layers 38a, 41a are examples of layer 1 and layer 3, respectively. The spacer layers 38b, 41b are examples of the 2 nd and 4 th layers, respectively.
The barrier metal layers 38a, 41a are, for example, metal layers containing Ti (titanium), Al (aluminum), or Mn (manganese), and here are Ti layers. The barrier metal layers 38a and 41a of the present embodiment are formed, for example, to prevent Cu atoms in the metal pads 38 and 41 from diffusing into the interlayer insulating films 14 and 13, respectively. The barrier metal layers 38a and 41a may be a metal compound layer containing a metal element and a nonmetal element, and may be a metal oxide film or a metal nitride film, for example. The barrier metal layers 38a and 41a may be alloy layers containing two or more metal elements. The spacer layers 38b, 41b are, for example, metal layers containing Cu, in this case Cu layers. The spacer layers 38b and 41b may be metal layers other than Cu layers.
The metal pad 38 and the metal pad 41 of the present embodiment have the same planar shape. These planar shapes are here squares or rectangles having two sides extending in the X direction and two sides extending in the Y direction. Therefore, the width in the X direction and the width in the Y direction of the metal spacer 41 of the present embodiment are the same as the width in the X direction and the width in the Y direction of the metal spacer 38, respectively.
Therefore, if the metal pad 41 is disposed directly above the metal pad 38, the lower surface of the metal pad 41 comes into contact only with the upper surface of the metal pad 38, and does not come into contact with the upper surface of a layer other than the metal pad 38. Similarly, the lower surface of the metal spacer 38 comes into contact only with the lower surface of the metal spacer 41, and does not come into contact with the lower surface of a layer other than the metal spacer 41.
However, the metal pad 41 of the present embodiment is not disposed directly above the metal pad 38. Therefore, the lower surface of the metal pad 41 of the present embodiment is not only in contact with the upper surface of the metal pad 38, but also provided on the upper surface of the interlayer insulating film 14. Similarly, the upper surface of the metal pad 38 of the present embodiment is not only in contact with the lower surface of the metal pad 38, but also provided below the lower surface of the interlayer insulating film 13. In the present embodiment, the metal layer 61 is formed between the upper surface of the metal pad 38 and the lower surface of the interlayer insulating film 13 and between the lower surface of the metal pad 41 and the upper surface of the interlayer insulating film 14.
The metal layer 61 contains, for example, the same metal element as that contained in the barrier metal layers 38a and 41 a. The metal element is, for example, Ti, Al or Mn. The metal layer 61 may further contain oxygen. In this embodiment, the barrier metal layers 38a and 41a are Ti layers, and the metal layer 61 is TiOxA (titanium oxide) layer.
The metal layer 61 of the present embodiment is formed by diffusing Ti atoms in the barrier metal layers 38a and 41a to the interface between the spacer layer 38b and the insulating film 13e and the interface between the spacer layer 41b and the insulating film 14e, and is formed at the position of these interfaces in a self-aligned manner. The metal layer 61 of the present embodiment is a TiO containing Ti atoms derived from the barrier metal layers 38a and 41a and O atoms derived from the insulating films 14e and 13exAnd (3) a layer. Therefore, the lower surface of the metal layer 61 of the present embodiment is in contact with the upper surface of the insulating film 14e and the upper surface of the spacer layer 38b, and the upper surface of the metal layer 61 of the present embodiment is in contact with the lower surface of the insulating film 13e and the lower surface of the spacer layer 41 b.
The metal layer 61 may contain the same metal element as that contained in only one of the barrier metal layer 38a and the barrier metal layer 41 a. For example, in the case where only the barrier metal layer 38a of the barrier metal layers 38a, 41a contains Ti atoms and the metal layer 61 is formed by Ti atoms diffused from the barrier metal layer 38a, it becomes that the barrier metal layer 38a and the metal layer 61 contain Ti and the barrier metal layer 41a does not contain Ti.
The metal layer 61 of the present embodiment may be formed between the metal pad 38 and the interlayer insulating film 13, or between the metal pad 41 and the interlayer insulating film 14, in a thin thickness or in a small size that cannot be referred to as a layer. Further details of the process of forming the metal layer 61 of the present embodiment will be described below.
Next, referring to fig. 5 and 6, the semiconductor device of the present embodiment is compared with the semiconductor device of the comparative example.
In the comparative example (fig. 5), the barrier metal layers 38a and 41a are not Ti layers but Ta (tantalum) layers. Ta atoms are less likely to diffuse than Ti atoms. Therefore, in the comparative example, the metal layer 61 is not formed between the metal pad 38 and the interlayer insulating film 13, and between the metal pad 41 and the interlayer insulating film 14.
In the comparative example, the insulating films 14e and 13e (SiO)2Film) is formed between the insulating films 14d and 13d (SiCN film) in the same manner as in this embodiment. SiO 22The film has a smaller effect of preventing diffusion of Cu atoms than a SiCN film. Therefore, in the comparative example, Cu atoms in the metal pads 38 and 41 diffuse into the interlayer insulating films 14 and 13 through the insulating films 14e and 13 e. Diffusion of Cu atoms may occur, for example, in an annealing step in the manufacture of a semiconductor device. Cu atoms diffused into interlayer insulating films 14 and 13 cause leakage current between metal pads 38, metal pads 41, metal pads 38 and metal pads 41, for example.
If the metal pads 38, 41 have the same planar shape and the metal pad 41 is disposed directly above the metal pad 38, diffusion of Cu atoms into the interlayer insulating films 14, 13 is not substantially problematic. In this case, the lower surface of the metal spacer 41 comes into contact with only the upper surface of the metal spacer 38, and the upper surface of the metal spacer 38 comes into contact with only the lower surface of the metal spacer 41.
However, when the array wafer W1 and the circuit wafer W2 are bonded to each other, an error may occur in the alignment between the metal pads 38 and the metal pads 41. In this case, the metal pad 41 is not disposed directly above the metal pad 38, the lower surface of the metal pad 41 is also in contact with the upper surface of the interlayer insulating film 14, and the upper surface of the metal pad 38 is also in contact with the lower surface of the interlayer insulating film 13.
Even in this case, if the upper surface of the interlayer insulating film 14 is formed of the insulating film 14d (SiCN film) and the lower surface of the interlayer insulating film 13 is formed of the insulating film 13d (SiCN film), it is possible to suppressDiffusion of Cu atoms into the interlayer insulating films 14 and 13. This is because the SiCN film has a large effect of preventing diffusion of Cu atoms. However, if the interlayer insulating films 14 and 13 include the insulating films 14e and 13e (SiO) by natural oxidation or the like2Film), Cu atoms in the metal pads 38, 41 diffuse into the interlayer insulating films 14, 13 through the insulating films 14e, 13 e.
On the other hand, in the present embodiment (fig. 6), the barrier metal layers 38a and 41a are Ti layers. Ti atoms diffuse more easily than Ta atoms. Therefore, in this embodiment, the metal layer 61 is formed between the metal pad 38 and the interlayer insulating film 13 and between the metal pad 41 and the interlayer insulating film 14. Therefore, according to the present embodiment, even if the metal pad 41 is not disposed directly above the metal pad 38, the interlayer insulating films 14 and 13 include the insulating films 14e and 13e (SiO) by natural oxidation or the like2Film), diffusion of Cu atoms from the metal pads 38, 41 into the interlayer insulating films 14, 13 can be suppressed by the metal layer 61. The Ti atoms that cause the metal layer 61 to diffuse are generated, for example, in an annealing step in the manufacture of a semiconductor device.
For using a Ti layer as the barrier metal layer 38a, 41a, TiO is presentxThe barrier property of the layer (metal layer 61) is high, and the cost for forming the Ti layer can be reduced. It should be noted that such a blocking effect is obtained when an Al layer is used to form AlOxIn the case of a layer, MnO is formed using a Mn layerxLayers can also be obtained.
The structure in which the metal pad 41 of the present embodiment is not provided directly above the metal pad 38 may be caused by an error in the alignment between the metal pad 38 and the metal pad 41, or may be intentionally generated when manufacturing a semiconductor device.
Fig. 7 to 11 are sectional views showing a method for manufacturing a semiconductor device according to embodiment 1. The methods shown in fig. 7 to 11 correspond to specific examples of the methods shown in fig. 3 and 4.
First, the array wafer W1 and the circuit wafer W2 were processed into the structure shown in FIG. 7. Specifically, an insulating film 13a is formed above the substrate 16 (see fig. 3), a via plug 42 is formed in the insulating film 13a, insulating films 13b, 13c, and 13d are sequentially formed on the insulating film 13a and the via plug 42, and a barrier metal layer 41a and a spacer layer 41b are sequentially formed in the insulating films 13b, 13c, and 13 d. Similarly, an insulating film 14a is formed above the substrate 15 (see fig. 3), a via plug 37 is formed in the insulating film 14a, insulating films 14b, 14c, and 14d are sequentially formed on the insulating film 14a and the via plug 37, and a barrier metal layer 38a and a spacer layer 38b are sequentially formed in the insulating films 14b, 14c, and 14 d. As a result, the metal pads 41 and 38 are formed in the interlayer insulating films 13 and 14, respectively.
Next, on the surfaces of the insulating films 13d and 14d, insulating films 13e and 14e are formed by oxidation, respectively (fig. 8). The insulating films 13e and 14e are formed by, for example, natural oxidation.
Next, the array wafer W1 and the circuit wafer W2 were bonded to each other by mechanical pressure so that the metal pad 41 was disposed on the metal pad 38 and the interlayer insulating film 13 was disposed on the interlayer insulating film 14 (fig. 9). Thereby, the interlayer insulating film 13 and the interlayer insulating film 14 are bonded. In fig. 9, an error occurs in the alignment between the metal pad 38 and the metal pad 41, and a part of the upper surface of the metal pad 38 is in contact with a part of the lower surface of the metal pad 41.
Subsequently, the array wafer W1 and the circuit wafer W2 were annealed (fig. 10). Thereby, the metal pad 41 and the metal pad 38 are bonded. Fig. 10 further shows grain boundaries α between grains in the spacer layers 38b and 41b, and a Ti atom group β diffused along the grain boundaries α or the bonding surface S. In the present embodiment, Ti atoms are diffused from the barrier metal layers 38a, 41a by annealing in the step shown in fig. 10.
As a result, Ti atoms in the barrier metal layers 38a and 41a diffuse into the interface between the spacer layer 38b and the insulating film 13e and the interface between the spacer layer 41b and the insulating film 14e, and a metal layer 61 is formed at the position of these interfaces in a self-aligned manner (fig. 11). Specifically, Ti atoms diffused from the barrier metal layers 38a and 41a into the interfaces react with O atoms in the insulating films 14e and 13e to form TiOxThe layer serves as a metal layer 61. Thus, according to the present embodiment, Cu atoms can be suppressed from being removed by the metal layer 61Diffusion of the metal pads 38, 41 into the interlayer insulating films 14, 13.
In this manner, the semiconductor device of fig. 6 is manufactured. Thereafter, the substrate 15 is thinned by CMP, the substrate 16 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor device of fig. 1 is manufactured.
As described above, the semiconductor device of the present embodiment includes the metal layer 61 containing the same metal element as the metal element contained in the barrier metal layers 38a and 41a between the upper surface of the metal spacer 38 and the lower surface of the interlayer insulating film 13 and between the lower surface of the metal spacer 41 and the upper surface of the interlayer insulating film 14. Therefore, according to the present embodiment, it is possible to form the metal pads 38 and 41 suitable for suppressing diffusion of metal atoms (for example, Cu atoms) from the pad layers 38b and 41b to the insulating films 14e and 13 e.
(embodiment 2)
Fig. 12 is a sectional view showing the structure of the semiconductor device according to embodiment 2.
The interlayer insulating films 13 and 14 of the present embodiment do not include the insulating films 13d and 14d (SiCN film), and as a result, do not include the insulating films 13e and 14e (SiO film)2A film). In this embodiment, the insulating film 13c (SiO) in the interlayer insulating film 132Film) and insulating film 14c (SiO) in interlayer insulating film 142Films) are in contact with each other at the bonding surface S.
The semiconductor device of the present embodiment also includes a metal layer 61. The metal layer 61 of the present embodiment is formed by reacting Ti atoms diffused from the barrier metal layers 38a and 41a with O atoms in the insulating films 14c and 13 c.
According to this embodiment, the time and effort for forming the insulating films 13d and 14d can be omitted. In addition, according to this embodiment, since the insulating films 13d and 14d do not exist in the vicinity of the surfaces of the interlayer insulating films 13 and 14, the surfaces of the interlayer insulating films 13 and 14 can be easily planarized by CMP. On the other hand, according to embodiment 1, diffusion of Cu atoms can be suppressed not only by the metal layer 61 but also by the insulating films 13d and 14 d.
Fig. 13 to 16 are sectional views showing a method for manufacturing a semiconductor device according to embodiment 2. The method shown in fig. 13 to 16 corresponds to a specific example of the method shown in fig. 3 and 4.
First, the array wafer W1 and the circuit wafer W2 were processed into the structure shown in FIG. 13. Specifically, an insulating film 13a is formed above the substrate 16 (see fig. 3), a via plug 42 is formed in the insulating film 13a, insulating films 13b and 13c are sequentially formed on the insulating film 13a and the via plug 42, and a barrier metal layer 41a and a spacer layer 41b are sequentially formed in the insulating films 13b and 13 c. Similarly, an insulating film 14a is formed above the substrate 15 (see fig. 3), a via plug 37 is formed in the insulating film 14a, insulating films 14b and 14c are sequentially formed on the insulating film 14a and the via plug 37, and a barrier metal layer 38a and a spacer layer 38b are sequentially formed in the insulating films 14b and 14 c. As a result, the metal pads 41 and 38 are formed in the interlayer insulating films 13 and 14, respectively.
Next, the array wafer W1 and the circuit wafer W2 were bonded together by mechanical pressure so that the metal pad 41 was disposed on the metal pad 38 and the interlayer insulating film 13 was disposed on the interlayer insulating film 14 (fig. 14). Thereby, the interlayer insulating film 13 and the interlayer insulating film 14 are bonded. In fig. 14, an error occurs in the alignment between the metal pad 38 and the metal pad 41, and a part of the upper surface of the metal pad 38 is in contact with a part of the lower surface of the metal pad 41.
Subsequently, the array wafer W1 and the circuit wafer W2 were annealed (fig. 15). Thereby, the metal pad 41 and the metal pad 38 are bonded. Fig. 15 further shows grain boundaries α between grains in the spacer layers 38b and 41b, and a Ti atom group β diffused along the grain boundaries α or the bonding surface S. In the present embodiment, Ti atoms are diffused from the barrier metal layers 38a, 41a by annealing in the step shown in fig. 15.
As a result, Ti atoms in the barrier metal layers 38a and 41a diffuse to the interface between the spacer layer 38b and the insulating film 13c and the interface between the spacer layer 41b and the insulating film 14c, and the metal layer 61 is formed at the position of these interfaces in a self-aligned manner (fig. 16). Specifically, the diffusion from the barrier metal layers 38a and 41a to these interfacesThe Ti atoms in (2) react with O atoms in the insulating films (14 c, 13 c) to form TiOxThe layer serves as a metal layer 61. Therefore, according to the present embodiment, diffusion of Cu atoms from the metal pads 38 and 41 into the interlayer insulating films 14 and 13 can be suppressed by the metal layer 61.
In this manner, the semiconductor device of fig. 12 is manufactured. Thereafter, the substrate 15 is thinned by CMP, the substrate 16 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor device of fig. 1 is manufactured.
As described above, the semiconductor device of the present embodiment includes the metal layer 61 containing the same metal element as the metal element contained in the barrier metal layers 38a and 41a between the upper surface of the metal spacer 38 and the lower surface of the interlayer insulating film 13 and between the lower surface of the metal spacer 41 and the upper surface of the interlayer insulating film 14. Therefore, according to the present embodiment, it becomes possible to form the metal pads 38 and 41 suitable for suppressing diffusion of metal atoms (for example, Cu atoms) from the pad layers 38b and 41b to the insulating films 14c and 13 c.
(embodiment 3)
Fig. 17 is a sectional view showing the structure of the semiconductor device according to embodiment 3.
The interlayer insulating film 13 of the present embodiment does not include the insulating film 13d (SiCN film), and as a result, does not include the insulating film 13e (SiO film)2A film). On the other hand, the interlayer insulating film 14 of the present embodiment includes an insulating film 14d (SiCN film), and as a result, also includes an insulating film 14e (SiO film)2A film). In this embodiment, the insulating film 13c (SiO) in the interlayer insulating film 132Film) and insulating film 14e (SiO) in interlayer insulating film 142Films) are in contact with each other at the bonding surface S.
The semiconductor device of the present embodiment also includes a metal layer 61. The metal layer 61 of the present embodiment is formed by reacting Ti atoms diffused from the barrier metal layers 38a and 41a with O atoms in the insulating films 14e and 13 c.
According to this embodiment, the same advantages as those of embodiment 1 can be obtained with respect to the interlayer insulating film 14, and the same advantages as those of embodiment 2 can be obtained with respect to the interlayer insulating film 13. The semiconductor device of the present embodiment can be manufactured by applying the method shown in fig. 13 to 16 to the array wafer W1 and the method shown in fig. 7 to 11 to the circuit wafer W2, for example.
In the semiconductor device of the present embodiment, the interlayer insulating film 13 may include the insulating films 13d and 13e, and the interlayer insulating film 14 may not include the insulating films 14d and 14 e.
(embodiment 4)
Fig. 18 is a sectional view showing the structure of the semiconductor device according to embodiment 4.
While the metal pad 38 and the via plug 37 of embodiments 1 to 3 are single damascene wires, the metal pad 38 and the via plug 37 of the present embodiment are dual damascene wires. Therefore, the barrier metal layer 37a and the plug material layer 37b in the through-hole plug 37 of the present embodiment are the same as the barrier metal layer 38a and the plug material layer 38b in the metal spacer 38, respectively, and the plug material layer 37b in the through-hole plug 37 is in contact with the spacer material layer 38b in the metal spacer 38. In other words, the barrier metal layers 38a and 37b are not provided at the boundary surface between the spacer layer 38b and the plug layer 37 b. The barrier metal layer 38a and the barrier metal layer 37b are examples of the 1 st layer, and the spacer layer 38b and the plug material layer 37b are examples of the 2 nd layer.
Similarly, while the metal pad 41 and the via plug 42 of embodiments 1 to 3 are single damascene wirings, the metal pad 41 and the via plug 42 of the present embodiment are dual damascene wirings. Therefore, the barrier metal layer 42a and the plug material layer 42b in the via plug 42 of the present embodiment are the same as the barrier metal layer 41a and the spacer material layer 41b in the metal spacer 41, respectively, and the plug material layer 42b in the via plug 42 is in contact with the spacer material layer 41b in the metal spacer 41. In other words, the barrier metal layers 41a and 42b are not provided on the boundary surface between the spacer layer 41b and the plug layer 42 b. The barrier metal layer 41a and the barrier metal layer 42b are examples of the 3 rd layer, and the spacer layer 41b and the plug layer 42b are examples of the 4 th layer.
According to the present embodiment, the metal pad 38 and the via plug 37 can be formed in a small number of steps, and the metal pad 41 and the via plug 42 can be formed in a small number of steps. The semiconductor device of this embodiment can be manufactured by using a dual damascene method instead of a single damascene method in the step of fig. 7 when the methods shown in fig. 7 to 11 are applied, for example.
(embodiment 5)
Fig. 19 is a sectional view showing the structure of the semiconductor device according to embodiment 5.
The metal pad 38 of the present embodiment has a different planar shape from the metal pad 41. The planar shapes of the metal pad 38 and the metal pad 41 in the present embodiment are both square or rectangular, but the width of the metal pad 41 in the X direction is different from the width of the metal pad 38 in the X direction, and the width of the metal pad 41 in the Y direction is different from the width of the metal pad 38 in the Y direction. For example, the width of the metal pad 41 in the X direction is shorter than the width of the metal pad 38 in the X direction, the width of the metal pad 41 in the Y direction is shorter than the width of the metal pad 38 in the Y direction, and the entire lower surface of the metal pad 41 is in contact with a part of the upper surface of the metal pad 38.
The semiconductor device of the present embodiment also includes a metal layer 61. The metal layer 61 of the present embodiment is formed by the reaction of Ti atoms diffused from the barrier metal layers 38a and 41a with O atoms in the insulating film 13 e.
In embodiments 1 to 4, if an error occurs in the alignment between the metal pad 38 and the metal pad 41, the contact area between the metal pad 38 and the metal pad 41 changes, and the contact resistance between the metal pad 38 and the metal pad 41 changes. On the other hand, in the present embodiment, even if a small error occurs in the alignment of the metal pad 38 and the metal pad 41, the contact area between the metal pad 38 and the metal pad 41 does not change, and the contact resistance between the metal pad 38 and the metal pad 41 does not change. Therefore, according to the present embodiment, it is possible to suppress the problem caused by the error in the alignment between the metal pad 38 and the metal pad 41.
Since the metal pad 38 and the metal pad 41 of the present embodiment have different planar shapes, even if an error in the alignment between the metal pad 38 and the metal pad 41 does not occur, a portion where the upper surface of the metal pad 38 is positioned below the lower surface of the interlayer insulating film 13 or a portion where the lower surface of the metal pad 41 is positioned above the upper surface of the interlayer insulating film 14 may occur. In the present embodiment, the metal layer 61 can be formed in such a portion. Thus, according to the present embodiment, it is possible to enjoy the advantage of the case where the metal pad 38 and the metal pad 41 have different planar shapes, and it is possible to suppress the disadvantage of the case where the metal pad 38 and the metal pad 41 have different planar shapes.
The semiconductor device of the present embodiment can be manufactured by, for example, applying the method shown in fig. 7 to 11, by making the planar shape of the metal pad 38 different from the planar shape of the metal pad 41 in the step of fig. 7. In this embodiment, a single damascene may be used instead of the dual damascene method.
(embodiment 6)
Fig. 20 is a sectional view showing the structure of the semiconductor device according to embodiment 6.
The semiconductor device of the present embodiment includes not only the metal pads 38 and 41 (see fig. 1 and the like) that are in contact with each other, but also the metal pads 38 and 41 that are not in contact with each other as shown in fig. 20. Such metal pads 38 and 41 are formed as dummy pads that are not used to electrically connect the array wafer W1 and the circuit wafer W2, for example. The dummy pads are formed, for example, to adjust the density of the metal pads 38 and 41 on the bonding surface S.
The semiconductor device of the present embodiment also includes a metal layer 61. The metal layer 61 on the metal pad 38 of the present embodiment is formed by reacting mainly Ti atoms diffused from the barrier metal layer 38a with O atoms in the insulating film 13 e. On the other hand, the metal layer 61 under the metal spacer 41 of the present embodiment is formed by the reaction of Ti atoms diffused from the barrier metal layer 41a mainly with O atoms in the insulating film 14 e.
The semiconductor device of the present embodiment can be manufactured by, for example, bonding the array wafer W1 and the circuit wafer W2 so that the metal pad 38 and the metal pad 41 do not contact each other as shown in fig. 20 in the step of fig. 9 when the method shown in fig. 7 to 11 is applied.
Although several embodiments have been described above, these embodiments are merely provided as examples and are not intended to limit the scope of the present invention. The novel apparatus and methods described herein may be embodied in other specific forms. The embodiments of the apparatus and method described in the present specification may be variously omitted, replaced, or modified without departing from the spirit of the present invention. The appended claims and their equivalents are intended to cover such modifications and variations as fall within the true scope and spirit of the invention.

Claims (15)

1. A semiconductor device includes:
1 st insulating film;
a 1 st pad which is a 1 st pad provided within the 1 st insulating film, the 1 st pad including a 1 st layer provided on a side surface and a lower surface of the 1 st insulating film and a 2 nd layer provided on a side surface and a lower surface of the 1 st insulating film via the 1 st layer;
a 2 nd insulating film, the 2 nd insulating film being provided on the 1 st insulating film;
a 2 nd spacer which is a 2 nd spacer provided on the 1 st spacer within the 2 nd insulating film and includes a 3 rd layer provided on a side surface and an upper surface of the 2 nd insulating film and a 4 th layer provided on a side surface and an upper surface of the 2 nd insulating film via the 3 rd layer; and
and a portion 1, provided between an upper surface of the 1 st pad and a lower surface of the 2 nd insulating film or between a lower surface of the 2 nd pad and an upper surface of the 1 st insulating film, containing a metal element that is the same as a metal element contained in the 1 st layer or the 3 rd layer.
2. The semiconductor device according to claim 1, wherein the part 1 contains the metal element and oxygen.
3. The semiconductor device according to claim 1 or 2, wherein the metal element comprises titanium, aluminum, or manganese.
4. The semiconductor device according to claim 1 or 2, wherein the 1 st layer is in contact with a side surface and a lower surface of the 1 st insulating film, or
The 3 rd layer is in contact with the side surface and the upper surface of the 2 nd insulating film.
5. The semiconductor device according to claim 1 or 2, wherein the 1 st insulating film comprises a 1 st film containing oxygen and contacting a lower surface of the 1 st portion, or
The 2 nd insulating film includes a 2 nd film containing oxygen and contacting an upper surface of the 1 st portion.
6. The semiconductor device according to claim 5, wherein the 1 st film or the 2 nd film is a natural oxide film.
7. The semiconductor device according to claim 5, wherein the 1 st insulating film comprises the 1 st film and a 3 rd film containing carbon and nitrogen and contacting a lower surface of the 1 st film, or
The 2 nd insulating film includes the 2 nd film and a 4 th film containing carbon and nitrogen and contacting an upper surface of the 2 nd film.
8. The semiconductor device according to claim 1 or 2, wherein the 1 st pad and the 2 nd pad have the same width.
9. The semiconductor device according to claim 1 or 2, wherein the 1 st pad and the 2 nd pad have different widths.
10. The semiconductor device according to claim 1 or 2, wherein the 1 st pad is provided on a 1 st plug including the 1 st layer and the 2 nd layer, and the 2 nd layer in the 1 st plug is in contact with the 2 nd layer in the 1 st pad, or
The 2 nd pad is disposed under a 2 nd plug comprising the 3 rd layer and the 4 th layer, the 4 th layer in the 2 nd plug being contiguous with the 4 th layer in the 2 nd pad.
11. A semiconductor device includes:
1 st insulating film;
a 1 st pad which is a 1 st pad provided within the 1 st insulating film, the 1 st pad including a 1 st layer provided on a side surface and a lower surface of the 1 st insulating film, and a 2 nd layer provided on a side surface and a lower surface of the 1 st insulating film via the 1 st layer;
a 2 nd insulating film, the 2 nd insulating film being provided on the 1 st insulating film;
a 2 nd spacer which is a 2 nd spacer provided in a position not in contact with the 1 st spacer within the 2 nd insulating film, and includes a 3 rd layer provided on a side surface and an upper surface of the 2 nd insulating film and a 4 th layer provided on a side surface and an upper surface of the 2 nd insulating film via the 3 rd layer; and
and a portion 1, provided between an upper surface of the 1 st pad and a lower surface of the 2 nd insulating film or between a lower surface of the 2 nd pad and an upper surface of the 1 st insulating film, containing a metal element that is the same as a metal element contained in the 1 st layer or the 3 rd layer.
12. The semiconductor device according to claim 11, wherein the part 1 contains the metal element and oxygen.
13. The semiconductor device according to claim 11 or 12, wherein the metal element comprises titanium, aluminum, or manganese.
14. A method of manufacturing a semiconductor device, comprising:
forming a 1 st pad in a 1 st insulating film, the 1 st pad including a 1 st layer provided on a side surface and a bottom surface of the 1 st insulating film and a 2 nd layer provided on a side surface and a bottom surface of the 1 st insulating film via the 1 st layer;
forming a 2 nd spacer in a 2 nd insulating film, the 2 nd spacer including a 3 rd layer provided on a side surface and a bottom surface of the 2 nd insulating film and a 4 th layer provided on a side surface and a bottom surface of the 2 nd insulating film via the 3 rd layer;
disposing the 2 nd insulating film on the 1 st insulating film, and disposing the 2 nd pad on the 1 st pad; and
forming a 1 st portion between an upper surface of the 1 st pad and a lower surface of the 2 nd insulating film, or between a lower surface of the 2 nd pad and an upper surface of the 1 st insulating film, the 1 st portion including a metal element that is the same as a metal element included in the 1 st layer or the 3 rd layer.
15. The method for manufacturing a semiconductor device according to claim 14, wherein the 1 st portion is formed by the metal element diffused from the 1 st layer or the 3 rd layer.
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