CN113380757B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113380757B
CN113380757B CN202010758379.8A CN202010758379A CN113380757B CN 113380757 B CN113380757 B CN 113380757B CN 202010758379 A CN202010758379 A CN 202010758379A CN 113380757 B CN113380757 B CN 113380757B
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layer
wiring
semiconductor device
metal
film
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CN113380757A (zh
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加藤敦史
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Kioxia Corp
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Kioxia Corp
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    • H01L23/5226—Via connections in a multilevel interconnection structure
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Abstract

根据一实施方式，半导体装置具备第1衬底、逻辑电路、第1绝缘膜、配线、插塞、及包含金属氧化物或金属氮化物的第1层。逻辑电路设置在第1衬底上。第1绝缘膜设置在逻辑电路的上方。配线设置在第1绝缘膜内，在沿着第1衬底的上表面的第1方向延伸，且具有含有金属的第1膜及介隔第1膜配置在第1绝缘膜内的第1金属层。插塞设置在配线下，在与第1方向交叉的第2方向延伸，且与配线电连接。第1层设置在插塞的上端与配线的下端之间。

Description

半导体装置
相关申请案的引用
本申请案基于2020年02月25日提出申请的在先日本专利申请案第2020-029592号的优先权而主张优先权利益，通过引用将其全部内容并入本文中。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
当在配线上形成通孔插塞时，存在配线的材料与通孔插塞的材料容易发生反应的情况。在该情况下，必须抑制配线的材料与通孔插塞的材料的反应。
发明内容
一实施方式提供一种能够抑制配线与插塞的反应的半导体装置。
根据一实施方式，半导体装置具备第1衬底、逻辑电路、第1绝缘膜、配线、插塞、及第1层。逻辑电路设置在第1衬底上。第1绝缘膜设置在逻辑电路的上方。配线设置在第1绝缘膜内，在沿着第1衬底的上表面的第1方向延伸，且具有含有金属的第1膜及介隔第1膜配置在第1绝缘膜内的第1金属层。插塞设置在配线下，在与第1方向交叉的第2方向延伸，且与配线电连接。第1层包含金属氧化物或金属氮化物，设置在插塞的上端与配线的下端之间。
根据所述构成，可提供一种能够抑制配线与插塞的反应的半导体装置。
附图说明
图1A是表示第1实施方式的半导体装置的构造的第1例的剖视图。
图1B是表示第1实施方式的半导体装置的构造的第2例的剖视图。
图2是表示图1A及图1B所示的半导体装置的制造方法的剖视图。
图3是表示继图2之后的图1A及图1B所示的半导体装置的制造方法的剖视图。
图4A是表示继图3之后的图1A所示的半导体装置的制造方法的剖视图。
图4B是表示继图3之后的图1B所示的半导体装置的制造方法的剖视图。
图5A是表示继图4A之后的图1A所示的半导体装置的制造方法的剖视图。
图5B是表示继图4B之后的图1B所示的半导体装置的制造方法的剖视图。
图6A是表示继图5A之后的图1A所示的半导体装置的制造方法的剖视图。
图6B是表示继图5B之后的图1B所示的半导体装置的制造方法的剖视图。
图7A是表示继图6A之后的图1A所示的半导体装置的制造方法的剖视图。
图7B是表示继图6B之后的图1B所示的半导体装置的制造方法的剖视图。
图8A是表示继图7A之后的图1A所示的半导体装置的制造方法的剖视图。
图8B是表示继图7B之后的图1B所示的半导体装置的制造方法的剖视图。
图9A是表示第2实施方式的半导体装置的构造的第1例的剖视图。
图9B是表示第2实施方式的半导体装置的构造的第2例的剖视图。
图10是表示第3实施方式的半导体装置的构造的剖视图。
图11是表示第3实施方式的半导体装置中的柱状部的构造的剖视图。
图12是表示第3实施方式的半导体装置的制造方法的剖视图。
图13A是表示第3实施方式的半导体装置的构造的第1例的剖视图。
图13B是表示第3实施方式的半导体装置的构造的第2例的剖视图。
图14A是表示第3实施方式的半导体装置的构造的第3例的剖视图。
图14B是表示第3实施方式的半导体装置的构造的第4例的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。在图1A至图14B中，对相同或类似的构成标注相同的符号，并省略重复的说明。
(第1实施方式)
图1A是表示第1实施方式的半导体装置的构造的第1例的剖视图。图1B是表示第1实施方式的半导体装置的构造的第2例的剖视图。第1实施方式的半导体装置如图1A或图1B所示，具备衬底1、作为第1绝缘膜的一例的第1层间绝缘膜2、多条配线3、作为第2绝缘膜的一例的第2层间绝缘膜4及第3层间绝缘膜5、作为插塞的一例的通孔插塞7、作为第2金属层的一例的金属层6、以及作为包含金属氧化物或金属氮化物的第1层的一例的金属氧化层81。
图1A表示在配线3上不发生位置偏移地形成通孔插塞7的情况下的半导体装置，图1B表示在配线3上发生位置偏移地形成通孔插塞7的情况下的半导体装置。以下，参照图1A，对第1实施方式的半导体装置的构造进行说明。在该说明之中，也适当参照图1B。
衬底1例如为硅(Si)衬底等半导体衬底。图1A表示了与衬底1的表面平行且相互垂直的X方向及Y方向、以及与衬底1的表面垂直的Z方向。在本说明书中，将+Z方向作为上方向处理，将-Z方向作为下方向处理。-Z方向既可以与重力方向一致，也可以不与重力方向一致。Y方向是沿着下述第1衬底(衬底15)的上表面的第1方向的一例。Z方向是与第1方向交叉的第2方向的一例。
第1层间绝缘膜2形成在衬底1上。第1层间绝缘膜2例如为氧化硅膜(SiO2膜)。第1层间绝缘膜2既可以直接形成在衬底1上，也可以介隔其它层形成在衬底1上。
多条配线3包含于设置在衬底1上方的相同配线层内，且形成在第1层间绝缘膜2内。作为一例，图1A表示了2条配线3。这些配线3在Y方向延伸，且在X方向相互隔开间隔地排列。多条配线3具有：第1阻挡金属膜3a，作为含有金属之第1膜的一例；以及配线金属层3b，作为第1金属层的一例，介隔第1阻挡金属膜3a配置在第1层间绝缘膜2内。配线金属层3b例如为含有铜(Cu)的金属层。第1阻挡金属膜3a是为了防止配线金属层3b含有的成分(例如，铜)向第1层间绝缘膜2内扩散而设置的。第1阻挡金属膜3a例如含有钛(Ti)。配线3能够通过如下方法形成：在第1层间绝缘膜2形成在Y方向延伸且在X方向相互隔开间隔排列的多个开口部，在所形成的多个开口部内介隔第1阻挡金属膜3a配置配线金属层3b。配线3并不限定于图1A的形态，例如，也可以为金属焊垫(Cu焊垫)、接触插塞或通孔插塞等金属插塞(Cu插塞)。
金属层6形成在配线3上。在图1A所示的例子中，金属层6形成在通孔插塞7下的配线3的配线金属层3b上。更详细来说，金属层6在下方与配线金属层3b相邻，在侧方与第1阻挡金属膜3a相邻。金属层6含有第1阻挡金属膜3a中所含有的成分(例如，钛)。金属层6例如能够通过如下方法形成：在形成配线3与第2及第3层间绝缘膜4、5之后，为了形成通孔插塞7而在第2及第3层间绝缘膜4、5内形成通孔，然后，在包含氮(N2)、氢(H2)及氩(Ar)中的任一者的环境下使第1阻挡金属膜3a退火。更具体来说，通过使第1阻挡金属膜3a退火，从而第1阻挡金属膜3a中所含有的成分(例如，钛)向配线金属层3b的上端部扩散，而形成包含扩散的成分的金属层6。如图1A所示，具有金属层6的配线3的第1阻挡金属膜3a的下部相比不具有金属层6的配线3的第1阻挡金属膜3a的下部来说，厚度变薄。
另一方面，在图1B中，为了形成通孔插塞7而在第2及第3层间绝缘膜4、5内形成通孔时，通孔相对于左侧的配线3发生了位置偏移。因此，仅左侧的配线3的右上端相对于通孔露出而曝露在包含氮、氢或氩的环境中。在该情况下，如图1B所示，在相对于通孔露出的配线3的右上端侧，第1阻挡金属膜3a中所含有的成分的扩散被局部地促进，从而金属层6的厚度变厚，另一方面，越朝向由第2层间绝缘膜4覆盖的配线3的左上端侧则金属层6的厚度变得越薄。
金属氧化层81为了抑制配线3与通孔插塞7的反应而形成在通孔插塞7下的配线3上。在图1A所示的例子中，金属氧化层81形成在金属层6上。更详细来说，金属氧化层81在下方与金属层6相邻，在侧方与第1阻挡金属膜3a相邻。另外，在图1A所示的例子中，金属氧化层81上端的位置在Z方向上与第1阻挡金属膜3a上端的位置及第1层间绝缘膜2上端的位置一致。金属氧化层81含有金属层6中所含有的成分(例如，钛)的氧化物，例如，含有氧化钛(TiOx)。这种金属氧化层81例如能够通过如下方法形成：在形成金属层6之后，通过在包含氧的环境下实施退火而将金属层6氧化。在通过氧化将金属层6的几乎全部置换为金属氧化层81的情况下，金属氧化层81也可以在下方不介隔金属层6而与配线金属层3b直接相邻。另外，金属氧化层81也可以通过不依赖于金属层6的反应(氧化等)而相对于金属层6独立的成膜工艺形成在配线3上。
另一方面，如图1B所示，在由于通孔的位置偏移导致仅配线3的右上端相对于通孔露出而曝露在氧环境中的情况下，在配线3的右上端侧，金属层6的氧化被局部地促进，从而金属氧化层81的厚度变厚，另一方面，越朝向由第2层间绝缘膜4覆盖的配线3的左上端侧则金属氧化层81的厚度变得越薄。
第2层间绝缘膜4及第3层间绝缘膜5依次形成在第1层间绝缘膜2上或配线3上。第2层间绝缘膜4例如为碳氮化硅膜(SiCN膜)。第3层间绝缘膜5例如为氧化硅膜。
通孔插塞7在第2及第3层间绝缘膜4、5内，形成在任一条配线3上。在图1A所示的例子中，通孔插塞7形成在形成着金属氧化层81的配线3上。通孔插塞7的下端与金属氧化层81相接。换句话说，金属氧化层81形成在通孔插塞7的下端与配线3的上端之间。此外，如已经叙述的那样，有时在金属氧化层81与配线3的上端之间形成金属层6。图1A表示了形成在左侧的配线3上的通孔插塞7。在图1A所示的例子中，通孔插塞7在左侧的配线3上沿Z方向延伸。通孔插塞7例如具有作为金属氮化膜的一例的第2阻挡金属膜7a、及作为第3金属层的一例的插塞金属层7b。第2阻挡金属膜7a例如为含有氮化钛(TiN)或氮化钨(WN)的阻挡金属膜。插塞金属层7b例如为含有钨(W)的W插塞材层。通孔插塞7能够通过如下方法获得：在第2及第3层间绝缘膜4、5内，形成到达至形成着金属氧化层81的配线3的通孔，在通孔内依次形成第2阻挡金属膜7a及插塞金属层7b。
另一方面，在图1B中，当在第2及第3层间绝缘膜4、5内形成通孔时，通孔相对于左侧的配线3发生了位置偏移。因此，第2阻挡金属膜7a也形成在左侧的配线3的侧面。结果，插塞金属层7b介隔第2阻挡金属膜7a形成在第2及第3层间绝缘膜4、5的侧面或第1层间绝缘膜2的表面，另外，介隔第2阻挡金属膜7a形成在左侧的配线3的上表面及侧面。第1实施方式的半导体装置可具有图1A所示的构造及图1B所示的构造中的任一构造。
第1实施方式的半导体装置可设为任何半导体装置，例如也可以设为三维半导体存储器。在该情况下，三维半导体存储器可将包含存储单元阵列的阵列芯片与包含CMOS(complementary metal oxide semiconductor，互补金属氧化物半导体)电路的电路芯片贴合而形成。另外，图1A或图1B的配线3与通孔插塞7既可以设置在阵列芯片内，也可以设置在电路芯片内。另外，第1实施方式的半导体装置也可以不具备衬底1。在下述第3实施方式中说明这种半导体装置的例子。
(制造方法)
接下来，参照图2至图8B，对以如上方式构成的第1实施方式的半导体装置的制造方法进行说明。
图2是表示图1A及图1B所示的半导体装置的制造方法的剖视图。首先，如图2所示，在衬底1上形成第1层间绝缘膜2，然后，在第1层间绝缘膜2，形成在X方向相互隔开间隔且在Y方向延伸的多个开口部O。开口部O为第1开口部的一例。多个开口部O例如利用光刻技术而形成。
图3是表示继图2之后的图1A及图1B所示的半导体装置的制造方法的剖视图。当在第1层间绝缘膜2形成多个开口部O之后，如图3所示，在多个开口部O内介隔第1阻挡金属膜3a形成配线金属层3b，由此形成多条配线3。第1阻挡金属膜3a例如通过溅镀而形成。配线金属层3b例如利用镀铜工艺而形成。配线金属层3b例如也可以当通过溅镀在第1阻挡金属膜3a上形成Cu晶种层之后介隔Cu晶种层形成在第1阻挡金属膜3a上。
图4A是表示继图3之后的图1A所示的半导体装置的制造方法的剖视图。图4B是表示继图3之后的图1B所示的半导体装置的制造方法的剖视图。在形成多条配线3之后，如图4A所示，在第1层间绝缘膜2上及多条配线3上依次形成第2层间绝缘膜4与第3层间绝缘膜5。在形成第2层间绝缘膜4及第3层间绝缘膜5之后，如图4A所示，在第2及第3层间绝缘膜4、5内，形成到达至任一配线3(也就是形成金属氧化层81的预定配线3)的通孔H。通孔H为第2开口部的一例。形成通孔H的结果为配线3的上表面在通孔H内露出。通孔H例如利用光刻技术而形成。在图4B中，通孔H相对于配线3发生了位置偏移，配线3的上表面及侧面在通孔H内露出。
图5A是表示继图4A之后的图1A所示的半导体装置的制造方法的剖视图。图5B是表示继图4B之后的图1B所示的半导体装置的制造方法的剖视图。在形成通孔H之后，如图5A所示，在因通孔H而露出的配线3的上端，形成含有第1阻挡金属膜3a中所含有的成分(例如，钛)的金属层6。金属层6例如通过如下方法而形成：在包含氮、氢及氩中的任一者的环境下使第1阻挡金属膜3a退火，通过退火使第1阻挡金属膜3a中所含有的成分(例如，钛)向配线3也就是配线金属层3b的上端以特定深度扩散。在图5B中，由于通孔H相对于配线3发生了位置偏移，所以在露出到通孔H内的配线3的右上端侧金属层6的厚度变厚，越朝向配线3的左上端侧则金属层6的厚度变得越薄。
图6A是表示继图5A之后的图1A所示的半导体装置的制造方法的剖视图。图6B是表示继图5B之后的图1B所示的半导体装置的制造方法的剖视图。在形成金属层6之后，如图6A所示，通过将金属层6氧化而在配线3上形成金属氧化层81。通过利用金属层6的氧化形成金属氧化层81，能够抑制形成金属氧化层81所需要的步骤数。通过在包含氧的环境下使金属层6退火来进行金属层6的氧化。在图6B中，由于通孔H相对于配线3发生了位置偏移，所以在露出到通孔H内的配线3的右上端侧金属氧化层81的厚度变厚，越朝向配线3的左上端侧则金属氧化层81的厚度变得越薄。
图7A是表示继图6A之后的图1A所示的半导体装置的制造方法的剖视图。图7B是表示继图6B之后的图1B所示的半导体装置的制造方法的剖视图。在形成金属氧化层81之后，如图7A所示，在通孔H内及第3层间绝缘膜5上形成第2阻挡金属膜7a。在第2阻挡金属膜7a含有氮化钛的情况下，第2阻挡金属膜7a通过使用含有氯的材料气体的热CVD(ChemicalVapor Deposition，化学气相沉积)法或等离子体CVD法而形成。含有氯的材料气体例如为包含四氯化钛(TiCl4)的气体。在第2阻挡金属膜7a含有氮化钨的情况下，第2阻挡金属膜7a通过使用含有氟的材料气体的热CVD法或等离子体CVD法而形成。在图7B中，第2阻挡金属膜7a也形成在配线3的侧面。
图8A是表示继图7A之后的图1A所示的半导体装置的制造方法的剖视图。图8B是表示继图7B之后的图1B所示的半导体装置的制造方法的剖视图。在形成第2阻挡金属膜7a之后，如图8A所示，在第2阻挡金属膜7a上形成插塞金属层7b。插塞金属层7b例如利用CVD法而形成。在图8B中，插塞金属层7b也介隔第2阻挡金属膜7a形成在配线3的侧面。
在形成插塞金属层7b之后，使插塞金属层7b的表面平坦化，由此将通孔H外的插塞金属层7b及第2阻挡金属膜7a去除，而在通孔H内形成通孔插塞7(图1A、图1B)。通孔插塞7通过以与配线3相接的方式形成，而电连接于配线3。插塞金属层7b的平坦化例如通过CMP(Chemical Mechanical Polishing，化学机械抛光)进行。然后，在衬底1上形成各种层间绝缘膜、配线层、插塞金属层等。这样一来，制造本实施方式的半导体装置。
此处，如果在配线3上未形成金属氧化层81，那么在使用含有氯或氟的材料气体成膜第2阻挡金属膜7a时，残留氯或残留氟会与第1阻挡金属膜3a中所含有的成分(例如，钛)发生反应而使第1阻挡金属膜3a与配线金属层3b的密接性降低，从而导致配线金属层3b移动。因配线金属层3b移动，而导致在第1阻挡金属膜3a与配线金属层3b之间产生空隙。因产生空隙，导致配线3的电阻值从设计值大幅度变化而无法确保配线可靠性。
相对于此，在第1实施方式的半导体装置中，在通孔插塞7的下端与配线3的上端之间，形成着相对于氯及氟反应性较低的金属氧化层81。由此，能够利用金属氧化层81来抑制残留氯或残留氟与第1阻挡金属膜3a中所含有的成分(钛)反应。由此，能够抑制空隙的产生而确保配线可靠性。另外，通过以与通孔插塞7的下端相接的方式设置金属氧化层81，能够更加有效地抑制残留氯或残留氟与第1阻挡金属膜3a中所含有的成分(钛)反应。
(第2实施方式)
接下来，对具备金属氮化层作为金属氧化/氮化层的一例的第2实施方式的半导体装置进行说明。图9A是表示第2实施方式的半导体装置的构造的第1例的剖视图。图9B是表示第2实施方式的半导体装置的构造的第2例的剖视图。
与第1实施方式不同，第2实施方式的半导体装置具备金属氮化层82作为金属氧化/氮化层的一例，来代替金属氧化层81。金属氮化层82的形成位置与金属氧化层81相同，为通孔插塞7的下端与配线3的上端之间。金属氮化层82例如含有氮化钛(TiN)。金属氮化层82例如能够通过如下方法形成：如图5A及图5B所示在配线3上形成金属层6之后，使所形成的金属层6氮化。通过利用金属层6的氮化来形成金属氮化层82，能够抑制形成金属氮化层82所需要的步骤数。例如能够通过在包含氨(NH3)的环境下使金属层6退火或对其进行等离子体处理来进行金属层6的氮化。
在第2实施方式的半导体装置中，在通孔插塞7的下端与配线3的上端之间，形成着相对于氯及氟反应性较低的金属氮化层82。由此，能够利用金属氮化层82来抑制残留氯或残留氟与第1阻挡金属膜3a中所含有的成分(钛)反应。
(第3实施方式)
图10是表示第3实施方式的半导体装置的构造的剖视图。图10所示的半导体装置是阵列芯片C1与电路芯片C2贴合而成的三维存储器。
阵列芯片C1具备包含三维地配置的多个存储单元的存储单元阵列11、存储单元阵列11上的绝缘膜12、以及存储单元阵列11下的层间绝缘膜13。绝缘膜12例如为氧化硅膜或氮化硅膜。层间绝缘膜13例如为氧化硅膜、或包含氧化硅膜与其它绝缘膜的积层膜。
电路芯片C2设置在阵列芯片C1下。符号S表示阵列芯片C1与电路芯片C2的贴合面。电路芯片C2具备层间绝缘膜14、以及层间绝缘膜14下的衬底15。层间绝缘膜14例如为氧化硅膜、或包含氧化硅膜与其它绝缘膜的积层膜。衬底15是第1衬底的一例，例如，为硅衬底等半导体衬底。图10表示了与衬底15的表面也就是上表面平行且相互垂直的X方向及Y方向、以及与衬底15的表面垂直的Z方向。Y方向是第1方向的例子，X方向是与第1方向交叉的第2方向的例子，Z方向是与第1及第2方向交叉的第3方向的例子。
阵列芯片C1具备多条字线WL及源极线SL，作为存储单元阵列11内的多个电极层。图10表示了存储单元阵列11的阶梯构造部21。各字线WL经由接触插塞22与字线配线层23电连接。贯通多条字线WL的各柱状部CL经由通孔插塞24与位线BL电连接，且与源极线SL电连接。源极线SL包含作为半导体层的第1层SL1及作为金属层的第2层SL2。符号V表示设置在位线BL下的通孔插塞。
电路芯片C2具备多个晶体管31。各晶体管31具备：栅极电极32，介隔栅极绝缘膜设置在衬底15上；以及未图示的源极扩散层及漏极扩散层，设置在衬底15内。另外，电路芯片C2具备：多个接触插塞33，设置在这些晶体管31的源极扩散层或漏极扩散层上；配线层34，设置在这些接触插塞33上，且包含多条配线；以及配线层35，设置在配线层34上，且包含多条配线。
电路芯片C2还具备：配线层36，设置在配线层35上，且包含多条配线；多个通孔插塞37，设置在配线层36上；以及多个金属焊垫38，设置在这些通孔插塞37上。金属焊垫38例如为Cu(铜)层或Al(铝)层。电路芯片C2作为控制阵列芯片C1的动作的控制电路(逻辑电路)发挥功能。该控制电路由晶体管31等构成，且电连接于金属焊垫38。
阵列芯片C1具备：多个金属焊垫41，设置在金属焊垫38上；以及多个通孔插塞42，设置在金属焊垫41上。另外，阵列芯片C1具备：配线层43，设置在这些通孔插塞42上，且包含多条配线；以及配线层44，设置在配线层43上，且包含多条配线。金属焊垫41例如为Cu层或Al层。所述通孔插塞V包含于配线层43。
阵列芯片C1还具备：多个通孔插塞45，设置在配线层44上；金属焊垫46，设置在这些通孔插塞45上或绝缘膜12上；以及钝化膜47，设置在金属焊垫46上或绝缘膜12上。金属焊垫46例如为Cu层或Al层，作为图10的半导体装置的外部连接焊垫(接合垫)发挥功能。钝化膜47例如为氧化硅膜等绝缘膜，具有使金属焊垫46的上表面露出的开口部P。金属焊垫46能够经由该开口部P利用接合线、焊球、金属凸块等连接于安装衬底或其它装置。
图11是表示第3实施方式的半导体装置中的柱状部CL的构造的剖视图。
如图11所示，存储单元阵列11具备交替地积层在层间绝缘膜13(图10)上的多条字线WL及多个绝缘层51。字线WL例如为W(钨)层。绝缘层51例如为氧化硅膜。
柱状部CL依次包含阻挡绝缘膜52、电荷蓄积层53、隧道绝缘膜54、通道半导体层55、及芯绝缘膜56。电荷蓄积层53例如为氮化硅膜，介隔阻挡绝缘膜52形成在字线WL及绝缘层51的侧面。电荷蓄积层53也可以为多晶硅层等半导体层。通道半导体层55例如为多晶硅层，介隔隧道绝缘膜54形成在电荷蓄积层53的侧面。阻挡绝缘膜52、隧道绝缘膜54、及芯绝缘膜56例如为氧化硅膜或金属绝缘膜。
图12是表示第3实施方式的半导体装置的制造方法的剖视图。图12表示了包含多个阵列芯片C1的阵列晶片W1及包含多个电路芯片C2的电路晶片W2。阵列晶片W1也被称为存储器晶片，电路晶片W2也被称为CMOS晶片。
图12的存储器晶片W1的方向与图10的阵列芯片C1的方向相反。在第3实施方式中，通过将阵列晶片W1与电路晶片W2贴合而制造半导体装置。图12表示了为了贴合而使方向反转之前的存储器晶片W1，图10表示了为了贴合而使方向反转并贴合及切割之后的阵列芯片C1。
在图12中，符号S1表示存储器晶片W1的上表面，符号S2表示电路晶片W2的上表面。存储器晶片W1具备设置在绝缘膜12下的衬底16。衬底16例如为硅衬底等半导体衬底。衬底16为第2衬底的一例。
在第3实施方式中，首先，如图12所示，在存储器晶片W1的衬底16上形成存储单元阵列11、绝缘膜12、层间绝缘膜13、阶梯构造部21、金属焊垫41等，在电路晶片W2的衬底15上形成层间绝缘膜14、晶体管31、金属焊垫38等。例如，在衬底16上依次形成通孔插塞45、配线层44、配线层43、通孔插塞42、及金属焊垫41。另外，在衬底15上依次形成接触插塞33、配线层34、配线层35、配线层36、通孔插塞37、及金属焊垫38。接着，利用机械压力将阵列晶片W1与电路晶片W2贴合。由此，将层间绝缘膜13与层间绝缘膜14粘接。接着，使阵列晶片W1及电路晶片W2在400℃下退火。由此，将金属焊垫41与金属焊垫38接合。
然后，通过CMP将衬底15薄膜化，且通过CMP将衬底16去除之后，将阵列晶片W1及电路晶片W2切断为多个芯片。这样一来，制造图10的半导体装置。此外，金属焊垫46与钝化膜47例如在衬底15薄膜化及衬底16被去除之后，形成在绝缘膜12上。
此外，在本实施方式中将阵列晶片W1与电路晶片W2贴合，但也可以取而代之将阵列晶片W1彼此贴合。参照图10至图12在上文叙述的内容、或参照图13A、图13B、图14A及图14B将在下文叙述的内容也能够应用于阵列晶片W1彼此的贴合。
另外，图10表示了层间绝缘膜13与层间绝缘膜14的交界面、或金属焊垫41与金属焊垫38的交界面，但一般来说在所述退火后便不再能观察到这些交界面。然而，这些交界面所处的位置例如能够通过检测金属焊垫41的侧面或金属焊垫38的侧面的倾斜、或者金属焊垫41的侧面与金属焊垫38的位置偏移来推定。
第1实施方式的半导体装置的构造、第2实施方式的半导体装置的构造能够应用于第3实施方式的阵列芯片C1。以下，参照图13A、图13B、图14A及图14B说明这种构造的例子。
图13A是表示第3实施方式的半导体装置的构造的第1例的剖视图。图13B是表示第3实施方式的半导体装置的构造的第2例的剖视图。图13A及图13B所示的半导体装置是将第1实施方式的半导体装置的构造应用于第3实施方式的阵列芯片C1而实现的。更详细来说，图13A表示了相对于配线3不发生位置偏移地形成通孔插塞7的情况下的半导体装置，图13B表示了相对于配线3上发生位置偏移地形成通孔插塞7的情况下的半导体装置。图13A及图13B所示的半导体装置由于经过将阵列晶片W1与电路晶片W2贴合而制造，所以图13A及图13B所示的阵列芯片C1的方向与图1A及图1B所示的半导体装置的方向相反。
以下，对图13A所示的半导体装置的构造进行说明，但该说明也能够应用于图13B所示的半导体装置。
在制造图13A所示的半导体装置时，实施图2、图3、图4A、图5A、图6A、图7A及图8A的工序，制作具有图1A所示的构造的阵列晶片W1。此时，第1层间绝缘膜2、多条配线3、金属层6、金属氧化层81、第2层间绝缘膜4、第3层间绝缘膜5及通孔插塞7形成在衬底16上代替形成在衬底1。
接着，如参照图12所说明的那样，将该阵列晶片W1与电路晶片W2贴合，然后进行切割等。这样一来，制造图13A的半导体装置。
此外，该例的配线3与通孔插塞7例如为图10所示的位线BL与通孔插塞V。图1A中，在配线3上形成通孔插塞7，但在图10或图13A中，在配线3(位线BL)下形成通孔插塞7(通孔插塞V)。另外，在图1A中，在通孔插塞7的下端与配线3的上端之间形成金属氧化层81，但在图13A中，在通孔插塞7的上端与配线3的下端之间形成金属氧化层81。
图14A是表示第3实施方式的半导体装置的构造的第3例的剖视图。图14B是表示第3实施方式的半导体装置的构造的第4例的剖视图。图14A及图14B所示的半导体装置是将第2实施方式的半导体装置的构造应用于第3实施方式的阵列芯片C1而实现的。图14A表示了相对于配线3不发生位置偏移地形成通孔插塞7的情况下的半导体装置，图14B表示了相对于配线3上发生位置偏移地形成通孔插塞9的情况下的半导体装置。图14A及图14B所示的半导体装置由于经过将阵列晶片W1与电路晶片W2贴合而制造，所以图14A及图14B所示的阵列芯片C1的方向与图9A及图9B所示的半导体装置的方向相反。
以下，对图14A所示的半导体装置的构造进行说明，但该说明也能够应用于图14B所示的半导体装置。
在制造图14A所示的半导体装置时，制作具有图9A所示的构造的阵列晶片W1。此时，第1层间绝缘膜2、多条配线3、金属层6、金属氮化层82、第2层间绝缘膜4、第3层间绝缘膜5及通孔插塞7形成在衬底16上代替形成在衬底1。
接着，如参照图12所说明的那样，将该阵列晶片W1与电路晶片W2贴合，然后进行切割等。这样一来，制造图14A所示的半导体装置。
此外，该例的配线3与通孔插塞9例如为图10所示的位线BL与通孔插塞V。图9A中，在配线3上形成通孔插塞7，但在图10或图14A中，在配线3(位线BL)下形成通孔插塞7(通孔插塞V)。另外，在图9A中，在通孔插塞7的下端与配线3的上端之间形成金属氮化层82，但在图14A中，在通孔插塞7的上端与配线3的下端之间形成金属氮化层82。
如以上所述，第3实施方式的半导体装置在通孔插塞7的上端与配线3的下端之间，具备金属氧化层81或金属氮化层82。由此，能够利用金属氧化层81或金属氮化层82来抑制残留氯或残留氟与第1阻挡金属膜3a中所含有的成分反应，所以能够抑制配线3与通孔插塞7反应。
以上，对几个实施方式进行了说明，但这些实施方式仅作为示例提出，并不旨在限定发明的范围。本说明书中所说明的新颖的装置及方法能以其它各种形态实施。另外，对于本说明书中所说明的装置及方法的形态，能够在不脱离发明主旨的范围内进行各种省略、置换、变更。随附的权利要求书及与其均等的范围旨在包含发明的范围或主旨中所包含的这种形态或变化例。

Claims (28)

1.一种半导体装置，其包括：
衬底；
第1绝缘膜，其设置在所述衬底的上方；
配线，其设置在所述第1绝缘膜内，所述配线在沿着所述衬底的上表面的第1方向延伸，所述配线具有第1膜及设置在所述第1膜上的第1金属层；
插塞，其设置在所述配线上，所述插塞在与所述第1方向交叉的第2方向延伸，所述插塞电连接于所述配线；
第1层，其包含金属氧化物或金属氮化物，所述第1层设置在所述插塞与所述配线之间；以及
第2金属层，其设置在所述第1层与所述第1金属层之间，所述第2金属层具有与所述第1层不同的成分，
其中所述第1膜、所述第1层和所述第2金属层含有相同的第1金属元素；
其中所述第1层在朝向所述配线的左上端侧相对于朝向所述配线的右上端侧的厚度变薄。
2.根据权利要求1所述的半导体装置，其中所述第1层与所述插塞相接触。
3.根据权利要求1所述的半导体装置，其中所述第1膜含有钛。
4.根据权利要求3所述的半导体装置，其中所述第1层含有氧化钛。
5.根据权利要求3所述的半导体装置，其中所述第1层含有氮化钛。
6.一种半导体装置，其包括：
第1衬底；
逻辑电路，其设置在所述第1衬底上；
第1绝缘膜，其设置在所述逻辑电路的上方；
配线，其包括：
第1膜，其设置在所述第1绝缘膜内，所述第1膜在沿着所述第1衬底的上表面的第1方向延伸；以及
第1金属层，其设置在所述第1绝缘膜内且在所述第1膜上；
插塞，其设置在所述配线之下，所述插塞在与所述第1方向交叉的第2方向延伸，所述插塞电连接于所述配线；
第1层，其包含金属氧化物或金属氮化物，所述第1层设置在所述插塞与所述配线之间；以及
第2金属层，其设置在所述第1层与所述第1金属层之间，所述第2金属层具有与所述第1层不同的成分，
其中所述第1膜、所述第1层和所述第2金属层含有相同的第1金属元素，且其中所述第1层在朝向所述配线的左上端侧相对于朝向所述配线的右上端侧的厚度变薄。
7.根据权利要求6所述的半导体装置，其中所述第1层与所述插塞相接触。
8.根据权利要求6所述的半导体装置，其中所述第1层的下端在所述第2方向定位在所述第1膜的下端处。
9.根据权利要求6所述的半导体装置，其中所述第1层包含所述第1金属元素的氧或氮。
10.根据权利要求6所述的半导体装置，其中所述第1金属元素是钛。
11.根据权利要求10所述的半导体装置，其中所述第1层含有氧化钛。
12.根据权利要求10所述的半导体装置，其中所述第1层含有氮化钛。
13.根据权利要求6所述的半导体装置，其进一步包括第2绝缘膜，其中所述插塞设置在所述逻辑电路的上方并且在被提供在所述第1绝缘膜之下的所述第2绝缘膜内，所述插塞包括金属氮化膜和第3金属层，所述第3金属层设置在所述第2绝缘膜内穿过所述金属氮化膜。
14.根据权利要求13所述的半导体装置，其中所述第3金属层含有钨，并且所述金属氮化膜含有氮化钛或氮化钨。
15.根据权利要求6所述的半导体装置，其中所述配线的所述第1金属层含有铜。
16.根据权利要求6所述的半导体装置，其中所述配线包括垫或插塞中的至少一者。
17.根据权利要求6所述的半导体装置，其中所述第1膜包括扩散阻挡金属。
18.根据权利要求6所述的半导体装置，其中所述第1层被布置以抑制所述插塞和所述配线之间的反应。
19.根据权利要求6所述的半导体装置，进一步包括所述第1层和所述插塞之间的扩散阻挡。
20.根据权利要求6所述的半导体装置，其中所述配线是位线。
21.根据权利要求6所述的半导体装置，其中所述第1层沿着所述第1方向具有不同的厚度。
22.根据权利要求6所述的半导体装置，其中所述插塞的部分定位在所述配线的侧面上。
23.根据权利要求6所述的半导体装置，其中所述配线包括第1配线和与所述第1配线相邻的第2配线，
其中所述第1配线的所述第1膜和所述第2配线的所述第1膜具有不同的厚度。
24.一种半导体装置，其包括：
衬底；
绝缘膜，其设置在所述衬底的上方；
第1配线，其包括：
第1膜，其设置在所述绝缘膜内，所述第1膜在沿着所述衬底的上表面的第1方向延伸，所述第1膜含有第1金属，及
第1金属层，其设置在所述绝缘膜内且设置在所述第1膜上；
插塞，其电连接于所述第1配线，所述插塞在与所述第1方向交叉的第2方向延伸；
第1层，其含有金属氧化物或金属氮化物，所述第1层设置在所述插塞与所述第1配线之间；以及
第2金属层，其设置在所述第1层与所述第1金属层之间，所述第2金属层含有所述第1金属且具有与所述第1层不同的成分，其中所述第1膜、所述第1层和所述第2金属层含有相同的金属元素；及
第2配线，其设置与第1配线相邻，所述第2配线具有第2膜，所述第2膜含有第1金属，所述第2膜在所述第1方向延伸，
其中所述第1层在朝向所述第1配线的左上端侧相对于朝向所述第1配线的右上端侧的厚度变薄。
25.根据权利要求24所述的半导体装置，其中所述相同的金属元素是钛。
26.根据权利要求25所述的半导体装置，其中所述第1层含有氧化钛。
27.根据权利要求25所述的半导体装置，其中所述第1层含有氮化钛。
28.根据权利要求24所述的半导体装置，其中所述配线的所述第1金属层含有铜。
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