TWI808340B - 半導體記憶裝置及其製造方法 - Google Patents

半導體記憶裝置及其製造方法 Download PDF

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TWI808340B
TWI808340B TW109127050A TW109127050A TWI808340B TW I808340 B TWI808340 B TW I808340B TW 109127050 A TW109127050 A TW 109127050A TW 109127050 A TW109127050 A TW 109127050A TW I808340 B TWI808340 B TW I808340B
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Taiwan
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metal pad
metal
memory device
array
semiconductor memory
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TW109127050A
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TW202137351A (zh
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若月啓
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日商鎧俠股份有限公司
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Abstract

實施形態提供一種可減少金屬焊墊彼此之接合不良之半導體記憶裝置及其製造方法。 一實施形態之半導體記憶裝置具備：陣列晶片，其具有記憶胞陣列；電路晶片，其具有與記憶胞電性連接之電路；及金屬焊墊，其將陣列晶片與電路晶片接合。金屬焊墊含有雜質。雜質之濃度於金屬焊墊之厚度方向上，隨著自表面向深度方向離開而變低。

Description

半導體記憶裝置及其製造方法
本發明之實施形態係關於一種半導體記憶裝置及其製造方法。
已知有於三維記憶體等半導體記憶裝置中將分別形成於2片晶圓之金屬焊墊彼此接合之技術。於該技術中，若金屬焊墊被過度研磨，則產生凹陷。
本發明所欲解決之問題在於提供一種可減少金屬焊墊彼此之接合不良之半導體記憶裝置及其製造方法。
一實施形態之半導體記憶裝置具備：陣列晶片，其具有記憶胞陣列；電路晶片，其具有與記憶胞電性連接之電路；及金屬焊墊，其將陣列晶片與電路晶片接合。金屬焊墊含有雜質。雜質之濃度於金屬焊墊之厚度方向上，隨著自表面向深度方向離開而變低。
1:陣列晶片
2:電路晶片
11:記憶胞陣列
12:絕緣層
13:絕緣層
14:層間絕緣膜
15:絕緣層
16:層間絕緣膜
17:基板
18:基板
21:階梯構造部
22:接觸插塞
23:字元配線層
24:接觸插塞
25:源極線
26:接觸插塞
27:選擇閘極配線層
28:插塞
31:電晶體
32:閘極電極
33:插塞
34:配線層
35:配線層
36:金屬焊墊
37:配線層
41:焊墊
42:外部連接電極
43:外部連接焊墊
51:絕緣層
52:阻擋絕緣膜
53:電荷儲存層
54:隧道絕緣膜
55:通道半導體層
56:核心絕緣膜
61:第2絕緣層
62,62a:第2金屬焊墊
63:銀層
71:第1絕緣層
72:第1金屬焊墊
BL:位元線
CL:柱狀部
SG:選擇閘極
W1:陣列晶圓
W2:電路晶圓
WL:字元線
BG:填埋源極線
圖1係表示第1實施形態之半導體記憶裝置之構造之剖視圖。
圖2係表示圖1所示之柱狀部之構造之剖視圖。
圖3係表示陣列晶圓與電路晶圓之構造之剖視圖。
圖4係表示研磨後之第2金屬焊墊之剖視圖。
圖5係表示實施烷硫醇(alkanethiol)處理後之第2金屬焊墊之剖視圖。
圖6係表示實施熱處理後之第2金屬焊墊之剖視圖。
圖7係將陣列晶圓與電路晶圓之接合部位放大所得之剖視圖。
圖8係表示導入有硝酸銀之第2金屬焊墊之剖視圖。
圖9係表示形成有銀層之第2金屬焊墊之剖視圖。
圖10係表示實施熱處理後之第2金屬焊墊之剖視圖。
圖11係將陣列晶圓與電路晶圓之接合部位放大所得之剖視圖。
圖12係表示於甲矽烷氣氛下實施熱處理後之第2金屬焊墊之剖視圖。
圖13係表示生成矽化物之第2金屬焊墊之剖視圖。
圖14係將陣列晶圓與電路晶圓之接合部位放大所得之剖視圖。
以下，參照圖式對本發明之實施形態進行說明。本實施形態並不限定本發明。
(第1實施形態)
圖1係表示第1實施形態之半導體記憶裝置之構造之剖視圖。圖1之半導體記憶裝置係將陣列晶片1與電路晶片2貼合而成之三維記憶體。
陣列晶片1具備包含複數個記憶胞之記憶胞陣列11、記憶胞陣列11上之絕緣層12(例如氮化矽膜)、絕緣層12上之絕緣層13(例如氧化矽膜)、及記憶胞陣列11下之層間絕緣膜14。
又，陣列晶片1具備複數條字元線WL、填埋源極線BG及選擇閘極SG作為記憶胞陣列11內之電極層。於記憶胞陣列11之階梯構造部21中，各字元線WL經由接觸插塞22與字元配線層23電性連接。同樣 地，填埋源極線BG經由接觸插塞24與源極線25電性連接，選擇閘極SG經由接觸插塞26與選擇閘極配線層27電性連接。貫通字元線WL、填埋源極線BG及選擇閘極SG之柱狀部CL經由插塞28與位元線BL電性連接。
進而，陣列晶片1具備：焊墊41，其經由未圖示之通孔插塞與配線層37電性連接；外部連接電極42，其設置於焊墊41上；及外部連接焊墊43，其設置於外部連接電極42上。外部連接焊墊43可經由焊球、金屬凸塊、接合線等連接於安裝基板或其他裝置。
電路晶片2介隔絕緣層15設置於陣列晶片1下。電路晶片2具備層間絕緣膜16、及層間絕緣膜16下之基板17。基板17例如為矽基板等半導體基板。於以下之說明中，將與基板17之表面平行且相互垂直之方向設為X方向及Y方向，將與基板17之表面垂直之方向設為Z方向。於本說明書中，將+Z方向作為上方向進行處理，將-Z方向作為下方向進行處理，但-Z方向可與重力方向一致，亦可與重力方向不一致。
又，電路晶片2具備複數個電晶體31。各電晶體31具備：閘極電極32，其介隔閘極絕緣膜設置於基板17上；及未圖示之源極擴散層及汲極擴散層，其等設置於基板17內。又，電路晶片2具備：複數個插塞33，其等設置於源極擴散層或汲極擴散層上；配線層34，其設置於該等插塞33上；及配線層35，其設置於配線層34上。電晶體31、插塞33、配線層34及配線層35構成與記憶胞陣列11電性連接之電路。
於配線層35上設置有複數個金屬焊墊36。各金屬焊墊36由絕緣層15包圍。於金屬焊墊36上設置有陣列晶片1之配線層37。
圖2係表示陣列晶片1之柱狀部CL之構造之剖視圖。如圖2所示，記憶胞陣列11具備交替地積層於層間絕緣膜14上之複數條字元線 WL與複數個絕緣層51。各字元線WL例如為鎢(W)層。各絕緣層51例如為 氧化矽膜。
柱狀部CL具備作為第1絕緣膜之例之阻擋絕緣膜52、電荷儲存層53、作為第2絕緣膜之例之隧道絕緣膜54、通道半導體層55及核心絕緣膜56。電荷儲存層53例如為氮化矽膜，介隔阻擋絕緣膜52形成於字元線WL及絕緣層51之側面。通道半導體層55例如為矽層，介隔隧道絕緣膜54形成於電荷儲存層53之側面。阻擋絕緣膜52、隧道絕緣膜54及核心絕緣膜56之例係氧化矽膜或金屬絕緣膜。
以下，對本實施形態之半導體記憶裝置之製造方法進行說明。
首先，如圖3所示，形成包含複數個陣列晶片1之陣列晶圓W1、及包含複數個電路晶片2之電路晶圓W2。於陣列晶圓W1之下表面形成有第1絕緣層71及複數個第1金屬焊墊72。各第1金屬焊墊72形成於配線層37之下表面。又，於陣列晶圓W1中，於絕緣層13上設置有基板18。
另一方面，於電路晶圓W2之上表面形成有第2絕緣層61及複數個第2金屬焊墊62。各第2金屬焊墊62形成於配線層35之上表面。此處，參照圖4~圖6對第2金屬焊墊62之製造方法詳細地進行說明。
首先，於配線層35上形成以銅(Cu)為主成分之第2金屬焊墊62a。其後，若對第2金屬焊墊62a進行研磨，則如圖4所示，有時第2金屬焊墊62a之上表面產生相對於第2絕緣層61之上表面下凹之凹陷。於該情形時，將陣列晶圓W1與電路晶圓W2接合時，會產生於接合面形成間隙之接合不良。
因此，於本實施形態中，如圖5所示，將包含碳(C)鍵結於 硫醇基(SH)所得之烷硫醇(CxHyS：x、y為自然數)之氣體或液體導入至第2金屬焊墊62a。藉此，碳作為雜質附著於第2金屬焊墊62a之表面。
繼而，進行將第2金屬焊墊62a加熱之熱處理。其結果，如圖6所示，碳向第2金屬焊墊62a中擴散而第2金屬焊墊62a之體積增加。藉此，第2金屬焊墊62完成。該第2金屬焊墊62之上表面成為位於與第2絕緣層61之上表面大致相同高度之位置之平面。又，第2金屬焊墊62如圖6所示，具有如下濃度梯度：隨著自表面(上表面)沿厚度方向(-Z方向)前進，即，隨著自表面向深度方向離開，而碳濃度變低。
另一方面，關於第1金屬焊墊72，亦可與第2金屬焊墊62同樣地形成。即，於對以銅為主成分之第1金屬焊墊72進行研磨時產生凹陷之情形時，藉由進行上述烷硫醇處理及熱處理，而形成含有碳作為雜質之第1金屬焊墊72。於該情形時，第1金屬焊墊72之下表面成為位於與第1絕緣層71之下表面大致相同高度之位置之平面。又，第1金屬焊墊72亦具有如下濃度梯度：隨著自表面(下表面)沿厚度方向(Z方向)前進，即，隨著自表面向深度方向離開，而碳濃度變低。
如上述般形成第1金屬焊墊72及第2金屬焊墊62之後，藉由機械壓力將陣列晶圓W1與電路晶圓W2貼合。藉此，將第1絕緣層71與第2絕緣層61接著，形成絕緣層15。
繼而，對陣列晶圓W1及電路晶圓W2以例如400℃進行退火。藉此，將第1金屬焊墊72與第2金屬焊墊62接合，形成複數個金屬焊墊36。
圖7係將陣列晶圓W1與電路晶圓W2之接合部位放大所得之剖視圖。如上所述，於第1金屬焊墊72及第2金屬焊墊62中，藉由將碳作 為雜質導入而凹陷得以矯正。因此，於第1金屬焊墊72與第2金屬焊墊62之接合面，換言之，於金屬焊墊36之中央部不形成間隙。又，如圖7所示，金屬焊墊36具有隨著自其中央部沿厚度方向(Z方向、-Z方向)離開而碳濃度變低之濃度梯度。
形成金屬焊墊36之後，藉由CMP(Chemical Mechanical Polishing，化學機械拋光)或濕式蝕刻將基板18去除，將陣列晶圓W1及電路晶圓W2切斷成複數個晶片。以此方式製造圖1之半導體記憶裝置。再者，外部連接電極42與外部連接焊墊43例如於去除基板18之後形成於焊墊41上。
根據本實施形態，藉由將碳作為雜質導入至金屬焊墊並進行熱處理，而使金屬焊墊之體積增加。因此，即便因金屬焊墊之研磨而產生凹陷，亦可使金屬焊墊之體積增加。藉此，可減少陣列晶片1與電路晶片2之接合不良。
再者，於本實施形態中，將碳導入至第1金屬焊墊72及第2金屬焊墊62之兩者，但碳之導入只要根據各金屬焊墊之下凹程度進行判斷即可。因此，亦可根據各金屬焊墊之下凹程度而將碳導入至第1金屬焊墊72或第2金屬焊墊62中之一者。
又，於本實施形態中，形成第1金屬焊墊72及第2金屬焊墊62時，熱處理於將陣列晶圓W1與電路晶圓W2接合之前進行，但亦可於該等晶圓之接合時進行。於陣列晶圓W1與電路晶圓W2之接合時，兩晶圓以例如400℃之熱進行退火，因此，亦可將該退火處理利用於上述熱處理。於該情形時，亦藉由作為雜質所導入之碳擴散而體積增加，因此，如圖7所示，可無間隙地將第1金屬焊墊72與第2金屬焊墊62接合。
(第2實施形態)
以下，針對第2實施形態，以與第1實施形態之不同點為中心進行說明。於本實施形態中，第1金屬焊墊72及第2金屬焊墊62之製造方法與第1實施形態不同。以下，參照圖8~圖10對本實施形態中之第2金屬焊墊62之製造方法進行說明。
如圖8所示，於第2金屬焊墊62a中產生凹陷之情形時，首先，將包含硝酸銀(AgNO3)之液體導入至第2金屬焊墊62a。藉此，發生下述式(1)所示之取代反應。
Figure 109127050-A0305-02-0008-17
藉由上述取代反應，如圖9所示，銀析出至第2金屬焊墊62a之表面而形成銀層63。
繼而，進行將第2金屬焊墊62a加熱之熱處理。其結果，如圖10所示，銀向第2金屬焊墊62a中擴散而第2金屬焊墊62a之體積增加。藉此，第2金屬焊墊62完成。該第2金屬焊墊62之上表面與第1實施形態同樣地，成為位於與第2絕緣層61之上表面大致相同高度之位置之平面。又，第2金屬焊墊62如圖10所示，具有隨著自表面(上表面)沿厚度方向(-Z方向)前進而銀濃度變低之濃度梯度。
另一方面，關於第1金屬焊墊72，亦可與第2金屬焊墊62同樣地形成。即，於對以銅為主成分之第1金屬焊墊72進行研磨時產生凹陷之情形時，藉由進行上述取代反應及熱處理，而形成含有銀作為雜質之第1金屬焊墊72。於該情形時，第1金屬焊墊72之下表面與第1實施形態同樣地，成為位於與第1絕緣層71之下表面大致相同高度之位置之平面。又，第1金屬焊墊72亦具有隨著自表面(下表面)沿厚度方向(Z方向)前進而銀濃 度變低之濃度梯度。
其後，與第1實施形態同樣地，藉由機械壓力將陣列晶圓W1與電路晶圓W2貼合而形成絕緣層15。進而，對陣列晶圓W1及電路晶圓W2以例如400℃進行退火，形成複數個金屬焊墊36。
圖11係將陣列晶圓W1與電路晶圓W2之接合部位放大所得之剖視圖。如上所述，於第1金屬焊墊72及第2金屬焊墊62中，藉由將銀作為雜質導入而凹陷得以矯正。因此，於金屬焊墊36之中央部不形成間隙。又，如圖11所示，金屬焊墊36具有隨著自其中央部沿厚度方向(Z方向、-Z方向)離開而銀濃度變低之濃度梯度。
根據本實施形態，藉由將銀作為雜質導入至金屬焊墊並進行熱處理，而使金屬焊墊之體積增加。因此，即便因金屬焊墊之研磨而產生凹陷，亦可使金屬焊墊之體積增加。藉此，可減少陣列晶片1與電路晶片2之接合不良。
再者，於本實施形態中，將硝酸銀導入至第2金屬焊墊62a，但亦可將氯化銀(AgCl)導入而代替硝酸銀。於該情形時，銀亦析出至第2金屬焊墊62a之表面，因此，可藉由熱處理使第2金屬焊墊62a之體積增加。
又，關於硝酸銀或氯化銀之導入，亦可與第1實施形態同樣地，根據研磨後之各金屬焊墊之下凹程度而導入至第1金屬焊墊72或第2金屬焊墊62中之一者。
(第3實施形態)
以下，針對第3實施形態，以與第1實施形態之不同點為中心進行說明。於本實施形態中，第1金屬焊墊72及第2金屬焊墊62之製造 方法與第1實施形態不同。以下，參照圖12及圖13對本實施形態中之第2金屬焊墊62之製造方法進行說明。
如圖12所示，於第2金屬焊墊62a中產生凹陷之情形時，首先，於甲矽烷(SiH4)氣氛下對第2金屬焊墊62a進行熱處理。其結果，如圖13所示，生成第2金屬焊墊62a中包含之銅與甲矽烷中包含之矽鍵結所得之矽化物而第2金屬焊墊62a之體積增加。藉此，第2金屬焊墊62完成。該第2金屬焊墊62之上表面與第1實施形態同樣地，成為位於與第2絕緣層61之上表面大致相同高度之位置之平面。又，第2金屬焊墊62如圖13所示，具有隨著自表面(上表面)沿厚度方向(-Z方向)前進而矽濃度變低之濃度梯度。
另一方面，關於第1金屬焊墊72，亦可與第2金屬焊墊62同樣地形成。即，於對以銅為主成分之第1金屬焊墊72進行研磨時產生凹陷之情形時，藉由在上述甲矽烷氣氛下進行熱處理，而形成含有矽作為雜質之第1金屬焊墊72。於該情形時，第1金屬焊墊72之下表面與第1實施形態同樣地，成為位於與第1絕緣層71之下表面大致相同高度之位置之平面。又，第1金屬焊墊72亦具有隨著自表面(下表面)沿厚度方向(Z方向)前進而銀濃度變低之濃度梯度。
其後，與第1實施形態同樣地，藉由機械壓力將陣列晶圓W1與電路晶圓W2貼合而形成絕緣層15。進而，對陣列晶圓W1及電路晶圓W2以例如400℃進行退火，形成複數個金屬焊墊36。
圖14係將陣列晶圓W1與電路晶圓W2之接合部位放大所得之剖視圖。如上所述，於第1金屬焊墊72及第2金屬焊墊62中，藉由將矽作為雜質導入而凹陷得以矯正。因此，於金屬焊墊36之中央部不形成間 隙。又，如圖14所示，金屬焊墊36具有隨著自其中央部沿厚度方向(Z方向、-Z方向)離開而矽濃度變低之濃度梯度。
根據本實施形態，藉由將矽作為雜質導入至金屬焊墊，而使金屬焊墊之體積增加。因此，即便因金屬焊墊之研磨而產生凹陷，亦可使金屬焊墊之體積增加。藉此，可減少陣列晶片1與電路晶片2之接合不良。
再者，於本實施形態中，於甲矽烷氣氛下進行熱處理，但亦可於乙矽烷(Si2H6)氣氛下進行熱處理。於該情形時，銅與矽鍵結所得之矽化物亦於第2金屬焊墊62a內擴散，因此，可使第2金屬焊墊62a之體積增加。
又，於本實施形態中，甲矽烷氣氛或乙矽烷氣氛之熱處理亦可於陣列晶圓W1與電路晶圓W2之接合時進行。於陣列晶圓W1與電路晶圓W2之接合時，兩晶圓以例如400℃之熱進行退火，因此，亦可將該退火處理利用於金屬焊墊之熱處理。於該情形時也是，藉由作為雜質所導入之矽擴散而金屬焊墊之體積增加，因此，如圖14所示，可無間隙地將第1金屬焊墊72與第2金屬焊墊62接合。
已對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出，並不意圖限定發明之範圍。該等實施形態能夠以其他多種形態實施，可於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，且同樣包含於申請專利範圍所記載之發明及其均等之範圍內。
[相關申請]
本申請享有以日本專利申請2020-046781號(申請日：2020 年3月17日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
15:絕緣層
36:金屬焊墊
61:第2絕緣層
62:第2金屬焊墊
71:第1絕緣層
72:第1金屬焊墊

Claims (9)

  1. 一種半導體記憶裝置，其具備：陣列晶片，其具有記憶胞陣列；電路晶片，其具有與上述記憶胞陣列電性連接之電路；及金屬焊墊，其將上述陣列晶片與上述電路晶片接合；且上述金屬焊墊含有雜質，上述雜質之濃度於上述金屬焊墊之厚度方向上，隨著自表面向深度方向離開而變低，上述金屬焊墊具有設置於上述陣列晶片之第1金屬焊墊、及設置於上述電路晶片之第2金屬焊墊，且上述金屬焊墊內之上述雜質之濃度於上述第1金屬焊墊與上述第2金屬焊墊之接合面處最高。
  2. 如請求項1之半導體記憶裝置，其中上述金屬焊墊含有銅(Cu)，且上述雜質為碳(C)、銀(Ag)或矽(Si)。
  3. 一種半導體記憶裝置之製造方法，其於具有記憶胞陣列之陣列晶圓之表面形成第1金屬焊墊，於具有與上述記憶胞陣列電性連接之電路之電路晶圓之表面形成第2金屬焊墊，將雜質導入至上述第1金屬焊墊及上述第2金屬焊墊之至少一者，對導入有上述雜質之金屬焊墊進行熱處理，將上述陣列晶圓與上述電路晶圓貼合而將上述第1金屬焊墊與上述第2金屬焊墊接合。
  4. 如請求項3之半導體記憶裝置之製造方法，其中利用銅形成上述第1金屬焊墊及上述第2金屬焊墊，將烷硫醇(CxHyS：x、y為自然數)導入至上述第1金屬焊墊及上述第2金屬焊墊之至少一者，對導入有上述烷硫醇之金屬焊墊進行熱處理。
  5. 如請求項4之半導體記憶裝置之製造方法，其中當將上述第1金屬焊墊與上述第2金屬焊墊接合時進行上述熱處理。
  6. 如請求項3之半導體記憶裝置之製造方法，其中利用銅形成上述第1金屬焊墊及上述第2金屬焊墊，將硝酸銀(AgNO3)或氯化銀(AgCl)導入至上述第1金屬焊墊及上述第2金屬焊墊之至少一者，對導入有上述硝酸銀或氯化銀之金屬焊墊進行熱處理。
  7. 如請求項6之半導體記憶裝置之製造方法，其中當將上述第1金屬焊墊與上述第2金屬焊墊接合時進行上述熱處理。
  8. 如請求項3之半導體記憶裝置之製造方法，其中利用銅形成上述第1金屬焊墊及上述第2金屬焊墊，於甲矽烷(SiH4)氣氛或乙矽烷(Si2H6)氣氛下對上述第1金屬焊墊及上述第2金屬焊墊之至少一者進行熱處理。
  9. 如請求項8之半導體記憶裝置之製造方法，其中當將上述第1金屬焊墊與上述第2金屬焊墊接合時進行上述熱處理。
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