CN114156275A - 半导体存储装置及其制造方法 - Google Patents

半导体存储装置及其制造方法 Download PDF

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CN114156275A
CN114156275A CN202110086518.1A CN202110086518A CN114156275A CN 114156275 A CN114156275 A CN 114156275A CN 202110086518 A CN202110086518 A CN 202110086518A CN 114156275 A CN114156275 A CN 114156275A
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region
substrate
opening
chip
semiconductor memory
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渡边慎也
荒井伸也
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Kioxia Corp
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Kioxia Corp
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Abstract

实施方式提供一种能够减少导致不良的破损的半导体存储装置及其制造方法。实施方式的半导体存储装置具备第1芯片及贴合于第1芯片的第2芯片。第1芯片具有第1衬底、设置在所述第1衬底上的晶体管、及设置在所述晶体管上方的第1焊垫。第2芯片具有设置在所述第1焊垫上的第2焊垫、设置在所述第2焊垫上方且具有多个存储单元的存储单元阵列、及连接于所述存储单元阵列的第2衬底。所述第1芯片及第2芯片具有具备所述存储单元阵列的第1区域、及具备从所述第1衬底到达所述第2衬底的间隔壁的第2区域。所述第2衬底在所述第2区域中具有贯通所述第2衬底的第1开口。

Description

半导体存储装置及其制造方法
[相关申请案]
本申请案享有以日本专利申请案2020-150045号(申请日：2020年9月7日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的所有内容。
技术领域
本发明的实施方式涉及一种半导体存储装置及其制造方法。
背景技术
业界是将形成着多个电路或元件的器件贴合，来制作一个半导体存储装置。
发明内容
本发明的实施方式提供一种能够减少导致不良的破损的半导体存储装置及其制造方法。
实施方式的半导体存储装置具备第1芯片及贴合于第1芯片的第2芯片。第1芯片具有第1衬底、设置在所述第1衬底上的晶体管、及设置在所述晶体管上方的第1焊垫。第2芯片具有设置在所述第1焊垫上的第2焊垫、设置在所述第2焊垫上方且具有多个存储单元的存储单元阵列、及连接于所述存储单元阵列的第2衬底。所述第1芯片及第2芯片具有具备所述存储单元阵列的第1区域、及具备从所述第1衬底到达所述第2衬底的间隔壁的第2区域。所述第2衬底在所述第2区域中具有贯通所述第2衬底的第1开口。
附图说明
图1是第1实施方式的半导体存储装置的剖视图。
图2是第1实施方式的半导体存储装置的柱状部的剖视图。
图3是第1实施方式的半导体存储装置的俯视图。
图4是第1实施方式的半导体存储装置的特征部分的放大图。
图5～9是用来对第1实施方式的半导体存储装置的制造方法进行说明的剖视图。
图10是用来对第1实施方式的半导体存储装置的制造方法进行说明的俯视图。
图11是第1变化例的半导体存储装置的特征部分的放大图。
图12是第2变化例的半导体存储装置的特征部分的放大图。
图13是第3变化例的半导体存储装置的俯视图。
图14是第4变化例的半导体存储装置的剖视图。
具体实施方式
以下，参照附图对实施方式的半导体存储装置进行说明。在以下说明中，对具有相同或类似功能的构成标注相同符号。并且，有时会省略这些构成的重复说明。附图是示意图或概念图，各部分的厚度与宽度的关系，部分间的尺寸的比率等未必与现实相同。本说明书中，所谓“连接”，并不限定于物理连接的情况，也包括电连接的情况。
首先，对X方向、Y方向、Z方向进行定义。X方向及Y方向是与下述第1衬底10的表面大致平行的方向。X方向与Y方向彼此大致正交。Z方向是与X方向及Y方向大致正交且远离第1衬底10的方向。但是，这些表达是为了方便说明，并非规定重力方向。本实施方式中，Z方向是“第1方向”的一例。
(第1实施方式)
图1是第1实施方式的半导体存储器100的剖视图。半导体存储器100是非易失性半导体存储装置，例如为NAND(NOT AND，与非)型闪速存储器。半导体存储器100是将阵列芯片1与电路芯片2贴合而成的三维存储器。阵列芯片1是第2芯片的一例，电路芯片2是第1芯片的一例。阵列芯片1与电路芯片2隔着贴合面S而贴合。电路芯片2作为控制阵列芯片1的动作的控制电路(逻辑电路)发挥作用。
半导体存储器100具备第1衬底10、积层体20、第2衬底50及绝缘层61、62。
第1衬底10是电路芯片2的衬底。第1衬底10例如为硅衬底。第1衬底10的一部分成为晶体管24的源极区域、漏极区域。
积层体20位于第1衬底10上。积层体20具有积层体20A及积层体20B。积层体20A积层于第1衬底10。积层体20B与第2衬底50相接。第1衬底10及积层体20A成为电路芯片2。第2衬底50及积层体20B成为阵列芯片1。
积层体20A具备多个焊垫21、多个接触插塞22、多条配线23、多个晶体管24及绝缘膜25。多个焊垫21中的一部分焊垫21A露出到贴合面S。露出到贴合面S的焊垫21A是第1焊垫的一例。晶体管24与焊垫21、接触插塞22、配线23的任一个电连接。
积层体20B具备多个焊垫26、多个接触插塞27、多条配线28、存储单元阵列30及绝缘膜29。多个焊垫26中的一部分焊垫26A露出到贴合面S。露出到贴合面S的焊垫26A是第2焊垫的一例。焊垫26A设置在焊垫21A上。
焊垫21、26、接触插塞22、27、配线23、28各自将存储单元阵列30与多个晶体管24连接。
焊垫21、26、接触插塞22、27、配线23、28各自例如含有Cu、Al。焊垫21、26是在XY面内具有一定区域的电极。阵列芯片1的焊垫21与电路芯片2的焊垫26隔着贴合面S而接合。接触插塞22、27是在Z方向上延伸且将不同阶层间电连接的配线。配线23、28是在XY面内的任一方向上延伸的配线。焊垫21、接触插塞22、配线23设置在第1衬底10的上方。焊垫26、接触插塞27、配线28处于积层体20B内，设置在积层体20A的上方。
各个晶体管24属于电路芯片2，且位于第1衬底10上。晶体管24控制存储单元阵列30。晶体管24经由焊垫21、26、接触插塞22、27、配线23、28，与存储单元阵列30电连接。绝缘膜25、29是使各阶层之间绝缘的层间绝缘膜。绝缘膜25、29例如为氧化硅膜与碳氮化硅膜的积层体。利用氧化硅膜与碳氮化硅膜的蚀刻速率的差异，形成用于焊垫21、26、接触插塞22、27、配线23、28等的开口。
存储单元阵列30设置在第2衬底50的上方。存储单元阵列30设置在焊垫26A的上方。存储单元阵列30属于阵列芯片1。存储单元阵列30在制造时被积层在第2衬底50上。图2是将第1实施方式的存储单元阵列30的柱状体CL附近放大后的剖视图。
存储单元阵列30具有多个导电层31、多个绝缘层32及柱状体CL。导电层31与绝缘层32交替地积层。
多个导电层31分别在X方向及Y方向上扩展。导电层31例如为掺杂着钨、杂质的多晶硅。导电层31的数量为任意。导电层31成为漏极侧选择栅极SGD、字线WL及源极侧选择栅极SGS。这些漏极侧选择栅极SGD、字线WL及源极侧选择栅极SGS各自在存储单元阵列30的阶梯区域ST露出，且分别与接触插塞27连接。
多个绝缘层32分别在X方向及Y方向上扩展。绝缘层32例如包含氧化硅。绝缘层32位于导电层31与第2衬底50之间、以及在Z方向上相邻的导电层31之间。绝缘层32使邻接的导电层31之间绝缘。绝缘层32的数量根据导电层31的数量来决定。
柱状体CL在存储单元阵列30内存在多个。柱状体CL分别在Z方向上延伸。各个柱状体CL例如在Z方向上贯通交替地积层的多个导电层31及多个绝缘层32。例如，柱状体CL从Z方向观察时的俯视形状为圆或椭圆。
柱状体CL分别从内侧起依序具有芯33、半导体柱身34、存储器膜35。柱状体CL形成在存储器孔MH内。
芯33在Z方向上延伸，呈柱状。芯33例如包含氧化硅。芯33位于半导体柱身34的内侧。
半导体柱身34在Z方向上延伸。半导体柱身34连接于第2衬底50的下述作为源极线发挥作用的导电区域。半导体柱身34被覆芯33的外侧面。半导体柱身34例如含有硅。硅例如为使非晶硅结晶化而成的多晶硅。
存储器膜35在Z方向上延伸。存储器膜35被覆半导体柱身34的外侧面。存储器膜35位于存储器孔MH的内表面与半导体柱身34的外侧面之间。存储器膜35例如包含隧道绝缘膜36及电荷储存膜37。隧道绝缘膜36、电荷储存膜37依序位于半导体柱身34的附近。
隧道绝缘膜36位于电荷储存膜37与半导体柱身34之间。隧道绝缘膜36例如包含氧化硅或氧化硅及氮化硅。隧道绝缘膜36是半导体柱身34与电荷储存膜37之间的电位障壁。
电荷储存膜37位于绝缘层32及导电层31的每一个与隧道绝缘膜36之间。电荷储存膜37例如包含氮化硅。电荷储存膜37与多个导电层31的每一个交叉的部分分别作为存储单元MC发挥作用。存储单元MC根据电荷储存膜37与多个导电层31交叉的部分(电荷储存部)内有无电荷，或根据所储存的电荷量来保存数据。电荷储存部位于各个导电层31与半导体柱身34之间，四周由绝缘材料包围。
在各个导电层31与绝缘层32之间、及各个导电层31与存储器膜35之间，可具有阻挡绝缘膜31a、障壁膜31b。阻挡绝缘膜31a抑制反向穿隧。反向穿隧是电荷从导电层31返回到存储器膜35的现象。阻挡绝缘膜31a例如为将氧化硅膜、金属氧化物膜、多个绝缘膜积层而成的积层构造膜。金属氧化物的一例为氧化铝。障壁膜31b例如为氮化钛或氮化钛与钛的积层构造膜。
可在各个绝缘层32与电荷储存膜37之间具有覆盖绝缘膜38。覆盖绝缘膜38例如包含氧化硅。覆盖绝缘膜38在加工时保护电荷储存膜37免受蚀刻的损害。覆盖绝缘膜38可不存在，也可在导电层31与电荷储存膜37之间残留一部分，用作阻挡绝缘膜。
图3是从Z方向观察第1实施方式的半导体存储器100的积层体20所得的俯视图。阵列芯片1及电路芯片2所含的积层体20具有第1区域A1、第2区域A2及第3区域A3。图1是沿着图3中的A-A线的剖视图。
从Z方向俯视观察时，第1区域A1是与存储单元阵列30重叠的区域。第1区域A1具有存储单元阵列30。第1区域A1被称为存储单元阵列区域，是存储数据的区域。
第2区域A2包围第1区域A1的四周。第2区域A2具有贯通积层体20，且从第1衬底10到达第2衬底50的间隔壁40。间隔壁40包围存储单元阵列30的四周。间隔壁40可以包围存储单元阵列30的方式存在多个。间隔壁40包含焊垫21、26、接触插塞22、27及配线23、28。间隔壁40被称为边缘密封件、裂缝导引件。间隔壁40含有金属。间隔壁40例如防止水分从周围向存储单元阵列30渗入。间隔壁40例如防止裂缝朝着存储单元阵列30产生。
从Z方向俯视观察时，第3区域A3位于第1区域A1与第2区域A2之间。第3区域A3例如位于第1区域A1的任一边的侧方。第3区域A3例如位于第1区域A1的X方向或Y方向的侧方。第3区域A3是存在露出到外部的焊垫P的区域。焊垫P是外部连接焊垫的一例。焊垫P是金属层53的一部分。焊垫P是与外部的连接端子，在向外部传输信号或向电路芯片2供给电源时使用。
第2衬底50位于积层体20上。第2衬底50是制作阵列芯片1时的衬底。第2衬底50例如为硅衬底。第2衬底50例如在第1区域A1中从第1衬底10侧的表面注入杂质而成为导电区域，该区域作为存储单元阵列30的源极线发挥作用。第2衬底50的厚度例如比第1衬底10的厚度薄。
另外，该实施方式中，虽然在第2衬底50形成导电区域，并使该区域作为源极线发挥作用，但源极线的构成并不限定于此。例如，也可在第2衬底50与存储单元阵列30中的最上层的导电层31(源极侧选择栅极)之间新添加作为源极线发挥作用的未图示的导电层SL。该导电层SL与第2衬底50之间电绝缘，各半导体柱身34的上端连接于导电层SL。
第2衬底50具有多个开口O21、O31。开口O21位于与第3区域A3在Z方向上重叠的位置。开口O31位于与第2区域A2在Z方向上重叠的位置。开口O31是“第1开口”的一例。开口O21是“第2开口”的一例。
开口O21散布在第3区域A3内。开口O21例如为从Z方向观察时呈矩形或圆形的贯通孔。开口O21在内部从外侧起依序具有氧化物层52、金属层53。金属层53将积层体20内的接触插塞27与外部电连接。金属层53的一部分成为露出到外部的焊垫P。氧化物层52例如为氧化硅。
开口O31例如为从Z方向观察时连续的贯通槽。开口O31连续地包围第1区域A1及第3区域A3的四周。开口O31可以包围第1区域A1及第3区域A3的四周的方式存在多个。
图4是将第1实施方式的半导体存储器100的开口O31附近放大后的剖视图。例如，开口O31位于从Z方向俯视观察时与间隔壁40重叠的位置。开口O31也可位于从Z方向俯视观察时与间隔壁40错开的位置。例如，开口O31也可位于从Z方向俯视观察时比间隔壁40更靠近第1区域A1侧的位置。开口O31内例如由氧化物51填充。氧化物51例如为氧化硅。
绝缘层61位于第2衬底50上。绝缘层62位于绝缘层61上。绝缘层61、62是保护积层体20的钝化膜。绝缘层61例如为氧化硅。绝缘层62例如为聚酰亚胺膜。
绝缘层61、62具有多个开口O22、O32。开口O22位于与第3区域A3在Z方向上重叠的位置。开口O32位于与第2区域A2在Z方向上重叠的位置。开口O32是“第3开口”的一例。开口O22位于与金属层53重叠的位置。从开口O22露出的金属层53成为焊垫P。开口O32位于从Z方向观察时与开口O31重叠的位置、或比与开口O31重叠的位置更靠近第1区域A1侧的位置。
随后，对第1实施方式的半导体存储器100的制造方法进行说明。半导体存储器100是将包含多个阵列芯片1的阵列晶圆W1与包含多个电路芯片2的电路晶圆W2贴合而制作的。阵列晶圆W1也被称为存储器晶圆。电路晶圆W2也被称为CMOS(Complementary Metal OxideSemiconductor，互补金属氧化物半导体)晶圆。
图5是阵列晶圆W1的特征部分的剖视图。图6是电路晶圆W2的特征部分的剖视图。阵列晶圆W1具有多个阵列芯片1(参照图1)。图5是一个阵列芯片1附近的放大图。图5所示的阵列晶圆W1的特征部分是与电路晶圆W2贴合前的状态，且与图1所示的阵列芯片1上下颠倒。电路晶圆W2具有多个电路芯片2(参照图1)。图6是电路晶圆W2的一个电路芯片2附近的放大图。
阵列晶圆W1是将积层体20B积层在衬底55上而获得的。积层体20B具有存储单元阵列30、焊垫26、接触插塞27、配线28及绝缘膜29。它们形成在各阶层中。阵列晶圆W1是通过反复执行所述各层的成膜、及利用光刻法等的加工而制作的。成膜方法及加工方法可使用公知的方法。绝缘膜29形成在存储单元阵列30、焊垫26、接触插塞27及配线28之间。在阵列晶圆W1的与衬底55相反一侧的贴合面S1，多个焊垫26A露出。
电路晶圆W2是将积层体20A积层在第1衬底10上而获得的。积层体20A具有焊垫21、接触插塞22、配线23及晶体管24。它们形成在各阶层中。电路晶圆W2是通过反复执行所述各层的成膜、及利用光刻法等的加工而制作的。成膜方法及加工方法可使用公知的方法。绝缘膜25形成在焊垫21、接触插塞22、配线23及晶体管24之间。在电路晶圆W2的与第1衬底10相反一侧的贴合面S2，多个焊垫21A露出。
随后，使阵列晶圆W1的贴合面S1与电路晶圆W2的贴合面S2彼此相对，通过机械压力将阵列晶圆W1与电路晶圆W2贴合。由此，将绝缘膜25A与绝缘膜25B接合。其次，在400℃下对阵列晶圆W1及电路晶圆W2进行退火。由此，将焊垫21A与焊垫26A贴合。
在将阵列晶圆W1与电路晶圆W2贴合后，将衬底55薄膜化。衬底55成为第2衬底50。衬底55例如通过化学机械研磨(CMP)而薄膜化。随后，如图7所示，在第2衬底50上形成开口O21、O31。开口O21与开口O31例如同时形成。在第2衬底50上积层氧化物层。氧化物层的一部分被覆开口O21及开口O31的内表面。之后，去除氧化物层中除了与开口O21、O31重叠的区域以外的部分。在开口O21内形成氧化物层56，并利用氧化物51将开口O31内填充。
随后，如图8所示，在氧化物层56上形成贯通孔，并积层金属层53。氧化物层56的剩余部分成为氧化物层52。随后，在第2衬底50之上依序积层绝缘层61、62。
随后，如图9所示，在绝缘层61、62上形成开口O22、O32。通过形成开口O22，金属层53的一部分露出，成为焊垫P。开口O32到达氧化物51。
图10是阵列晶圆W1与电路晶圆W2贴合而成的贴合体的从Z方向观察的俯视图。贴合体具有多个芯片区域Cp。芯片区域Cp例如包含第1区域A1、第2区域A2、第3区域A3。在邻接的芯片区域Cp之间存在第4区域A4。如图9所示，积层体20中，在第4区域A4内不存在焊垫21、26、接触插塞22、27、配线23、28等构造物，第4区域A4包含绝缘膜25、29。第4区域A4是将贴合体切割成多个芯片时的切割线。
随后，沿着切割线(第4区域A4)将贴合体切割，获得多个芯片。切割是从贴合体的第2衬底50侧开始进行的。通过以上步骤，制作本实施方式的半导体存储器100。此处所示出的制造步骤为一例，也可在各步骤之间插入其它步骤。
在切割贴合体时，存在贴合体中意外地产生裂缝的情况。另外，除切割过程中以外，也存在切割时贴合体中产生的形变在退火等后续步骤中导致产生裂缝的情况。如果裂缝到达半导体存储器100的存储区域、控制区域，则该芯片不良。裂缝容易沿着不同种类的材料界面扩展。例如，裂缝沿着绝缘膜25中的氧化硅膜与碳氮化硅膜的界面扩展。
由于第1实施方式的半导体存储器100在第2衬底50上形成有开口O31，所以能够抑制裂缝到达半导体存储器100的存储区域、控制区域。裂缝容易沿着不同种类的材料界面扩展，且容易沿着开口O31及间隔壁40扩展。切割时沿着第4区域A4中的氧化硅膜与碳氮化硅膜的界面在XY面内产生的裂缝通过开口O31及间隔壁40而转向Z方向。通过利用开口O31及间隔壁40使裂缝在Z方向上前进，能够抑制裂缝到达半导体存储器100的存储区域、控制区域。
(第1变化例)
对第1实施方式的半导体存储器100的第1变化例进行说明。图11是将第1变化例的半导体存储器的开口O31附近放大后的剖视图。第1变化例的半导体存储器中除以下说明以外的构成与第1实施方式的半导体存储器100相同。
第2衬底50具有开口O31。开口O31的内表面由氧化物层57被覆。在氧化物层57的内侧，存在由氧化物层57及绝缘层61所围成的空隙Sp。如图11所示，绝缘层61、62也可不具有多个开口O22、O32。绝缘层61、62也可与第1实施方式同样地具有多个开口O22、O32。
当在开口O21内积层氧化物层56时，能同时积层氧化物层57。当开口O31的宽度足够大于要成膜的氧化物层57的厚度时，通过成膜氧化物层57来形成空隙Sp。当开口O31内填充着氧化物时，通过去除所填充的氧化物的一部分，来获得氧化物层57及空隙Sp。
通过第1变化例的构成，也能够与第1实施方式同样地抑制裂缝扩展到半导体存储器的存储区域、控制区域。
(第2变化例)
对第1实施方式的半导体存储器100的第2变化例进行说明。图12是将第2变化例的半导体存储器的开口O31附近放大后的剖视图。第2变化例的半导体存储器中除以下说明以外的构成与第1实施方式的半导体存储器100相同。
第2衬底50具有开口O31。开口O31的内表面从内侧起依序由氧化物层58、金属层59被覆。氧化物层58被覆在开口O31的侧壁。金属层59被覆在开口O31的底面及侧壁。如图12所示，金属层59的内侧可由绝缘层61、62被覆。从Z方向观察时，开口O31跨及多个间隔壁40。
当在开口O21内形成氧化物层52及金属层53时，可同时制作氧化物层58及金属层59。
通过第2变化例的构成，也能够与第1实施方式同样地抑制裂缝扩展到半导体存储器的存储区域、控制区域。
(第3变化例)
对第1实施方式的半导体存储器100的第3变化例进行说明。图13是第3变化例的半导体存储器的从Z方向观察的俯视图。第3变化例的半导体存储器中除以下说明以外的构成与第1实施方式的半导体存储器100相同。
第1实施方式的开口O31是连续地包围第1区域A1及第3区域A3的四周的贯通槽，与此相对，第3变化例的开口O31A散布在第1区域A1及第3区域A3的四周。从Z方向观察时，多个开口O31A包围第1区域A1及第3区域A3。包围第1区域A1及第3区域A3的开口群可存在多个。
通过第3变化例的构成，也能够与第1实施方式同样地抑制裂缝扩展到半导体存储器的存储区域、控制区域。
(第4变化例)
对第1实施方式的半导体存储器100的第4变化例进行说明。图14是第4变化例的半导体存储器的剖视图。图14所示的半导体存储器是多个芯片集成而成的晶圆，处于切割加工前的状态。图14所示的半导体存储器与图9的不同点在于，在第4区域A4形成着开口O41。对于与图9相同的构成，标注相同符号并省略说明。
开口O41位于第4区域A4。开口O41是“第4开口”的一例。开口O41贯穿第2衬底50、绝缘层61、绝缘层62，到达积层体20。开口O41例如沿着第4区域A4延伸。开口O41可与开口O31、O32同时形成。开口O41也可与最靠近第4区域A4侧的开口O31、O32相连。
通过第4变化例的构成，也能够与第1实施方式同样地抑制裂缝扩展到半导体存储器的存储区域、控制区域。另外，由于切割线上不存在第2衬底50，所以能够进一步抑制切割时的裂缝。
对本发明的几个实施方式进行了说明，但这些实施方式是作为示例而提出的，并未意图限定发明的范围。这些实施方式可通过其它各种方式加以实施，可在不脱离发明主旨的范围内进行各种省略、置换、变更。这些实施方式及其变化包含在发明的范围及主旨中，同样包含在权利要求书中记载的发明及其均等的范围内。
[符号的说明]
1:阵列芯片
2:电路芯片
10:第1衬底
20,20A,20B:积层体
21,21A,26,26A,P:焊垫
22,27:接触插塞
23,28:配线
24:晶体管
25,29:绝缘膜
30:存储单元阵列
40:间隔壁
50:第2衬底
51:氧化物
52,56,57,58:氧化物层
53,59:金属层
55:衬底
61,62:绝缘层
100:半导体存储器
A1:第1区域
A2:第2区域
A3:第3区域
A4:第4区域
CL:柱状体
Cp:芯片区域
MC:存储单元
O21,O22,O31,O31A,O32,O41:开口
S,S1,S2:贴合面
Sp:空隙
W1:阵列晶圆
W2:电路晶圆。

Claims (14)

1.一种半导体存储装置，其具备：
第1芯片，具有第1衬底、设置在所述第1衬底上之晶体管、及设置在所述晶体管上方的第1焊垫；及
第2芯片，具有设置在所述第1焊垫上的第2焊垫、设置在所述第2焊垫上方且具有多个存储单元的存储单元阵列、及设置在所述存储单元阵列上方的第2衬底，且贴合于所述第1芯片；
从与所述第1衬底正交的第1方向观察时，所述第1芯片及第2芯片具有：第1区域，具有所述存储单元阵列；及第2区域，包围所述第1区域的四周，且具有从所述第1衬底到达所述第2衬底的间隔壁；
所述第2衬底在所述第2区域中具有贯通所述第2衬底的第1开口。
2.根据权利要求1所述的半导体存储装置，其中所述第1芯片及所述第2芯片还具有第3区域，该第3区域从所述第1方向观察时位于所述第1区域与所述第2区域之间，且具有外部连接焊垫，
所述第2衬底在所述第3区域中具有贯通所述第2衬底的第2开口。
3.根据权利要求1所述的半导体存储装置，其中从所述第1方向观察时，所述第1开口连续地包围所述第1区域。
4.根据权利要求1所述的半导体存储装置，其中所述第2衬底具有多个所述第1开口，
从所述第1方向观察时，多个所述第1开口分别包围所述第1区域。
5.根据权利要求1至4中任一项所述的半导体存储装置，其中所述第1开口由氧化物填充。
6.根据权利要求2所述的半导体存储装置，其中所述第1开口由氧化物填充，
所述第2开口由与所述第1开口相同的氧化物填充。
7.根据权利要求1至4中任一项所述的半导体存储装置，其还具备被覆所述第1开口的内表面的氧化物层。
8.根据权利要求7所述的半导体存储装置，其还具备被覆所述氧化物层的内表面的金属层。
9.根据权利要求1至4中任一项所述的半导体存储装置，其具有多个所述间隔壁，
从所述第1方向观察时，所述第1开口跨及多个所述间隔壁。
10.根据权利要求1至4中任一项所述的半导体存储装置，其中所述第2衬底的厚度比所述第1衬底的厚度薄。
11.根据权利要求1至4中任一项所述的半导体存储装置，其在所述第2衬底上还具备绝缘层，
所述绝缘层在从所述第1方向观察时与所述第1开口重叠的位置、或比与所述第1开口重叠的位置更靠近所述第1区域侧的位置具备第3开口。
12.根据权利要求1至4中任一项所述的半导体存储装置，其中所述第1芯片及所述第2芯片具有多个包含所述第1区域及所述第2区域的芯片区域，
所述第2衬底在邻接的所述芯片区域之间具有具备第4开口的第4区域。
13.一种半导体存储装置的制造方法，其是在第1衬底上形成晶体管及第1焊垫来制作第1芯片，
在第2衬底上形成存储单元阵列及第2焊垫来制作第2芯片，
以使所述第1焊垫与所述第2芯片贴合的方式将所述第1芯片与所述第2芯片贴合，
在所述第2衬底的第2区域及第3区域的各区域中同时形成贯通所述第2衬底的第1开口及第2开口，
所述第2区域是包围具有所述存储单元阵列的第1区域的四周，且具有从所述第1衬底到达所述第2衬底的间隔壁的区域，
所述第3区域是位于所述第1区域与所述第2区域之间的区域。
14.根据权利要求13所述的半导体存储装置的制造方法，其成膜氧化物层，所述氧化物层被覆所述第1开口及所述第2开口的内表面。
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US20220352044A1 (en) * 2021-04-22 2022-11-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method of the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018148071A (ja) * 2017-03-07 2018-09-20 東芝メモリ株式会社 記憶装置
JP2018163970A (ja) 2017-03-24 2018-10-18 東芝メモリ株式会社 半導体装置及びその製造方法
JP2020038746A (ja) * 2018-09-06 2020-03-12 キオクシア株式会社 半導体記憶装置
JP2020047810A (ja) * 2018-09-20 2020-03-26 キオクシア株式会社 半導体記憶装置及びその製造方法
KR20200094529A (ko) * 2019-01-30 2020-08-07 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 제조방법
JP2020141100A (ja) * 2019-03-01 2020-09-03 キオクシア株式会社 半導体装置およびその製造方法
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