WO2016075791A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

Info

Publication number
WO2016075791A1
WO2016075791A1 PCT/JP2014/080072 JP2014080072W WO2016075791A1 WO 2016075791 A1 WO2016075791 A1 WO 2016075791A1 JP 2014080072 W JP2014080072 W JP 2014080072W WO 2016075791 A1 WO2016075791 A1 WO 2016075791A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
rewiring
metal film
cap
semiconductor device
Prior art date
Application number
PCT/JP2014/080072
Other languages
English (en)
French (fr)
Inventor
和義 前川
河野　祐一
Original Assignee
ルネサスエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ルネサスエレクトロニクス株式会社 filed Critical ルネサスエレクトロニクス株式会社
Priority to EP14890461.8A priority Critical patent/EP3220410A4/en
Priority to JP2015545230A priority patent/JPWO2016075791A1/ja
Priority to PCT/JP2014/080072 priority patent/WO2016075791A1/ja
Priority to CN201480027415.6A priority patent/CN105793964A/zh
Priority to US14/891,319 priority patent/US10083924B2/en
Priority to TW104135663A priority patent/TW201630075A/zh
Publication of WO2016075791A1 publication Critical patent/WO2016075791A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0218—Structure of the auxiliary member
    • H01L2224/02181—Multilayer auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02185—Shape of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0219—Material of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03466—Conformal deposition, i.e. blanket deposition of a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/035—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05007—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05176—Ruthenium [Ru] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0518—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H01L2224/05566—Both on and outside the bonding interface of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4502—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45664—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48664—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48863—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48864—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/07—Polyamine or polyimide
    • H01L2924/07025—Polyimide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a rewiring composed of a metal film on a plurality of wiring layers formed on a main surface of a semiconductor substrate and a manufacturing method thereof. It is related to effective technology.
  • a multilayer wiring is formed of a metal film mainly composed of Cu (copper) or Al (aluminum) on a semiconductor substrate on which semiconductor elements such as CMIS (Complementary Metal Insulator Semiconductor) transistors are formed.
  • a final passivation film is formed on the multilayer wiring.
  • Patent Document 1 a rewiring mainly composed of Cu is formed on a final passivation film, and an electrode pad and a rewiring formed on the uppermost wiring under the final passivation film, A technique for electrically connecting the two is disclosed.
  • a wire 20 is connected to a pad 18 formed so as to partially cover the upper and side surfaces of the rewiring 15 containing Cu as a main component.
  • Patent Document 2 Japanese Patent Laying-Open No. 2012-4210
  • Patent Document 3 a barrier metal having a protruding portion 9 in which a rewiring layer 6 made of an aluminum alloy formed on a passivation film 4 is extended on the passivation film 6. It is disclosed that migration and corrosion of the rewiring layer 6 are suppressed by completely covering with the film 8.
  • a semiconductor device having a rewiring (semiconductor integrated circuit device) studied by the inventors of the present application includes a semiconductor chip, a wire connected to the semiconductor chip, and a sealing body that seals the semiconductor chip and the wire.
  • the semiconductor chip includes a semiconductor element, a rewiring mainly composed of Cu electrically connected to the semiconductor element, and a wiring formed of a multilayer wiring layer that electrically connects the semiconductor element and the rewiring.
  • the rewiring is connected to a pad electrode that is a part of the wiring formed by the uppermost wiring layer of the multilayer wiring layer.
  • the rewiring is electrically connected to the pad electrode through the opening of the surface protective film and the first organic protective film provided to expose the pad electrode.
  • the upper surface and the side surface of the rewiring are covered with the second organic protective film, and the second organic protective film has an opening exposing the external pad electrode formed on the upper surface of the rewiring. The wire is connected to the rewiring.
  • a plurality of rewirings are formed on the semiconductor chip, the minimum linewidth of rewiring is 12 ⁇ m, and the minimum interval between adjacent rewirings is 15 ⁇ m.
  • a seed layer made of a metal film (for example, a Cr film) for forming the rewiring is provided on the lower surface of the rewiring, but the upper surface and the side surface of the rewiring are in contact with the second organic protective film. .
  • HAST Highly Accelerated temperature and humidity Stress Test
  • the first and second organic protective films covering the rewiring made of Cu are made of a polyimide film and contain moisture and halogen ions.
  • Cu ions ionized Cu
  • the minimum interval (15 ⁇ m) between adjacent rewirings is large, there is a region where a high voltage is applied and a high electric field is applied between adjacent rewirings, and Cu dendritic precipitation occurs in this region. It turns out that it has occurred.
  • An object of the present invention is to provide a technique capable of improving reliability in a semiconductor device having rewiring.
  • a semiconductor device includes a pad electrode formed in an uppermost layer of a plurality of wiring layers, a protective film having an opening on the pad electrode, a base metal film formed on the protective film, and a base metal A rewiring formed on the film; and a cap metal film formed to cover an upper surface and a side surface of the rewiring. Then, in the region outside the rewiring, between the cap metal film and the protective film formed on the side wall of the rewiring, a base metal film different from the rewiring and a different material from the rewiring are used. A cap metal film is formed, and the base metal film and the cap metal film are in direct contact with each other in a region outside the rewiring.
  • the reliability of a semiconductor device having rewiring can be improved.
  • FIG. 1 is a circuit block diagram of a semiconductor device according to a first embodiment of the present invention.
  • 1 is an overall plan view of a semiconductor chip on which a semiconductor device according to a first embodiment of the present invention is formed. It is a top view which expands and shows a part of FIG.
  • FIG. 4 is a cross-sectional view taken along line AA in FIG. 3.
  • FIG. 6 is a cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof.
  • FIG. 6 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5;
  • FIG. 7 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6;
  • FIG. 8 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;
  • FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;
  • FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;
  • FIG. 11 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10;
  • FIG. 12 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11;
  • FIG. 13 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12;
  • 11 is a cross-sectional view of the semiconductor device that is Modification 1 during the manufacturing process.
  • FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;
  • FIG. 11 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10
  • FIG. 11 is a cross-sectional view of a semiconductor device that is a second modification during the manufacturing process.
  • FIG. FIG. 11 is a cross-sectional view of the semiconductor device that is Modification Example 3 during the manufacturing process.
  • FIG. 11 is a cross-sectional view of the semiconductor device that is Modification Example 4 during the manufacturing process. It is sectional drawing in the manufacturing process of the semiconductor device which is a comparative example.
  • FIG. 19 is a cross-sectional view of the semiconductor device as the comparative example following FIG. 18 during the manufacturing process thereof.
  • FIG. 10 is a sectional view of the semiconductor device of Second Embodiment during the manufacturing process thereof.
  • FIG. 21 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 20;
  • FIG. 16 is a cross-sectional view of the semiconductor device that is Modification Example 5 during the manufacturing process.
  • the constituent elements are not necessarily indispensable unless otherwise specified or apparently indispensable in principle.
  • the shapes when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).
  • hatching may be omitted even in a cross-sectional view for easy understanding of the drawings. Further, even a plan view may be hatched to make the drawing easy to see.
  • the semiconductor device semiconductor integrated circuit device
  • the semiconductor device includes, for example, a plurality of semiconductor elements, a plurality of layers of wiring (multilayer wiring) formed above the plurality of semiconductor elements, and a plurality of semiconductor elements.
  • FIG. 1 is a circuit block diagram of a semiconductor device.
  • the semiconductor device includes, for example, an input / output (I / O) circuit, an analog circuit, a CMIS-logic circuit, a power MIS circuit, and a memory circuit formed on the device surface of the semiconductor chip 1A. Configure the device.
  • the CMIS-logic circuit is composed of, for example, a CMIS transistor having an operating voltage of 1 to 3 V, and the I / O circuit and the memory circuit are, for example, operated voltages of 1 to 3 V and 5 It is composed of ⁇ 8V CMIS transistors.
  • the CMIS transistor having an operating voltage of 1 to 3 V includes a first n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a first gate insulating film and a first p-channel type having a first gate insulating film. It consists of MISFET.
  • the CMIS transistor having an operating voltage of 5 to 8 V is composed of a second n-channel MISFET having a second gate insulating film and a second p-channel MISFET having a second gate insulating film. Is done.
  • the film thickness of the second gate insulating film is configured to be larger than the film thickness of the first gate insulating film.
  • the MISFET is referred to as a MIS transistor.
  • the analog circuit is composed of, for example, a CMIS transistor (or bipolar transistor) having an operating voltage of 5 to 8 V, a resistor element, and a capacitor element
  • the power MIS circuit is a CMIS transistor having an operating voltage of 5 to 8 V, for example. It is composed of a high voltage MIS transistor (high voltage element) having an operating voltage of 20V to 100V.
  • the high-breakdown-voltage MIS transistor includes, for example, a third n-channel MISFET having a third gate insulating film, a third p-channel MISFET having a third gate insulating film, or both.
  • a voltage of 20 V to 100 V is applied between the gate electrode and the drain region or between the gate electrode and the source region, the thickness of the third gate insulating film is the thickness of the second gate insulating film. It is configured to be thicker.
  • FIG. 2 is an overall plan view showing an example of the semiconductor chip 1A
  • FIG. 3 is an enlarged plan view of a region surrounded by a broken line X in FIG. 2
  • FIG. 4 is a cross-sectional view taken along line AA in FIG. It is.
  • FIG. 2 shows an example of the layout of the redistribution lines RM, RMV, and RMS formed on the device surface of the semiconductor chip 1A.
  • the redistribution lines RM, RMV, and RMS have a film thickness and a thickness that are larger than those of a plurality of layers of the semiconductor chip 1A (the first layer Al wiring 5, the second layer Al wiring 7, and the third layer Al wiring 9 shown in FIG. 4). Since both the wiring widths are large, the impedance is very low compared to a multi-layer wiring.
  • the rewiring RM, RMV, and RMS are used as, for example, a rewiring RM for signal input / output, a rewiring RMV for supplying power (Vcc, GND), and a rewiring RMS for connection between internal circuits.
  • a plurality of rewiring RMs constituting external connection terminals of the semiconductor device are arranged in the periphery of the semiconductor chip 1A.
  • An external pad electrode 18 is formed at one end of each rewiring RM constituting the external connection terminal of the semiconductor device, and the other end is a pad formed in the uppermost layer wiring as shown in FIGS. It is connected to the electrode 9a.
  • the external pad electrodes 18 are not particularly limited, but are arranged in a line along each side of the semiconductor chip 1A. Needless to say, the external pad electrodes 18 may be arranged in a zigzag manner or in three or more rows along each side of the semiconductor chip 1A. That is, the rewiring RM is, for example, a signal input / output rewiring configuring the input / output (I / O) circuit of FIG.
  • the rewiring RMV shown in FIG. 2 is a rewiring for supplying power (Vcc, GND).
  • An external pad electrode 18 is formed at one end of the rewiring RMV, and the other end is connected to a pad electrode 9a formed in the power supply wiring in the semiconductor chip 1A. Therefore, the power supply (from the outside of the semiconductor chip 1A ( Vcc, GND) voltage can be supplied to the plurality of power supply wirings in the semiconductor chip 1A with low impedance.
  • the rewiring RMS shown in FIG. 2 is used as a wiring for connecting between circuits or elements formed in the semiconductor chip 1A. Therefore, the external pad electrode 18 is not formed on the rewiring RMS. Both ends of the rewiring RMS are connected to pad electrodes 9a formed on the wiring.
  • FIG. 3 is an enlarged plan view of two adjacent signal input / output rewiring RMs. Since two adjacent rewirings RM have the same planar shape, the rewiring RM located in the upper part of the drawing will be described as an example.
  • the rewiring RM extends in the X direction on the paper surface, and is electrically connected at one end to the pad electrode 9a of the wiring 9 extending in the X direction on the paper surface.
  • An external pad electrode 18 is formed at the other end of the rewiring RM.
  • the rewiring RM has a first plane pattern P1, and the base metal film UM and the cap metal film CM have a second plane pattern P2.
  • the first plane pattern P1 and the second plane pattern P2 are similar, and the second plane pattern P2 has a shape obtained by enlarging the first plane pattern P1.
  • An overhang PP formed of the base metal film UM and the cap metal film CM is disposed around the entire rewiring RM. That is, when the first plane pattern P1 is enlarged by the width S3 of the projecting portion PP, the second plane pattern P2 is obtained.
  • the minimum wiring width L of the rewiring RM is, for example, 12 ⁇ m, the minimum wiring interval S1 between adjacent rewiring RMs is 15 ⁇ m, the minimum spacing S2 between adjacent protruding portions PP is 10 ⁇ m, and the protruding amount S3 of the protruding portions PP. Is 2.5 ⁇ m.
  • the overhang amount S3 of the overhang portion PP is the same over the entire periphery of the rewiring RM, but the second plane pattern P2 is shifted from the first plane pattern P1, for example, by ⁇ in the X direction. Also good.
  • the second plane pattern P2 is shifted by ⁇ in the X direction with respect to the first plane pattern P1
  • a p-type well 2P, an n-type well 2N, and an element isolation trench 3 are formed in a semiconductor substrate 1P made of p-type single crystal silicon.
  • a semiconductor substrate 1P made of p-type single crystal silicon.
  • an element isolation insulating film 3a made of a silicon oxide film is buried.
  • An n-channel MIS transistor (Qn) is formed in the p-type well 2P.
  • the n-channel MIS transistor (Qn) is formed in the active region defined by the element isolation trench 3, and has a source region ns and a drain region nd formed in the p-type well 2P and a gate insulation on the p-type well 2P. And a gate electrode ng formed through the film ni.
  • a p-channel MIS transistor (Qp) is formed in the n-type well 2N, and a gate is formed on the source region ps and drain region pd and a gate insulating film pi on the n-type well 2N.
  • an electrode pg is formed in the p-type well 2P.
  • a wiring made of a metal film for connecting the semiconductor elements is formed above the n-channel MIS transistor (Qn) and the p-channel MIS transistor (Qn).
  • Wirings connecting semiconductor elements generally have a multilayer wiring structure of about 3 to 10 layers, but FIG. 4 is composed of a metal film mainly composed of an Al alloy as an example of the multilayer wiring. Three wiring layers (first layer Al wiring 5, second layer Al wiring 7, and third layer Al wiring 9) are shown.
  • the wiring layer is used to collectively represent a plurality of wirings formed in each wiring layer.
  • the second wiring layer is thicker than the first wiring layer, and the third wiring layer is thicker than the second wiring layer.
  • inter-layer insulating films 4, 6, and 8 made of silicon oxide films and plugs p1, p2, and p3 that electrically connect the three layers of wiring, respectively. Is formed.
  • the interlayer insulating film 4 is formed on the semiconductor substrate 1P so as to cover the semiconductor element, for example, and the first layer Al wiring 5 is formed on the interlayer insulating film 4.
  • the first layer Al wiring 5 is electrically connected to the source region ns, the drain region nd, and the gate electrode ng of the n-channel MIS transistor (Qn), which is a semiconductor element, via a plug p1 formed in the interlayer insulating film 4, for example.
  • the first-layer Al wiring 5 is electrically connected to the source region ps, drain region pd, and gate electrode pg of the p-channel type MIS transistor (Qp), which is a semiconductor element, via a plug p1 formed in the interlayer insulating film 4. Connected to.
  • the connection between the gate electrodes ng and pg and the first layer Al wiring 5 is not shown.
  • the second layer Al wiring 7 is electrically connected to the first layer Al wiring 5 via a plug p2 formed in the interlayer insulating film 6, for example.
  • the third layer Al wiring 9 is electrically connected to the second layer Al wiring 7 via a plug p3 formed in the interlayer insulating film 8, for example.
  • the plugs p1, p2, and p3 are made of a metal film, for example, a W (tungsten) film.
  • a multilayer wiring (three-layer wiring) is formed of a metal film mainly composed of Cu by a chemical mechanical polishing method (CMP method)
  • the wiring may be formed by a dual damascene method in which a wiring and a plug are integrally formed.
  • the interlayer insulating films 4, 6, and 8 are made of a silicon oxide film (SiO 2 ), and include a silicon oxide film containing carbon (SiOC film), a silicon oxide film containing nitrogen and carbon (SiCON film), and fluorine. Of course, it may be composed of a single layer film or a laminated film of a silicon oxide film (SiOF film).
  • the third layer Al wiring 9 which is the uppermost wiring layer of the multilayer wiring, as a final passivation film, for example, a single layer film such as a silicon oxide film or a silicon nitride film, or a surface composed of these two layer films
  • a protective film (protective film, insulating film) 10 is formed.
  • the third layer Al wiring 9 is not limited to the pad electrode 9a, and may be, for example, a wiring integrally formed with the pad electrode 9a, a wiring not connected to the pad electrode 9a, or the like.
  • the wiring that is not connected to the pad electrode 9a is used as a wiring that electrically connects between semiconductor elements or circuits and constitutes a semiconductor integrated circuit.
  • a base insulating film (organic protective film, insulating film) 11 which is an insulating film having an opening 11a above the pad opening 10a is formed. Further, a rewiring RM electrically connected to the pad electrode 9 a through the opening 11 a of the base insulating film 11 and the pad opening 10 a of the surface protective film 10 is formed on the base insulating film 11.
  • the opening 11a is larger than the pad opening 10a, and the upper surface (surface) of the surface protection film 10 that defines the pad opening 10a is exposed from the opening 11a on the entire circumference of the pad opening 10a.
  • the rewiring RM is formed inside the pad opening 10a and the opening 11a so as to completely fill the pad opening 10a and the opening 11a, and further extends on the base insulating film 11.
  • the base metal film UM is interposed between the pad electrode 9a and the rewiring RM.
  • the base metal film UM is in contact with and electrically connected to the pad electrode 9 a, and the side surface (side wall) and the top surface of the surface protective film 10 in the pad opening 10 a of the surface protective film 10 and the opening 11 a of the base insulating film 11. , And along the side surface (side wall) of the base insulating film 11, and further extends to the upper surface of the base insulating film 11.
  • the base metal film UM has an upper surface and a lower surface, the upper surface is in contact with the rewiring RM, and the lower surface is in contact with the pad electrode 9a, the surface protective film 10, and the base insulating film 11.
  • the base metal film UM is composed of a base barrier film having a three-layer structure. From the first base barrier film UM1, the second base barrier film UM2, and the third base barrier film UM3 from the pad electrode 9a side. Become. Therefore, the upper surface of the base metal film UM means the upper surface of the third base barrier film UM3, and the lower surface means the lower surface of the first base barrier film UM1.
  • the first base barrier film UM1, the second base barrier film UM2, and the third base barrier film UM3 are composed of, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and a titanium (Ti) film in this order.
  • the film thickness is 10 nm, 50 nm, and 10 nm in this order. This film thickness is the film thickness on the upper surface of the base insulating film 11.
  • the rewiring RM has an upper surface, a lower surface, and side surfaces, and the lower surface of the rewiring RM is in contact with the upper surface of the base metal film UM.
  • the rewiring RM is a copper film containing copper (Cu) as a main component, and has a laminated structure of a seed film RM1 and a plating film RM2. Therefore, the lower surface of the rewiring RM means the lower surface of the seed film RM1, and the upper surface means the upper surface of the plating film RM2. Further, the side surface (side wall) of the rewiring RM means the side surface (side wall) of the stacked structure of the seed film RM1 and the plating film RM2.
  • the film thicknesses of the seed film RM1 and the plating film RM2 are 250 nm and 6 ⁇ m, respectively.
  • the rewiring RM is a film more than 10 times as thick as the third layer Al wiring 9, in other words, the wiring 9 on which the pad electrode 9a is formed.
  • This is a low-resistance wiring having a thickness. That is, the film thickness of the rewiring RM is larger than the film thickness of the wiring 9 on which the pad electrode 9a is formed. Desirably, the film thickness of the rewiring RM is not less than 10 times the film thickness of the wiring 9 on which the pad electrode 9a is formed.
  • the cap metal film CM is formed in contact with the upper surface and the side surface of the rewiring RM so as to completely cover the rewiring RM.
  • the cap metal film CM covers the entire upper surface and the entire side surface of the rewiring RM.
  • the cap metal film CM completely covers the side surface (side wall) of the seed film RM1 and the side surface (side wall) of the plating film RM2 constituting the rewiring RM.
  • the cap metal film CM has an upper surface and a lower surface, and the lower surface is in contact with the upper surface of the rewiring RM and the side surface of the rewiring RM, and in a region outside the rewiring RM (a region where the rewiring RM is not formed). In direct contact with the upper surface of the underlying metal film UM.
  • the base metal film UM and the cap metal film CM extend from the side surface of the rewiring RM (strictly, the lower end portion of the side surface of the rewiring RM) to the region outside the rewiring RM (region where the rewiring RM is not formed).
  • An overhang portion PP is provided, and the upper surface of the base metal film UM and the lower surface of the cap metal film CM are in direct contact with each other in the overhang portion PP.
  • the overhang amount S3 of the overhang portion PP is larger than the film thickness of the cap metal film CM formed on the side surface (side wall) of the rewiring RM, for example, 2.5 ⁇ m.
  • the ends of the base metal film UM and the cap metal film CM which are the tips of the overhanging portions PP, are formed on the rewiring RM more than the cap metal film CM formed on the side surface (side wall) of the rewiring RM.
  • the overhang portion PP is formed over the entire circumference of the rewiring RM in plan view.
  • the overhang amount S3 is the width of the overhang portion PP and means the distance from the end of the rewiring RM to the end of the base metal film UM or the cap metal film CM in the region outside the rewiring RM.
  • the cap metal film CM has a laminated structure of the first cap barrier film CM1 and the second cap barrier film CM2, and the lower surface of the first cap barrier film CM1 is in contact with the upper surface and the side surface of the rewiring RM. Further, it is in contact with the upper surface of the base metal film UM (more precisely, the upper surface of the third base barrier film UM3).
  • the lower surface of the cap metal film CM means the lower surface of the first cap barrier film CM1, and the upper surface means the upper surface of the second cap barrier film CM2.
  • the first cap barrier film CM1 is made of a titanium (Ti) film and has a film thickness of 50 nm.
  • the second cap barrier film CM2 is made of a palladium (Pd) film, and the film thickness thereof is 175 nm. This film thickness is the film thickness on the upper surface of the rewiring RM.
  • the third base barrier film UM3 constituting the base metal film UM and the first cap barrier film CM1 constituting the cap metal film CM are made of a film made of the same material (specifically, a titanium (Ti) film).
  • Ti titanium
  • the overhang portion PP has a structure in which the cap metal film CM is laminated on the base metal film UM, the film thickness of the base metal film UM and the cap metal in the overhang portion PP in the region outside the rewiring RM.
  • the sum of the film CM and the film thickness is larger than the film thickness of the base metal film UM sandwiched between the rewiring RM and the base insulating film 11.
  • the sum of the film thickness of the base metal film UM and the film thickness of the first cap barrier film CM1 in the overhanging portion PP in the region outside the rewiring RM is the base between the rewiring RM and the base insulating film 11 It is thicker than the film thickness of the metal film UM.
  • a protective film 12 is formed so as to entirely cover the rewiring RM.
  • the protective film 12 has an opening 12a that partially exposes the upper surface of the rewiring RM (more precisely, the upper surface of the cap metal film CM and the upper surface of the second cap barrier film CM2).
  • the portion is an external pad electrode 18.
  • both the base insulating film 11 and the protective film 12 can be made of an organic film such as a polyimide resin, a benzocyclobutene resin, an acrylic resin, an epoxy resin, or a silicon resin.
  • the base metal film UM and the cap metal film CM prevent the copper (Cu) film constituting the rewiring RM from moving (diffusing) to the outside as copper ions. What is the rewiring RM? It is composed of different materials (different materials). Further, the base metal film UM and the cap metal film CM do not include a copper (Cu) film.
  • the signal input / output rewiring RM has been described as an example, but the power supply rewiring RMV and the rewiring RMS for connecting between circuits or elements have the same structure as the rewiring RM.
  • the power supply rewiring RMV and the rewiring RMS for connecting between circuits or elements have the same structure as the rewiring RM.
  • the rewiring RM made of a copper film covers the lower surface of the rewiring RM, covers the base metal film UM made of a material different from the rewiring RM, and covers the upper surface and side surfaces of the rewiring RM and is made of a material different from the rewiring RM. It is completely surrounded by the cap metal film CM. In the region outside the rewiring RM, the base metal film UM and the cap metal film CM have an overhang portion PP, and the base metal film UM and the cap metal film CM are in direct contact with each other in the overhang portion PP. ing.
  • the copper constituting the redistribution line RM moves (diffuses) to an area outside the redistribution line RM and is adjacent to each other. It is possible to prevent a breakdown voltage deterioration or a short circuit between the rewiring RMs. Further, since moisture, halogen ions, etc. contained in the polyimide film constituting the base insulating film 11 or the protective film 12 can be prevented from entering the rewiring RM made of the copper film, oxidation of the copper film can be prevented, It is possible to prevent a breakdown voltage deterioration or a short circuit between adjacent rewirings RM.
  • the protruding amount of the protruding portion is larger than the film thickness of the cap metal film CM covering the side surface of the rewiring RM. Even when the overhang amount is reduced due to the deviation of the second pattern with respect to the first pattern, since the reduced overhang amount is larger than the film thickness of the cap metal film CM covering the side surface of the rewiring RM, there is a manufacturing variation. Even in this case, it is possible to prevent a breakdown voltage deterioration or a short circuit between adjacent rewirings RM. Oxidation of the copper film constituting the rewiring RM can be prevented.
  • the base barrier film that is the upper surface of the base metal film UM and the cap barrier film that is the lower surface of the cap metal film are films made of the same material. Therefore, the adhesion between the base metal film UM and the cap metal film CM in the overhanging portion can be improved, and the copper constituting the rewiring RM can be sufficiently prevented from moving (diffusing) to the region outside the rewiring RM. Therefore, it is possible to prevent a breakdown voltage deterioration or short circuit between adjacent rewiring RMs and oxidation of the rewiring RMs.
  • the overhang portion PP is formed over the entire circumference of the rewiring RM, it is possible to prevent breakdown voltage deterioration or short circuit between the rewiring RM adjacent in all directions and oxidation of the rewiring. it can.
  • the rewiring RM is completely wrapped by the base metal film UM having the second planar pattern P2 larger than the first planar pattern P1 of the rewiring RM made of a copper film and the cap metal film CM, and the rewiring RM In the outer region, the upper surface of the base metal film UM and the lower surface of the cap metal film CM are in direct contact.
  • the rewiring RM can be prevented from being oxidized, and a breakdown voltage deterioration or a short circuit between the adjacent rewirings RM can be prevented.
  • the copper film constituting the rewiring RM is oxidized and copper ions are generated, the copper ions can be prevented from moving (diffusing) outside the rewiring RM.
  • the second plane pattern P2 is larger than the first plane pattern P1 on the entire circumference of the first plane pattern P1, it is possible to prevent breakdown voltage deterioration or short circuit between the rewiring RMs adjacent in all directions. it can.
  • Method for Manufacturing Semiconductor Device Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. The method for manufacturing a rewiring, which is a feature of the first embodiment, will be mainly described. The rewiring manufacturing method corresponds to the cross section shown in FIG.
  • 5 to 13 are cross-sectional views of the semiconductor device according to the first embodiment during the manufacturing process.
  • FIG. 5 shows a process of preparing a semiconductor substrate on which a plurality of wiring layers and pad electrodes are formed.
  • the semiconductor substrate 1P After the p-channel type MIS transistor (Qp) and the n-channel type MIS transistor (Qn) are formed, wiring composed of a plurality of wiring layers is formed. Specifically, as described with reference to FIG. 4, three wiring layers (first layer Al wiring 5, second layer Al wiring 7, and third layer Al wiring 9) are formed.
  • a surface protective film 10 is formed above the third layer Al wiring 9, and the surface protective film 10 has a pad opening 10a and is a third layer Al that is the uppermost wiring layer. A portion of the wiring 9 exposed from the pad opening 10a is a pad electrode 9a.
  • the cross-sectional structure shown in FIG. 5 is as described in FIG.
  • FIG. 6 shows a process of forming the base insulating film 11, the base metal film UM, and the seed film RM1.
  • a base insulating film 11 is formed on the surface protective film 10, and a photosensitive polyimide resin is used as the base insulating film 11.
  • Photosensitive polyimide is applied onto the surface protective film 10 and exposed to expose the pad openings 10a and the pad electrodes 9a, and then cured and cured. That is, the base insulating film 11 having the opening 11a larger than the pad opening 10a and the pad electrode 9a is formed.
  • a base metal film UM and a seed film RM1 that are electrically connected to the pad electrode 9a through the opening 11a and the pad opening 10a are formed (deposited).
  • the first base barrier film UM1, the second base barrier film UM2, and the third base barrier film UM3 constituting the base metal film UM are sequentially formed of a titanium (Ti) film of 5 to 50 nm and a titanium nitride (TiN) film of 10 to It is appropriate to form a 100 nm titanium (Ti) film with a thickness of 5 to 50 nm.
  • the titanium (Ti) film is 10 nm
  • the titanium nitride (TiN) film is 50 nm
  • the titanium (Ti) film is 10 nm.
  • the first base barrier film UM1, the second base barrier film UM2, and the third base barrier film UM3 are formed by, for example, a sputtering method.
  • a seed film RM1 made of a copper (Cu) film is formed on the third base barrier film UM3 by sputtering.
  • the seed film RM1 has a thickness of about 250 nm.
  • FIG. 7 shows the plating process of the rewiring RM formation process.
  • a resist mask (resist pattern) PR1 is formed to expose a region where the rewiring RM is formed and cover a region where the rewiring RM is not formed. That is, the resist mask PR1 is an inverted pattern of the first plane pattern P1, and has an opening corresponding to the first plane pattern P1.
  • the plating film RM2 made of a copper (Cu) film is selectively formed on the seed film RM1 in the region exposed from the resist mask PR1 by electrolytic (electric) plating using the base metal film UM and the seed film RM1 as seed layers. To form.
  • the thickness of the plating film RM2 is about 6 ⁇ m, for example.
  • the film thickness of the plating film RM2 is preferably in the range of 2 ⁇ m to 10 ⁇ m. If the film thickness of the plating film RM2 is too thin, the resistance of the rewiring RM increases, so that a resistance value that satisfies the requirements of the device can be obtained. It should be a film thickness, and a certain film thickness is generally required. However, if the thickness is too large, the warpage of the wafer becomes large, a transport error occurs in the subsequent lithography and processing apparatus, the processing becomes difficult, and the manufacturing cost increases and the productivity decreases. For example, the base metal film UM and the like are given the same reference numerals before and after patterning. In this step, the plating film RM2 having the first planar pattern P1 is formed.
  • FIG. 8 shows a removal (processing) process of the seed film RM1 which is a process of forming the rewiring RM.
  • the resist mask PR1 is removed.
  • the seed film RM1 in a region exposed from the plating film RM2 is removed, so that a patterned seed film RM1 having a planar pattern equal to the plating film RM2 remains under the plating film RM2.
  • a rewiring RM having the first planar pattern P1 and having a stacked structure of the seed film RM1 and the plating film RM2 is formed.
  • the base metal film UM in the region exposed from the plating film RM2 is important to leave the base metal film UM in the region exposed from the plating film RM2 (in other words, the region outside the rewiring RM) without being removed.
  • the base metal film UM remains in the region exposed from the plating film RM2.
  • the base metal film UM in the region exposed from the plating film RM2 is removed by etching by about half the film thickness. You may do it. That is, the thickness of the base metal film UM in the region exposed from the plating film RM2 may be about half the thickness of the base metal film UM in the region covered with the plating film RM2.
  • the etching is dry etching containing a chlorine-based gas using the plating film RM2 or the seed film RM1 as a heart mask.
  • FIG. 9 shows a part of the process of forming the cap metal film CM.
  • a cap metal film CM is formed (deposited) so as to completely cover the upper surface and side surfaces of the rewiring RM.
  • the cap metal film CM before patterning is called a cap metal material film.
  • the cap metal film CM is composed of a plurality of cap barrier films.
  • the first cap barrier film (first cap metal material film) CM1 the second cap barrier film (second cap metal material film) CM2, and the third cap barrier film (third cap metal film).
  • Material film) CM3 is formed sequentially.
  • the third cap barrier film CM3 is also handled as a part of the cap metal film CM.
  • the first cap barrier film CM1, the second cap barrier film CM2, and the third cap barrier film CM3 have a titanium (Ti) film of 10 to 200 nm, a palladium (Pd) film of 10 to 200 nm, and a titanium (Ti) film of 10 to 200 nm. It is appropriate to form the film with a thickness of 200 nm.
  • the lower titanium (Ti) film is 10 nm
  • the palladium (Pd) film is 50 nm
  • the upper titanium (Ti) film is 175 nm.
  • first cap barrier film CM1 the second cap barrier film CM2, and the third cap barrier film CM3
  • a conformal film forming method such as a CVD method in order to completely cover the side surface of the rewiring RM.
  • CVD method a conformal film forming method
  • the first cap barrier film CM1 in contact with the third base barrier film UM3 is made of the same material as the film of the third base barrier film UM3, so that the third base barrier film UM3 and the third base barrier film UM3 in the overhanging portion PP are formed.
  • Adhesiveness with 1 cap barrier film CM1 can be improved.
  • the base metal film UM and the cap metal film in the overhanging portion PP are made equal by using the same material for the film that becomes the upper surface of the base metal film UM having the laminated structure and the film that becomes the lower surface of the cap metal film CM having the multilayer structure.
  • Adhesiveness with CM can be improved, movement (diffusion) of copper ions constituting the rewiring RM can be prevented, and entry of moisture and the like from the base insulating film 11 or the protective film 12 can be prevented.
  • the surface of the rewiring RM and the base metal film UM (particularly, the third base barrier film UM3) is subjected to hydrogen plasma treatment, and the upper surface and side surfaces of the rewiring RM and the base
  • the oxide film on the upper surface of the metal film UM may be removed and cleaned to improve the adhesion between the base metal film UM and the cap metal film CM.
  • a resist mask PR2 is formed on the third cap barrier film CM3.
  • the resist mask PR2 corresponds to the second planar pattern P2, and is a pattern that covers the rewiring RM and the projecting portion PP around the rewiring RM and exposes the rest in plan view.
  • FIG. 10 shows a part of the process of forming the cap metal film CM subsequent to FIG.
  • the third cap barrier film CM3 in the region exposed from the resist mask PR2 is removed by dry etching or wet etching to form a third cap barrier film CM3 having the second planar pattern P2.
  • the third cap barrier film CM3 made of a titanium (Ti) film is wet-etched using an ammonia aqueous solution. That is, the third cap barrier film CM3 is patterned using the resist mask PR2.
  • the second cap barrier film CM2 is etched by using the patterned third cap barrier film CM3 made of a titanium (Ti) film as a hard mask to form a second cap barrier film CM2 having a second planar pattern P2.
  • the second cap barrier film CM2 made of a palladium (Pd) film is wet etched using a potassium iodide iodide solution, but may be etched by a dry etching method. That is, the second cap barrier film CM2 is patterned (etched) using the third cap barrier film CM3 as a mask.
  • the base metal film UM exists in the overhanging portion PP that is an area outside the rewiring RM, and in the overhanging portion PP, Since the cap metal film CM and the base metal film UM are in direct contact with each other, the etching solution does not penetrate into the rewiring RM.
  • FIG. 11 shows a part of the process of forming the cap metal film CM and the processing process of the base metal film UM following FIG.
  • the first cap barrier film CM1 and the base metal film UM in the regions exposed from the third cap barrier film CM3 and the second cap barrier film CM2 are removed by etching, and the upper surface of the base insulating film 11 is exposed. Since the first cap barrier film CM1 and the base metal film UM are formed of a titanium (Ti) film and a titanium nitride (TiN) film, for example, the first cap barrier film CM1 is formed by wet etching using an ammonia aqueous solution.
  • the base metal film UM can be removed to form the first cap barrier film CM1 and the base metal film UM having the second planar pattern P2.
  • the third cap barrier film CM3 formed of a titanium (Ti) film is also removed at the same time, and the upper surface of the second cap barrier film CM2 is exposed.
  • the film thickness of the third cap barrier film CM3 so as to be approximately equal to the etching time of the first cap barrier film CM1 and the base metal film UM, the first cap barrier film with respect to the end portion of the second cap barrier film CM2 is set. Side etching of the CM1 and the base metal film UM can be reduced.
  • the cap metal film CM covering the upper surface and the side surface of the adjacent rewiring RM and the base metal film UM in contact with the lower surface are separated, and the cap metal film CM and the base metal film UM having the same second planar pattern P2 are separated. Is formed.
  • “equal” includes the case where there is a dimensional difference due to the above-mentioned side etching.
  • the base metal film UM exists in the overhanging portion PP that is an area outside the rewiring RM.
  • the cap metal film CM and the base metal film UM are in direct contact with each other, so that the etching solution does not penetrate into the rewiring RM.
  • FIG. 12 shows a process for forming the protective film 12.
  • a protective film 12 having an opening 12a that covers the upper surface and the side surface of the rewiring RM and exposes the external pad electrode 18 provided on the upper surface of the rewiring RM is formed.
  • the protective film 12 is thicker than the rewiring RM and is in contact with the upper surface of the base insulating film 11 in a region between adjacent rewiring RMs.
  • a photosensitive polyimide resin is used as the protective film 12.
  • a photosensitive polyimide is applied on the rewiring RM and exposed to form an opening 12a exposing the external pad electrode 18, and then cured and cured.
  • FIG. 13 shows a mounting process of the semiconductor chip 1A.
  • the semiconductor chip 1A is mounted on the die pad portion 25D, the rewiring RM and the lead 25L are connected by the wire 27, and then a part of the lead 25L (inner lead portion), the die pad portion 25D, and the semiconductor chip 1A.
  • the wire 27 is sealed with a sealing body (sealing resin) 26 to complete the semiconductor device (semiconductor integrated circuit device) of the first embodiment.
  • a semiconductor chip 1A having a plurality of redistribution lines RM is mounted on a die pad portion 25D and electrically connected to a plurality of leads 25L by wires 27.
  • a part (inner lead part) of the lead 25L, the die pad part 25D, the semiconductor chip 1A, and the wire 27 are sealed with a sealing body (sealing resin) 26 such as a thermosetting epoxy resin.
  • the sealing body 26 contains a filler such as silica (SiO 2 ) in addition to the epoxy resin.
  • the lead 25 has an outer lead portion extending from the inner lead portion covered with the sealing body 26 to the outside of the sealing body 26.
  • the wire 27 is connected to the external pad electrode 18 formed on the upper surface of the rewiring RM of the semiconductor chip 1A shown in FIG. 4 or 12, and the other end is connected to the inner lead portion of the lead 25L.
  • the die pad portion 25D and the plurality of leads 25L are made of, for example, copper (Cu) or 42 alloy (iron nickel alloy), and the wire 27 is made of copper (Cu).
  • a second cap barrier film CM2 made of a palladium (Pd) film is exposed on the surface of the external pad electrode 18, and a wire 27 made of copper is bonded to the second cap barrier film CM2 made of a palladium (Pd) film. Therefore, stable and sufficient bonding strength is possible, and high-reliability bonding with high shear strength is possible.
  • a copper wire Pd-coated Cu wire
  • a gold wire Au wire whose surface is coated with palladium (Pd) may be used.
  • the titanium (Ti) film is used as the first cap barrier film CM1, an alloy containing Ni, Mo, W, Co, Ru, Ta, or the like as a main component or a laminated film of these metals may be used. Further, although a titanium (Ti) film is used as the third base barrier film UM3, alloys such as metals such as Ni, Mo, W, Co, Ru, Ta, nitrides thereof, carbides thereof, and the like containing these metals as main components are used. A laminated film of these metals may be used. ⁇ Characteristics of semiconductor device manufacturing method> The main features of the method for manufacturing the semiconductor device according to the first embodiment will be described below.
  • a base metal film UM continuously extends from below the rewiring RM in a certain projecting portion PP.
  • the base metal film UM exists between the cap metal film CM formed on the side surface (side wall) of the rewiring RM and the base insulating film 11. Therefore, it is possible to prevent the occurrence of a defect that the copper (Cu) film forming the rewiring RM is peeled off in both the etching steps. Next, this effect will be described.
  • FIG. 18 and FIG. 19 are cross-sectional views during a manufacturing process of a semiconductor device which is a comparative example of the first embodiment.
  • FIG. 18 shows a state in which the base metal film UM in the region exposed from the plating film RM2 is removed following the step of removing the seed film RM1 described with reference to FIG. Unlike the manufacturing method of the first embodiment, after removing the seed film RM1, the plating process RM2 or the underlying metal film UM in the region exposed from the seed film RM1 is completely removed, so that the etching process of the underlying metal film UM is performed. In this case, overetching is essential. That is, as shown in FIG. 18, a side etch occurs in which the end of the base metal film UM recedes from the end of the rewiring RM, and the rewiring RM protrudes from the end of the base metal film UM in a bowl shape. Become.
  • the cap metal film CM is deposited on the upper surface and the side surface of the rewiring RM.
  • the step breakage occurs due to the side etching of the base metal film UM.
  • the etching solution is discharged from the step breakage portion to the rewiring RM or the rewiring RM. It was found that the lower base metal film UM soaked and a part of the rewiring RM was peeled off.
  • the underlying metal film UM in the region exposed from the plating film RM2 is completely removed continuously.
  • the base metal film UM is left until the cap metal film CM in the region outside the rewiring RM is removed, and following the removal of the cap metal film CM (in the same process)
  • the base metal film UM in the region outside the rewiring RM is removed, the above disconnection can be prevented and the rewiring RM can be prevented from being peeled off.
  • a second cap barrier film CM2 made of a palladium (Pd) film is exposed on the surface of the external pad electrode 18, and a wire 27 made of copper is bonded to the second cap barrier film CM2 made of a palladium (Pd) film. Since they are connected, it is possible to perform bonding with stable and sufficient bonding strength.
  • FIG. 14 is a cross-sectional view of the semiconductor device as the first modification of the first embodiment during the manufacturing process.
  • the side surface (side wall) of the rewiring RM is between the step of removing the seed film RM1 described with reference to FIG. 8 and the step of forming the cap metal film CM described with reference to FIG. Is added to the forward taper.
  • argon (Ar) sputter etching on the rewiring RM, a trapezoidal rewiring RMa whose side surface is forward tapered in a cross-sectional view can be obtained.
  • the trapezoidal shape can be said to be a shape in which the lower surface of the rewiring RMa is wider than the upper surface, or a shape in which the width of the lower surface is larger than the width of the upper surface in a sectional view.
  • the rewiring RMa has a laminated structure of a seed film RM1a and a plating film RM2a, and the side surfaces of the seed film RM1a and the plating film RM2a have a continuous forward taper.
  • the plating film RM2 is formed by the electrolytic plating method described with reference to FIG. 7, since the side surface of the resist mask PR1 is a forward taper, the side surface of the plating film RM2 is a reverse taper, and in the sectional view of the plating film RM2.
  • the shape is an inverted trapezoidal shape.
  • the covering property of the cap metal film CM formed so as to cover the side surface of the rewiring RM is lowered, and the cap metal film CM having a discontinuous portion or a pinhole is formed.
  • an etching solution penetrates into the rewiring RM in the wet etching process of the cap metal film CM, and a side surface of the rewiring RM is etched (abnormal etching).
  • FIG. 15 is a cross-sectional view of the semiconductor device as the second modification of the first embodiment during the manufacturing process.
  • the shoulder or side surface of the rewiring RM is interposed between the step of removing the seed film RM1 described with reference to FIG. 8 and the step of forming the cap metal film CM described with reference to FIG. Add a rounding process.
  • the rewiring RMb with a rounded shoulder can be obtained.
  • the oxide film on the surface of the copper film of the rewiring RM is reduced by annealing at a temperature of about 300 ° C. to 450 ° C. in a hydrogen (H 2 ) plasma treatment or a hydrogen (H 2 ) atmosphere, the temperature of 300 ° C.
  • the rewiring RMb has a stacked structure of a seed film RM1b and a plating film RM2b.
  • the shoulder of the rewiring RM is rounded and the side surface is smooth, so that the coverage of the cap metal film CM is improved, and the rewiring RM is abnormally etched due to the discontinuity or pinhole of the cap metal film CM. Can be prevented.
  • FIG. 16 is a cross-sectional view of the semiconductor device as the third modification of the first embodiment during the manufacturing process.
  • FIG. 16 shows a semiconductor chip 1D which is a modification of the semiconductor chip 1A shown in FIG. 4.
  • the difference from the semiconductor chip 1A is rewiring without interposing a base insulating film 11 on the surface protective film 10.
  • RM is arranged.
  • the base metal film UM is in contact with and electrically connected to the pad electrode 9 a and extends to the side wall and the upper surface of the surface protective film 10 in the pad opening 10 a of the surface protective film 10.
  • the lower surface of the base metal film UM is in contact with the upper surface of the surface protective film 10.
  • the base metal film UM and the cap metal film CM in contact with the lower surface of the rewiring RM are the same as those in the first embodiment.
  • Other structures and manufacturing methods are the same as those in the first embodiment.
  • the bottom surface of the rewiring RM is completely covered with the base metal film UM, the top surface and the side surfaces are completely covered with the cap metal film CM, and the base metal film UM and the cap metal film CM are in direct contact with each other at the projecting portion PP.
  • the copper constituting the rewiring RM can be prevented from moving (diffusing) to the outside as copper ions. Moreover, it is possible to prevent the copper film constituting the rewiring RM from being oxidized by moisture, halogen ions, or the like contained in the protective film 12 or the sealing body 26. That is, since the electrical reliability between the adjacent rewirings RM can be improved, the base insulating film 11 shown in FIG. 4 can be omitted.
  • the protective film 12 made of an organic film is provided on the rewiring RM and the surface protective film, even if the semiconductor chip 1D is sealed with a sealing body 26 containing silica, as shown in FIG. It is possible to prevent cracks in the surface protective interlayer 10 resulting from the contact between the sealing body 26 and the surface protective film 10.
  • the electrical reliability between the adjacent rewiring RMs can be improved, not only the base insulating film 11 but also the protective film 12 may be omitted. Even if moisture and halogen ions are contained in the sealing body 26, the above structure can prevent moisture and halogen ions from entering the rewiring RM.
  • FIG. 17 is a cross-sectional view of the semiconductor device as the fourth modification of the first embodiment during the manufacturing process.
  • FIG. 17 is a modification of the mounting process described in FIG.
  • the semiconductor chip 1A is mounted on the wiring board 30 via the adhesive layer 39, and the rewiring RM and the bonding finger 32 are connected by the wire 37, and then the upper surface side of the wiring board 30, the semiconductor chip 1A, and the wire 37 are connected. Is sealed with a sealing body (sealing resin) 38 to complete the semiconductor device (semiconductor integrated circuit device) of Modification 4.
  • the wiring board 30 has a plurality of bonding fingers 32 made of a conductor layer on the upper surface of a core layer 31 made of an insulating layer, and a plurality of lands 33 made of a conductor layer on the lower surface.
  • the plurality of bonding fingers 32 and the plurality of lands 33 are electrically insulated by a solder resist 35 made of an insulating layer.
  • the bonding fingers 32 and the lands 33 are electrically connected via via wirings 34 made of a conductor layer formed on the core layer 31, and bump electrodes 36 made of solder are connected to the lands 33.
  • the sealing body 38 is made of a thermosetting epoxy resin or the like, and contains a filler such as silica (SiO 2).
  • the wire 37 is connected to the external pad electrode 18 formed on the upper surface of the rewiring RM of the semiconductor chip 1A shown in FIG. 4 or 16, and the other end is connected to the bonding finger 32.
  • the wire 27 is a copper (Cu) wire, but a copper wire (Pd-coated Cu wire) whose surface is covered with palladium (Pd) or a gold wire (Au wire) may be used.
  • the external pad electrode 18 and the bonding finger 32 are electrically connected with a wire.
  • a solder ball is formed on the external pad electrode 18 on the upper surface of the rewiring RM, and the external pad electrode 18 is connected with the solder ball.
  • the bonding fingers 32 may be electrically connected.
  • the external pad electrode 18 and the bonding finger 32 may be connected by a solder ball with the side of the semiconductor chip 1A on which the rewiring RM is formed facing the upper surface of the wiring board 30.
  • the second embodiment corresponds to a modification of the semiconductor device manufacturing method of the first embodiment.
  • 20 and 21 are sectional views of the semiconductor device according to the second embodiment during the manufacturing process.
  • the semiconductor device of the second embodiment is indicated as a semiconductor chip 1E. Parts common to the manufacturing method of the first embodiment are denoted by the same reference numerals.
  • the underlying metal film UM in the region exposed from the seed film RM1 is removed.
  • the base metal film UM in the region exposed from the seed film RM1 is completely removed, so that overetching is essential in the etching process of the base metal film UM.
  • a side etch occurs in which the end portion of the base metal film UMa recedes from the end portion of the rewiring RM, and the rewiring RM protrudes in a bowl shape from the end portion of the base metal film UMa.
  • the rewiring RM has a stacked structure of a seed film RM1 and a plating film RM2, and the base metal film UMa has a stacked structure of a first base barrier film UM1a, a second base barrier film UM2a, and a third base barrier film UM3a.
  • etching is performed on the rewiring RM, and the rewiring RM is processed until the side surface of the rewiring RM is coincident with the side surface of the base metal film UMa or until the inner side of the rewiring RM is closer to the side surface of the base metal film UMa. Sharpen. That is, the protruding portion is removed by etching.
  • a rewiring RMc having a side surface coinciding with the side surface of the base metal film UMa is formed.
  • the rewiring RMc has a laminated structure of a seed film RM1c and a plating film RM2c.
  • the side surface of the rewiring RMc is on the inner side of the rewiring RMc than the side surface of the base metal film UMa.
  • the wet etching for the base metal film UM uses, for example, an ammonia aqueous solution. Then, the etching for the rewiring RM may be either wet etching or dry etching.
  • the steps after the step of forming the cap metal film CM of the first embodiment are performed to complete the semiconductor device having the semiconductor chip 1E.
  • the cap metal film is removed. It is possible to prevent the rewiring RMc from being peeled off due to CM breakage. Since the lower surface of the cap metal film CM can be in contact with the side surface or the upper surface of the base metal film UM, oxidation of the copper film constituting the rewiring RMc or movement (diffusion) of copper ions can be prevented. .
  • Modification 5 corresponds to a modification of the method for manufacturing the semiconductor device of the second embodiment.
  • FIG. 22 is a cross-sectional view of a semiconductor device as a fifth modification of the second embodiment during the manufacturing process.
  • the semiconductor device of Modification 5 is indicated as a semiconductor chip 1F. Portions common to the manufacturing method of Embodiment 1 or 2 are denoted by the same reference numerals.
  • the rewiring RM is sputter-etched in order to fill the space under the protruding portion of the rewiring RM.
  • argon (Ar) sputter etching on the rewiring RM shown in FIG. 20, as shown in FIG. 22, a trapezoidal rewiring RMd whose side surface is forward tapered as shown in FIG. 22 is obtained. Can do.
  • the space between the protruding portion of the rewiring RMc and the base insulating film 11 can be filled with the redeposited material (reattached material) 13.
  • the rewiring RMd has a stacked structure of a seed film RM1d and a plating film RM1d.
  • the process after the formation process of the cap metal film CM of the first embodiment is performed to complete the semiconductor device having the semiconductor chip 1F. Since the space is filled, the cap metal film CM is formed. The disconnection can be prevented, and the rewiring RMd can be prevented from peeling off.
  • the space between the protruding portion of the rewiring RM and the base insulating film 11 can be eliminated by performing the reflow of Modification 2 instead of etching the protruding portion.
  • the mounting process of Modification 4 may be applied to the semiconductor chip 1E or 1F of Embodiment 2 or Modification 5.
  • [Appendix 1] (A) forming a pad electrode on the main surface of the semiconductor substrate; (B) forming a first insulating film having an opening on the pad electrode; (C) forming a base metal film electrically connected to the pad electrode through the opening on the first insulating film; (D) forming a rewiring electrically connected to the pad electrode through the base metal film on the base metal film; (E) forming a cap metal film that covers the top and side surfaces of the rewiring; Have The step (d) (D-1) forming the rewiring electrically connected to the pad electrode through the base metal film on the base metal film; (D-2) a step of completely etching the base metal film in a region exposed from the rewiring; (D-3) Thereafter, the step of retreating the rewiring by wet etching, Including The step (e) (E-1) forming a cap barrier film over the entire main surface of the semiconductor substrate; (E-2) forming the cap metal film by patterning the

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

　半導体装置は、複数の配線層の最上層に形成されたパッド電極９ａと、パッド電極９ａ上に開口１１ａを有する下地絶縁膜１１と、下地絶縁膜１１上に形成された下地金属膜ＵＭと、下地金属膜ＵＭ上に形成された再配線ＲＭと、再配線ＲＭの上面および側面を覆うように形成されたキャップ金属膜ＣＭとを有する。そして、再配線ＲＭの外側の領域において、再配線ＲＭの側壁上に形成されたキャップ金属膜ＣＭと下地絶縁膜１１との間には、再配線ＲＭとは別材料の下地金属膜ＵＭと、再配線ＲＭとは別材料のキャップ金属膜ＣＭと、が形成されており、再配線ＲＭの外側の領域において、下地金属膜ＵＭとキャップ金属膜ＣＭとが直接接している。

Description

半導体装置およびその製造方法
　本発明は、半導体装置およびその製造方法に関し、特に、半導体基板の主面上に形成された複数の配線層の上部に、金属膜で構成された再配線を有する半導体装置およびその製造方法に適用して有効な技術に関するものである。
　半導体装置は、例えばＣＭＩＳ(Complementary Metal Insulator Semiconductor)トランジスタなどの半導体素子が形成された半導体基板の上部に、例えばＣｕ（銅）またはＡｌ（アルミニウム）を主成分とする金属膜で多層配線が形成され、多層配線の上部にファイナルパッシベーション膜が形成される。
　特開２００３－２３４３４８号公報（特許文献１）には、ファイナルパッシベーション膜上にＣｕを主成分とする再配線を形成し、ファイナルパッシベーション膜の下の最上層配線に形成した電極パッドと再配線とを電気的に接続する技術が開示されている。
　特開２０１２－４２１０号公報（特許文献２）の図２５には、Ｃｕを主要な成分とする再配線１５の上面および側面を部分的に覆うように形成されたパッド１８にワイヤ２０が接続された構造が開示されている。
　特開２０００－３０６９３８号公報（特許文献３）の要約には、パッシベーション膜４上に形成されたアルミニウム合金からなる再配線層６を、パッシベーション膜６上に張り出した張出部位９を有するバリアメタル膜８により完全に被覆することで、再配線層６のマイグレーションやコロージョンの発生を抑制することが開示されている。
　“Development of highly reliable Cu wiring of L/S=1/1μm for chip to chip interconnection”（非特許文献１）には、ＳＡＰ(Semi-Additive Process)法で形成したＣｕ配線の信頼性向上の為に、Ｃｕ配線の上面および側面に無電解メッキ法で形成した金属バリア膜を設けた構造が開示されている。
特開２００３－２３４３４８号公報 特開２０１２－４２１０号公報 特開２０００－３０６９３８号公報
T.Kanki et al., "Development of highly reliable Cu wiring of L/S=1/1μm for chip to chip interconnection" Interconnect Technology Conference, 2012 IEEE International,4-6 June 2012
　本願発明者が検討している再配線を有する半導体装置（半導体集積回路装置）は、半導体チップと、半導体チップに接続されたワイヤと、半導体チップおよびワイヤを封止する封止体とを有する。半導体チップは、半導体素子と、半導体素子に電気的に接続されたＣｕを主成分とする再配線と、半導体素子と再配線とを電気的に接続する多層配線層からなる配線とを有する。再配線は、多層配線層の最上層の配線層で形成された配線の一部分であるパッド電極に接続されている。最上層の配線層で形成された配線と再配線との間は、最上層の配線層で形成された配線を覆う表面保護膜と、表面保護膜上に形成された第１有機保護膜とで電気的に分離されているが、パッド電極を露出するように設けられた表面保護膜と第１有機保護膜の開口を介して、再配線はパッド電極と電気的に接続されている。再配線の上面と側面は第２有機保護膜で覆われているが、第２有機保護膜は、再配線の上面に形成された外部パッド電極を露出する開口を有しており、この開口部でワイヤが再配線に接続されている。
　半導体チップには、複数の再配線が形成されており、再配線の最小の線幅は１２μｍであり、隣接する再配線の最小間隔は１５μｍである。再配線の下面には、再配線を形成するための金属膜（例えば、Ｃｒ膜）からなるシード層が設けられているが、再配線の上面および側面は、第２有機保護膜と接している。
　本願発明者が検討している半導体装置は、高耐圧、高信頼性が要求されるため、ＨＡＳＴ（Highly Accelerated temperature and humidity Stress Test）試験と呼ばれる高温高湿度雰囲気中での動作試験を実施している。本願発明者の検討によれば、ＨＡＳＴ試験において、隣り合う再配線の間で、一方の再配線からＣｕが樹枝状に析出して、隣り合う再配線間の耐圧劣化または短絡が発生し、半導体装置の信頼性が低下していることが判明した。そして、Ｃｕの樹枝状の析出は、表面保護膜と第１有機保護膜との界面または第１および第２有機保護膜の界面で発生していることも分かった。
　本願発明者の分析によれば、Ｃｕからなる再配線を覆う第１および第２有機保護膜は、ポリイミド膜からなり、水分やハロゲンイオンを含んでいるため、再配線を構成するＣｕの表面が酸化され、その結果、Ｃｕイオン（イオン化したＣｕ）が発生する。上記半導体装置では、隣り合う再配線の最小間隔（１５μｍ）は大きいものの、高電圧が印加され、隣り合う再配線間に高電界がかかる領域が存在し、この領域でＣｕの樹枝状の析出が発生していることが分かった。つまり、Ｃｕイオンが高電界の影響で、表面保護膜と第１有機保護膜との界面または第１および第２有機保護膜の界面を移動（拡散）することで隣り合う再配線間の耐圧劣化または短絡が発生し、半導体装置の信頼性が低下していると考えている。
　本発明の目的は、再配線を有する半導体装置において、信頼性を向上させることのできる技術を提供することにある。
　本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。
　一実施の形態である半導体装置は、複数の配線層の最上層に形成されたパッド電極と、パッド電極上に開口を有する保護膜と、保護膜上に形成された下地金属膜と、下地金属膜上に形成された再配線と、再配線の上面および側面を覆うように形成されたキャップ金属膜とを有する。そして、再配線の外側の領域において、再配線の側壁上に形成されたキャップ金属膜と保護膜との間には、再配線とは別材料の下地金属膜と、再配線とは別材料のキャップ金属膜と、が形成されており、再配線の外側の領域において、下地金属膜とキャップ金属膜とが直接接している。
　一実施の形態によれば、再配線を有する半導体装置の信頼性を向上させることができる。
本発明の実施の形態１である半導体装置の回路ブロック図である。 本発明の実施の形態１である半導体装置が形成された半導体チップの全体平面図である。 図２の一部を拡大して示す平面図である。 図３のＡ－Ａ線に沿った断面図である。 本実施の形態１の半導体装置の製造工程中の断面図である。 図５に続く半導体装置の製造工程中の断面図である。 図６に続く半導体装置の製造工程中の断面図である。 図７に続く半導体装置の製造工程中の断面図である。 図８に続く半導体装置の製造工程中の断面図である。 図９に続く半導体装置の製造工程中の断面図である。 図１０に続く半導体装置の製造工程中の断面図である。 図１１に続く半導体装置の製造工程中の断面図である。 図１２に続く半導体装置の製造工程中の断面図である。 変形例１である半導体装置の製造工程中の断面図である。 変形例２である半導体装置の製造工程中の断面図である。 変形例３である半導体装置の製造工程中の断面図である。 変形例４である半導体装置の製造工程中の断面図である。 比較例である半導体装置の製造工程中の断面図である。 図１８に続く比較例である半導体装置の製造工程中の断面図である。 実施の形態２の半導体装置の製造工程中の断面図である。 図２０に続く半導体装置の製造工程中の断面図である。 変形例５である半導体装置の製造工程中の断面図である。
　以下の実施の形態においては便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、応用例、詳細説明、補足説明等の関係にある。また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でもよい。
　さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数等（個数、数値、量、範囲等を含む）についても同様である。
　以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一または関連する符号を付し、その繰り返しの説明は省略する。また、複数の類似の部材（部位）が存在する場合には、総称の符号に記号を追加し個別または特定の部位を示す場合がある。また、以下の実施の形態では、特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。
　また、実施の形態で用いる図面においては、断面図であっても図面を見易くするためにハッチングを省略する場合もある。また、平面図であっても図面を見易くするためにハッチングを付す場合もある。
　また、断面図および平面図において、各部位の大きさは実デバイスと対応するものではなく、図面を分かりやすくするため、特定の部位を相対的に大きく表示する場合がある。また、平面図と断面図が対応する場合においても、各部位の大きさを変えて表示する場合がある。
（実施の形態１）
　本実施の形態１および以下の実施の形態の半導体装置（半導体集積回路装置）は、例えば複数の半導体素子と、複数の半導体素子の上部に形成された複数層の配線（多層配線）と、複数層の内の最上層の配線に接続された複数の再配線を有する半導体チップを有し、複数の半導体素子を前記多層配線および複数の再配線により接続して構成される。
＜半導体装置について＞
　図１は、半導体装置の回路ブロック図である。図１に示すように、半導体装置は、例えば半導体チップ１Ａのデバイス面に形成された入出力（Ｉ／Ｏ）回路、アナログ回路、ＣＭＩＳ－ロジック回路、パワーＭＩＳ回路、およびメモリ回路を備え、半導体装置を構成している。
　半導体装置を構成する上記回路のうち、ＣＭＩＳ－ロジック回路は、例えば動作電圧が１～３ＶのＣＭＩＳトランジスタで構成されており、Ｉ／Ｏ回路およびメモリ回路は、例えば動作電圧が１～３Ｖおよび５～８ＶのＣＭＩＳトランジスタで構成されている。
　動作電圧が１～３ＶのＣＭＩＳトランジスタは、第１のゲート絶縁膜を有する第１のｎチャネル型ＭＩＳＦＥＴ(Metal Insulator Semiconductor Field Effect Transistor)と、第１のゲート絶縁膜を有する第１のｐチャネル型ＭＩＳＦＥＴとで構成される。また、動作電圧が５～８ＶのＣＭＩＳトランジスタは、第２のゲート絶縁膜を有す第２のｎチャネル型ＭＩＳＦＥＴと、第２のゲート絶縁膜を有す第２のｐチャネル型ＭＩＳＦＥＴとで構成される。第２のゲート絶縁膜の膜厚は、第１のゲート絶縁膜の膜厚よりも厚く構成される。以下の説明では、ＭＩＳＦＥＴをＭＩＳトランジスタという。
　また、アナログ回路は、例えば動作電圧が５～８ＶのＣＭＩＳトランジスタ（またはバイポーラトランジスタ）と抵抗素子と容量素子とで構成されており、パワーＭＩＳ回路は、例えば動作電圧が５～８ＶのＣＭＩＳトランジスタと動作電圧が２０Ｖ～１００Ｖの高耐圧ＭＩＳトランジスタ（高耐圧素子）とで構成されている。
　高耐圧ＭＩＳトランジスタは、例えば第３のゲート絶縁膜を有する第３のｎチャネル型ＭＩＳＦＥＴ、または第３のゲート絶縁膜を有する第３のｐチャネル型ＭＩＳＦＥＴ、あるいは両方で構成される。ゲート電極とドレイン領域との間、またはゲート電極とソース領域との間に２０Ｖ～１００Ｖの電圧が印加される場合、第３のゲート絶縁膜の膜厚は、第２のゲート絶縁膜の膜厚よりも厚くなるように構成される。
　図２は、半導体チップ１Ａの一例を示す全体平面図、図３は、図２の破線Ｘで囲まれた領域の拡大平面図、図４は、図３のＡ－Ａ線に沿った断面図である。
　図２は、半導体チップ１Ａのデバイス面上に形成された再配線ＲＭ、ＲＭＶ、ＲＭＳのレイアウトの一例を示している。再配線ＲＭ、ＲＭＶ、ＲＭＳは、半導体チップ１Ａの複数層の配線（図４に示す第１層Ａｌ配線５、第２層Ａｌ配線７、第３層Ａｌ配線９）に比べ、その膜厚および配線幅ともに大きいため、複数層の配線に比べ、非常に低インピーダンスである。再配線ＲＭ、ＲＭＶ、ＲＭＳは、例えば、信号入出力用の再配線ＲＭと、電源（Ｖｃｃ、ＧＮＤ）供給用の再配線ＲＭＶおよび内部回路間の接続用の再配線ＲＭＳとして使用されている。
　図２に示すように、半導体チップ１Ａの周辺部には、半導体装置の外部接続端子を構成する複数の再配線ＲＭが配置されている。半導体装置の外部接続端子を構成する再配線ＲＭのそれぞれの一端には、外部パッド電極１８が形成されており、他端は、図３、４に示すように最上層の配線に形成されたパッド電極９ａに接続されている。外部パッド電極１８は、特に限定されないが、半導体チップ１Ａの各辺に沿って一列に配置される。なお、外部パッド電極１８は、半導体チップ１Ａの各辺に沿って千鳥状、あるいは３列以上の列となるように配置してもよいのは勿論である。つまり、再配線ＲＭは、例えば、図１の入出力（Ｉ／Ｏ）回路を構成する信号入出力用の再配線である。
　また、図２に示す再配線ＲＭＶは、電源（Ｖｃｃ、ＧＮＤ）供給用の再配線である。再配線ＲＭＶの一端には外部パッド電極１８が形成され、他端は半導体チップ１Ａ内の電源配線に形成されたパッド電極９ａに接続されているので、半導体チップ１Ａの外部から供給された電源（Ｖｃｃ、ＧＮＤ）電圧を、半導体チップ１Ａ内の複数の電源配線に低インピーダンスで供給することができる。
　また、図２に示す再配線ＲＭＳは、半導体チップ１Ａに形成された回路間または素子間を接続する配線として使用されている。したがって、再配線ＲＭＳには外部パッド電極１８は形成されていない。再配線ＲＭＳの両端は、配線に形成されたパッド電極９ａに接続されている。
　図３は、隣り合う２つの信号入出力用の再配線ＲＭの拡大平面図を示している。隣り合う２つの再配線ＲＭは、互いに等しい平面形状を有するので、紙面上部に位置する再配線ＲＭを例に説明する。再配線ＲＭは、紙面のＸ方向に延在しており、その一端で、紙面のＸ方向に延在する配線９のパッド電極９ａに電気的に接続されている。再配線ＲＭの他端には、外部パッド電極１８が形成されている。再配線ＲＭは、第１平面パターンＰ１を有し、下地金属膜ＵＭおよびキャップ金属膜ＣＭは第２平面パターンＰ２を有している。第１平面パターンＰ１と第２平面パターンＰ２とは相似形であり、第２平面パターンＰ２は、第１平面パターンＰ１を拡大した形状を有する。再配線ＲＭの全周囲には、下地金属膜ＵＭおよびキャップ金属膜ＣＭで構成された張り出し部ＰＰが配置されている。つまり、第１平面パターンＰ１を張り出し部ＰＰの幅Ｓ３だけ拡大すると第２平面パターンＰ２となる。
　また、再配線ＲＭの最小配線幅Ｌは、例えば１２μｍであり、隣り合う再配線ＲＭの最小配線間隔Ｓ１は１５μｍ、隣り合う張り出し部ＰＰ間の最小間隔Ｓ２は１０μｍ、張り出し部ＰＰの張り出し量Ｓ３は２．５μｍ、である。
　理想的には、再配線ＲＭの全周囲にわたって、張り出し部ＰＰの張り出し量Ｓ３は等しくなるが、第２平面パターンＰ２が第１平面パターンＰ１に対して、例えば、Ｘ方向にαだけずれていても良い。第１平面パターンＰ１対して、第２平面パターンＰ２がＸ方向にαだけずれた場合、第１平面パターンＰ１の右側の辺の張り出し量はＳ３Ｒ＝（Ｓ３＋α）となり、左側の辺の張り出し量はＳ３Ｌ＝（Ｓ３－α）となる。
　本実施の形態１では、張り出し量Ｓ３を充分に確保し、減少した側の張り出し量Ｓ３Ｌ＝（Ｓ３－α）が、図４に示す、再配線ＲＭの側面上に形成されたキャップ金属膜ＣＭの膜厚よりも大きくしている。
　図４に示すように、例えばｐ型の単結晶シリコンからなる半導体基板１Ｐにはｐ型ウエル２Ｐ、ｎ型ウエル２Ｎおよび素子分離溝３が形成されており、素子分離溝３の内部には、例えば酸化シリコン膜からなる素子分離絶縁膜３ａが埋め込まれている。
　上記ｐ型ウエル２Ｐ内にはｎチャネル型ＭＩＳトランジスタ（Ｑｎ）が形成されている。ｎチャネル型ＭＩＳトランジスタ（Ｑｎ）は、素子分離溝３で規定された活性領域に形成され、ｐ型ウエル２Ｐ内に形成されたソース領域ｎｓおよびドレイン領域ｎｄと、ｐ型ウエル２Ｐ上にゲート絶縁膜ｎｉを介して形成されたゲート電極ｎｇとを有している。また、上記ｎ型ウエル２Ｎ内にはｐチャネル型ＭＩＳトランジスタ（Ｑｐ）が形成されており、ソース領域ｐｓおよびドレイン領域ｐｄと、ｎ型ウエル２Ｎ上にゲート絶縁膜ｐｉを介して形成されたゲート電極ｐｇとを有している。
　上記ｎチャネル型ＭＩＳトランジスタ（Ｑｎ）およびｐチャネル型ＭＩＳトランジスタ（Ｑｎ）の上部には、半導体素子間を接続する金属膜からなる配線が形成されている。半導体素子間を接続する配線は、一般に３層～１０層程度の多層配線構造を有しているが、図４には、多層配線の一例として、Ａｌ合金を主体とする金属膜で構成された３層の配線層（第１層Ａｌ配線５、第２層Ａｌ配線７、第３層Ａｌ配線９）が示されている。配線層とは、各配線層で形成された複数の配線を纏めて表す場合に使用する。配線層の膜厚は、第２層の配線層は第１層の配線層より厚く、第３層の配線層は第２層の配線層よりも厚い。
　ｎチャネル型ＭＩＳトランジスタ（Ｑｎ）およびｐチャネル型ＭＩＳトランジスタ（Ｑｎ）と第１層Ａｌ配線５との間、第１層Ａｌ配線５と第２層Ａｌ配線７との間、および第２層Ａｌ配線７と第３層Ａｌ配線９との間には、それぞれ酸化シリコン膜などからなる層間絶縁膜４、６、８と、３層の配線間を電気的に接続するプラグｐ１、ｐ２、ｐ３が形成されている。
　上記層間絶縁膜４は、例えば半導体素子を覆うように、半導体基板上１Ｐ上に形成され、第１層Ａｌ配線５はこの層間絶縁膜４上に形成される。第１層Ａｌ配線５は、例えば層間絶縁膜４に形成されたプラグｐ１を介して半導体素子であるｎチャネル型ＭＩＳトランジスタ（Ｑｎ）のソース領域ｎｓ、ドレイン領域ｎｄ、ゲート電極ｎｇに電気的に接続される。また、第１層Ａｌ配線５は、層間絶縁膜４に形成されたプラグｐ１を介して半導体素子であるｐチャネル型ＭＩＳトランジスタ（Ｑｐ）のソース領域ｐｓ、ドレイン領域ｐｄ、ゲート電極ｐｇに電気的に接続される。ゲート電極ｎｇ、ｐｇと第１層Ａｌ配線５との接続は図示していない。
　第２層Ａｌ配線７は、例えば層間絶縁膜６に形成されたプラグｐ２を介して第１層Ａｌ配線５に電気的に接続される。第３層Ａｌ配線９は、例えば層間絶縁膜８に形成されたプラグｐ３を介して第２層Ａｌ配線７に電気的に接続される。プラグｐ１、ｐ２、ｐ３は金属膜、例えばＷ（タングステン）膜で構成される。
　なお、多層配線（３層配線）を化学的機械研磨法(ＣＭＰ法)によりＣｕを主体とする金属膜で形成する場合は、配線とプラグとを一体に形成するデュアルダマシン法で形成してよいことは勿論である。また、層間絶縁膜４、６、８は、酸化シリコン膜（ＳｉＯ２）からなるが、炭素を含む酸化シリコン膜（ＳｉＯＣ膜）、窒素と炭素を含む酸化シリコン膜（ＳｉＣＯＮ膜）、フッ素を含む酸化シリコン膜（ＳｉＯＦ膜）の単層膜または積層膜で構成してよいことは勿論である。
　多層配線の最上層の配線層である上記第３層Ａｌ配線９の上部には、ファイナルパッシベーション膜として、例えば酸化シリコン膜、窒化シリコン膜などの単層膜、あるいはこれらの２層膜からなる表面保護膜（保護膜、絶縁膜）１０が形成されている。そして、この表面保護膜１０に形成されたパッド開口（開口）１０ａの底部に露出した最上層の配線層である第３層Ａｌ配線９は、Ａｌパッドであるパッド電極（電極パッド、第１電極パッド）９ａを構成している。
　上記第３層Ａｌ配線９は、パッド電極９ａに限らず、例えばパッド電極９ａに一体に形成される配線、パッド電極９ａに接続されない配線などを構成する。パッド電極９ａに接続されない配線は、半導体素子間あるいは回路間を電気的に接続し、半導体集積回路を構成する配線として使用される。
　上記表面保護膜１０の上には、パッド開口１０ａの上方に開口１１ａを有する絶縁膜である下地絶縁膜（有機保護膜、絶縁膜）１１が形成されている。また、下地絶縁膜１１の上には、下地絶縁膜１１の開口１１ａ、および表面保護膜１０のパッド開口１０ａを通じてパッド電極９ａに電気的に接続された再配線ＲＭが形成されている。開口１１ａはパッド開口１０ａよりも大きく、パッド開口１０ａの全周において、パッド開口１０ａを規定する表面保護膜１０の上面（表面）が開口１１ａから露出している。再配線ＲＭは、パッド開口１０ａおよび開口１１ａを完全に埋めるように、パッド開口１０ａおよび開口１１ａの内部に形成され、さらに、下地絶縁膜１１の上に延在している。
　パッド電極９ａと再配線ＲＭとの間には、下地金属膜ＵＭが介在している。下地金属膜ＵＭは、パッド電極９ａに接触して電気的に接続されており、表面保護膜１０のパッド開口１０ａおよび下地絶縁膜１１の開口１１ａにおいて、表面保護膜１０の側面（側壁）および上面、ならびに下地絶縁膜１１の側面（側壁）に沿って形成され、さらに、下地絶縁膜１１の上面に延在している。下地金属膜ＵＭは、上面と下面とを有し、上面は再配線ＲＭと接しており、下面は、パッド電極９ａ、表面保護膜１０および下地絶縁膜１１に接している。後述するが、下地金属膜ＵＭは、３層構造の下地バリア膜で構成されており、パッド電極９ａの側から第１下地バリア膜ＵＭ１、第２下地バリア膜ＵＭ２および第３下地バリア膜ＵＭ３からなる。したがって、下地金属膜ＵＭの上面とは、第３下地バリア膜ＵＭ３の上面を意味し、下面とは第１下地バリア膜ＵＭ１の下面を意味する。第１下地バリア膜ＵＭ１、第２下地バリア膜ＵＭ２および第３下地バリア膜ＵＭ３は、例えば、順に、チタン（Ｔｉ）膜、窒化チタン（ＴｉＮ）膜およびチタン（Ｔｉ）膜で構成し、それらの膜厚は、順に、１０ｎｍ、５０ｎｍおよび１０ｎｍとする。この膜厚は、下地絶縁膜１１の上面上における膜厚である。
　また、再配線ＲＭは、上面、下面および側面を有しており、再配線ＲＭの下面は下地金属膜ＵＭの上面と接している。再配線ＲＭは、銅（Ｃｕ）を主成分とする銅膜であり、シード膜ＲＭ１とメッキ膜ＲＭ２との積層構造で構成されている。したがって、再配線ＲＭの下面とは、シード膜ＲＭ１の下面を意味し、上面とはメッキ膜ＲＭ２の上面を意味する。また、再配線ＲＭの側面（側壁）とは、シード膜ＲＭ１とメッキ膜ＲＭ２の積層構造の側面（側壁）を意味する。シード膜ＲＭ１およびメッキ膜ＲＭ２の膜厚は、それぞれ、２５０ｎｍおよび６μｍである。ちなみに、第３層Ａｌ配線９の膜厚は、４００ｎｍ～６００ｎｍであるので、再配線ＲＭは、第３層Ａｌ配線９、言い換えると、パッド電極９ａが形成された配線９の１０倍以上の膜厚を有する低抵抗の配線である。つまり、再配線ＲＭの膜厚は、パッド電極９ａが形成された配線９の膜厚よりも大きい。望ましくは、再配線ＲＭの膜厚はパッド電極９ａが形成された配線９の膜厚の１０倍以上である。
　再配線ＲＭの上面および側面に接して、再配線ＲＭを完全に覆うようにキャップ金属膜ＣＭが形成されている。キャップ金属膜ＣＭは、再配線ＲＭの上面の全体および側面の全体を覆っている。キャップ金属膜ＣＭは、再配線ＲＭを構成するシード膜ＲＭ１の側面（側壁）およびメッキ膜ＲＭ２の側面（側壁）を完全に覆っている。キャップ金属膜ＣＭは、上面と下面を有し、下面は再配線ＲＭの上面および再配線ＲＭの側面と接しており、再配線ＲＭの外側の領域（再配線ＲＭが形成されていない領域）において、下地金属膜ＵＭの上面と直接接している。
　下地金属膜ＵＭおよびキャップ金属膜ＣＭは、再配線ＲＭの側面（厳密には、再配線ＲＭの側面の下端部分）から再配線ＲＭの外側の領域（再配線ＲＭが形成されていない領域）に張り出し部ＰＰを有しており、張り出し部ＰＰにおいて、下地金属膜ＵＭの上面とキャップ金属膜ＣＭの下面とは直接接している。また、張り出し部ＰＰの張り出し量Ｓ３は、再配線ＲＭの側面（側壁）上に形成されたキャップ金属膜ＣＭの膜厚よりも大きく、例えば、２．５μｍである。つまり、平面視において、張り出し部ＰＰの先端である下地金属膜ＵＭおよびキャップ金属膜ＣＭの端部は、再配線ＲＭの側面（側壁）上に形成されたキャップ金属膜ＣＭよりも再配線ＲＭの外側に位置している。また、張り出し部ＰＰは、平面視における再配線ＲＭの全周にわたって形成されている。張り出し量Ｓ３は、張り出し部ＰＰの幅であり、再配線ＲＭの外側の領域における、再配線ＲＭの端部から下地金属膜ＵＭまたはキャップ金属膜ＣＭの端部までの距離を意味する。
　後述するが、キャップ金属膜ＣＭは、第１キャップバリア膜ＣＭ１および第２キャップバリア膜ＣＭ２の積層構造からなり、第１キャップバリア膜ＣＭ１の下面が再配線ＲＭの上面および側面と接しており、さらに、下地金属膜ＵＭの上面（正確には、第３下地バリア膜ＵＭ３の上面）と接している。キャップ金属膜ＣＭの下面は、第１キャップバリア膜ＣＭ１の下面を意味し、上面は、第２キャップバリア膜ＣＭ２の上面を意味する。第１キャップバリア膜ＣＭ１は、チタン（Ｔｉ）膜からなり、その膜厚は５０ｎｍであり、第２キャップバリア膜ＣＭ２は、パラジウム（Ｐｄ）膜からなり、それらの膜厚は、１７５ｎｍである。この膜厚は、再配線ＲＭの上面上における膜厚である。
　また、下地金属膜ＵＭを構成する第３下地バリア膜ＵＭ３とキャップ金属膜ＣＭを構成する第１キャップバリア膜ＣＭ１を同じ材質からなる膜（具体的にはチタン（Ｔｉ）膜）としたことで、張り出し部ＰＰにおける下地金属膜ＵＭとキャップ金属膜ＣＭの接着性を強固にでき、再配線ＲＭを構成する銅の移動（拡散）を低減している。
　また、張り出し部ＰＰにおいては、下地金属膜ＵＭ上にキャップ金属膜ＣＭが積層した構造となっているため、再配線ＲＭの外側の領域の張り出し部ＰＰにおける下地金属膜ＵＭの膜厚とキャップ金属膜ＣＭの膜厚との和は、再配線ＲＭと下地絶縁膜１１とに挟まれた下地金属膜ＵＭの膜厚よりも厚くなっている。また、再配線ＲＭの外側の領域の張り出し部ＰＰにおける下地金属膜ＵＭの膜厚と第１キャップバリア膜ＣＭ１の膜厚との和は、再配線ＲＭと下地絶縁膜１１とに挟まれた下地金属膜ＵＭの膜厚よりも厚くなっている。
　再配線ＲＭを全体的に覆うように保護膜１２が形成されている。保護膜１２は、再配線ＲＭの上面（正確には、キャップ金属膜ＣＭの上面、第２キャップバリア膜ＣＭ２の上面）を部分的に露出する開口１２ａを有しており、再配線ＲＭの露出部分が外部パッド電極１８となっている。
　ここで、下地絶縁膜１１および保護膜１２は、ともに、有機膜、例えば、ポリイミド系樹脂やベンゾシクロブテン系樹脂、アクリル系樹脂、エポキシ系樹脂、シリコン系樹脂等を用いることができる。
　なお、下地金属膜ＵＭおよびキャップ金属膜ＣＭは、再配線ＲＭを構成する銅（Ｃｕ）膜が銅イオンとなって外部に移動（拡散）するのを防止するものであり、再配線ＲＭとは異なる材料（別材料）で構成されている。また、下地金属膜ＵＭおよびキャップ金属膜ＣＭには、銅（Ｃｕ）膜は含まれていない。
　また、信号入出力用の再配線ＲＭを例に説明したが、電源供給用の再配線ＲＭＶおよび回路間又は素子間を接続する再配線ＲＭＳも、再配線ＲＭと同様の構造である。
＜半導体装置の特徴＞
　以下に、本実施の形態１の半導体装置の主な特徴を説明する。
　銅膜からなる再配線ＲＭは、再配線ＲＭの下面を覆い、再配線ＲＭとは異なる材料からなる下地金属膜ＵＭと、再配線ＲＭの上面および側面を覆い、再配線ＲＭとは異なる材料からなるキャップ金属膜ＣＭとで完全に囲まれている。そして、再配線ＲＭの外側の領域において、下地金属膜ＵＭとキャップ金属膜ＣＭとは張り出し部ＰＰを有しており、張り出し部ＰＰにおいて、下地金属膜ＵＭとキャップ金属膜ＣＭとが直接接触している。このような構造により、隣り合う再配線ＲＭの間に電界がかかったとしても、再配線ＲＭを構成する銅が、再配線ＲＭの外側の領域に移動（拡散）することで発生する、隣り合う再配線ＲＭ間の耐圧劣化または短絡を防止することができる。また、下地絶縁膜１１または保護膜１２を構成するポリイミド膜に含まれる水分、ハロゲンイオン等が、銅膜からなる再配線ＲＭ中に侵入するのを防止できるので、銅膜の酸化を防止でき、隣り合う再配線ＲＭ間の耐圧劣化または短絡を防止できる。
　上記張り出し部の張り出し量は、再配線ＲＭの側面を覆うキャップ金属膜ＣＭの膜厚よりも大きい。また、第１パターンに対する第２パターンのずれによって張り出し量が減少した場合にも、減少した張り出し量が、再配線ＲＭの側面を覆うキャップ金属膜ＣＭの膜厚よりも大きいので、製造ばらつきがあった場合でも、隣り合う再配線ＲＭ間の耐圧劣化または短絡を防止することができる。再配線ＲＭを構成する銅膜の酸化を防止できる。
　また、下地金属膜ＵＭの上面となる下地バリア膜とキャップ金属膜の下面となるキャップバリア膜とを同じ材質からなる膜としている。そのため、張り出し部における下地金属膜ＵＭとキャップ金属膜ＣＭとの接着性を向上でき、再配線ＲＭを構成する銅が、再配線ＲＭの外側の領域に移動（拡散）するのを十分に防止できるので、隣り合う再配線ＲＭ間の耐圧劣化または短絡、ならびに再配線ＲＭの酸化を防止することができる。
　また、平面視において、再配線ＲＭの全周にわたって張り出し部ＰＰが形成されているので、全ての方向に隣り合う再配線ＲＭとの間の耐圧劣化または短絡並びに再配線の酸化を防止することができる。
　平面視において、銅膜からなる再配線ＲＭが有する第１平面パターンＰ１よりも大きい第２平面パターンＰ２を有する下地金属膜ＵＭとキャップ金属膜ＣＭとで再配線ＲＭを完全に包み込み、再配線ＲＭの外側の領域において、下地金属膜ＵＭの上面とキャップ金属膜ＣＭの下面とが直接接触している。この構造により、隣り合う再配線ＲＭ間に高電界が印加されても、再配線ＲＭの酸化を防止でき、隣り合う再配線ＲＭ間の耐圧劣化または短絡を防止できる。また、再配線ＲＭを構成する銅膜が酸化して銅イオンが発生したとしても、再配線ＲＭの外側に銅イオンが移動（拡散）するのを防止できる。
　また、第１平面パターンＰ１の全周において、第２平面パターンＰ２は第１平面パターンＰ１よりも大きいので、全ての方向に隣り合う再配線ＲＭとの間の耐圧劣化または短絡を防止することができる。
＜半導体装置の製造方法＞
　次に、本実施の形態１の半導体装置の製造方法について説明するが、本実施の形態１の特徴である再配線の製造方法を中心に説明する。再配線の製造方法は、図４に示した断面に対応している。
　図５～図１３は、本実施の形態１の半導体装置の製造工程中の断面図である。
　図５は、複数の配線層とパッド電極が形成された半導体基板を準備する工程を示している。半導体基板１Ｐには、ｐチャネル型ＭＩＳトランジスタ（Ｑｐ）およびｎチャネル型ＭＩＳトランジスタ（Ｑｎ）が形成された後、複数の配線層からなる配線が形成されている。具体的には、図４で説明したように、３層の配線層（第１層Ａｌ配線５、第２層Ａｌ配線７、第３層Ａｌ配線９）が形成されている。そして、第３層Ａｌ配線９の上部には、表面保護膜１０が形成されているが、表面保護膜１０は、パッド開口１０ａを有しており、最上層の配線層である第３層Ａｌ配線９のパッド開口１０ａから露出した部分が、パッド電極９ａとなっている。図５に示された断面構造は、図４で説明した通りである。
　図６は、下地絶縁膜１１、下地金属膜ＵＭおよびシード膜ＲＭ１の形成工程を示している。まず、表面保護膜１０上に下地絶縁膜１１を形成するが、下地絶縁膜１１として感光性ポリイミド樹脂を用いる。表面保護膜１０上に感光性ポリイミドを塗布、露光してパッド開口１０ａおよびパッド電極９ａを露出させた後、キュアを行い硬化させる。つまり、パッド開口１０ａおよびパッド電極９ａより大きい開口１１ａを有する下地絶縁膜１１を形成する。
　次に、開口１１ａ、パッド開口１０ａを介してパッド電極９ａに電気的に接続する下地金属膜ＵＭおよびシード膜ＲＭ１を形成（堆積）する。下地金属膜ＵＭを構成する第１下地バリア膜ＵＭ１、第２下地バリア膜ＵＭ２および第３下地バリア膜ＵＭ３は、順に、チタン（Ｔｉ）膜を５～５０ｎｍ、窒化チタン（ＴｉＮ）膜を１０～１００ｎｍ、チタン（Ｔｉ）膜を５～５０ｎｍの膜厚で形成するのが適当である。ここでは、一例として、チタン（Ｔｉ）膜を１０ｎｍ、窒化チタン（ＴｉＮ）膜を５０ｎｍおよびチタン（Ｔｉ）膜を１０ｎｍとする。これらの第１下地バリア膜ＵＭ１、第２下地バリア膜ＵＭ２および第３下地バリア膜ＵＭ３は、例えば、スパッタ法により形成する。次に、スパッタ法を用いて、銅（Ｃｕ）膜からなるシード膜ＲＭ１を第３下地バリア膜ＵＭ３上に形成する。シード膜ＲＭ１は、２５０ｎｍ程度の膜厚とする。
　図７は、再配線ＲＭの形成工程のメッキ工程を示している。シード膜ＲＭ１の上に、再配線ＲＭの形成領域を露出し、再配線ＲＭが形成されない領域を覆うレジストマスク（レジストパターン）ＰＲ１を形成する。つまり、レジストマスクＰＲ１は、第１平面パターンＰ１の反転パターンとなっており、第１平面パターンＰ１に対応する開口を有している。次に、下地金属膜ＵＭおよびシード膜ＲＭ１をシード層として、電解（電気）めっき法により、銅（Ｃｕ）膜からなるメッキ膜ＲＭ２をレジストマスクＰＲ１から露出した領域のシード膜ＲＭ１上に選択的に形成する。メッキ膜ＲＭ２の膜厚は、例えば、約６μｍとする。メッキ膜ＲＭ２の膜厚は、２μｍ～１０μｍの範囲にするのが良く、メッキ膜ＲＭ２の膜厚は薄すぎると再配線ＲＭの抵抗が高くなるため、デバイスの要求を満足する抵抗値を得られる膜厚にすべきであり、ある程度の膜厚が一般的には必要となる。但し、厚すぎるとウエハの反りが大きくなり、その後のリソグラフィや加工装置で搬送エラーが発生し、加工が困難となり、製造コスト増加や生産性低下の弊害が発生する。なお、例えば、下地金属膜ＵＭ等は、パターニングの前後で同様の符号を付している。この工程で、第１平面パターンＰ１を有するメッキ膜ＲＭ２が形成される。
　図８は、再配線ＲＭの形成工程であるシード膜ＲＭ１の除去（加工）工程を示している。メッキ膜ＲＭ２形成後に、レジストマスクＰＲ１を除去する。次に、メッキ膜ＲＭ２から露出した領域のシード膜ＲＭ１を除去することで、メッキ膜ＲＭ２の下に、メッキ膜ＲＭ２と等しい平面パターンを有するパターニングされたシード膜ＲＭ１が残る。この工程で、第１平面パターンＰ１を有し、シード膜ＲＭ１とメッキ膜ＲＭ２との積層構造からなる再配線ＲＭが形成される。
　この時、メッキ膜ＲＭ２から露出した領域（言い換えると、再配線ＲＭの外側の領域）の下地金属膜ＵＭは、除去せずに残しておくことが重要である。ただし、下地金属膜ＵＭは、メッキ膜ＲＭ２から露出した領域に残っていることが重要であり、例えば、メッキ膜ＲＭ２から露出した領域の下地金属膜ＵＭを半分程度の膜厚分だけエッチングで除去しても良い。つまり、メッキ膜ＲＭ２から露出した領域の下地金属膜ＵＭの膜厚を、メッキ膜ＲＭ２で覆われた領域の下地金属膜ＵＭの膜厚の半分程度にしても良い。メッキ膜ＲＭ２から露出した領域の下地金属膜ＵＭの膜厚を薄くすることで、下地絶縁膜１１から下地金属膜ＵＭが剥離するのを防止することができる。下地金属膜ＵＭの膜厚を低減することで、下地金属膜ＵＭの持つ応力を低減して下地絶縁膜１１からの剥離を低減できるという効果が得られる。ここで、エッチングは、メッキ膜ＲＭ２またはシード膜ＲＭ１をハートマスクとして、塩素系のガスを含むドライエッチングとする。
　図９は、キャップ金属膜ＣＭを形成する工程の一部を示している。再配線ＲＭの上面および側面を完全に覆うようにキャップ金属膜ＣＭを形成（堆積）する。パターニングされる前のキャップ金属膜ＣＭは、キャップ金属材料膜と呼ぶ。キャップ金属膜ＣＭは、複数層のキャップバリア膜で構成されている。キャップ金属膜ＣＭを形成するために、第１キャップバリア膜（第１キャップ金属材料膜）ＣＭ１、第２キャップバリア膜（第２キャップ金属材料膜）ＣＭ２および第３キャップバリア膜（第３キャップ金属材料膜）ＣＭ３を順次形成する。なお、本実施の形態１においては、第３キャップバリア膜ＣＭ３もキャップ金属膜ＣＭの一部として扱う。第１キャップバリア膜ＣＭ１、第２キャップバリア膜ＣＭ２および第３キャップバリア膜ＣＭ３は、チタン（Ｔｉ）膜を１０～２００ｎｍ、パラジウム（Ｐｄ）膜を１０～２００ｎｍ、チタン（Ｔｉ）膜を１０～２００ｎｍの膜厚で形成するのが適当である。ここでは、一例として、下層のチタン（Ｔｉ）膜を１０ｎｍ、パラジウム（Ｐｄ）膜を５０ｎｍ、上層のチタン（Ｔｉ）膜を１７５ｎｍとする。第１キャップバリア膜ＣＭ１、第２キャップバリア膜ＣＭ２および第３キャップバリア膜ＣＭ３は、再配線ＲＭの側面を完全に覆うために、ＣＶＤ法などのコンフォーマルな成膜方法を用いるのが良いが、これに限るものではない。
　ここで、第３下地バリア膜ＵＭ３と接する第１キャップバリア膜ＣＭ１を、第３下地バリア膜ＵＭ３の膜と同じ材質の膜としたことで、張り出し部ＰＰにおける、第３下地バリア膜ＵＭ３と第１キャップバリア膜ＣＭ１との接着性を向上させることができる。言い換えると、積層構造の下地金属膜ＵＭの上面となる膜と、積層構造のキャップ金属膜ＣＭの下面となる膜の材質を等しくすることで、張り出し部ＰＰにおける、下地金属膜ＵＭとキャップ金属膜ＣＭとの接着性を向上でき、再配線ＲＭを構成する銅イオンの外部への移動（拡散）を防止でき、下地絶縁膜１１または保護膜１２からの水分などの侵入を防止できる。
　また、第１キャップバリア膜ＣＭ１の成膜前に、再配線ＲＭおよび下地金属膜ＵＭ（特に、第３下地バリア膜ＵＭ３）の表面に水素プラズマ処理を施し、再配線ＲＭの上面および側面ならびに下地金属膜ＵＭの上面の酸化膜を除去して清浄化し、下地金属膜ＵＭとキャップ金属膜ＣＭとの接着性を向上させておくと良い。
　次に、図９に示すように、レジストマスクＰＲ２を、第３キャップバリア膜ＣＭ３上に形成する。レジストマスクＰＲ２は、第２平面パターンＰ２に対応しており、平面視において、再配線ＲＭおよび再配線ＲＭの周囲の張り出し部ＰＰを覆い、それ以外を露出するパターンとなっている。
　図１０は、図９に続く、キャップ金属膜ＣＭを形成する工程の一部の工程を示している。レジストマスクＰＲ２から露出した領域の第３キャップバリア膜ＣＭ３をドライエッチングまたはウェットエッチングで除去し、第２平面パターンＰ２を有する第３キャップバリア膜ＣＭ３を形成する。チタン（Ｔｉ）膜からなる第３キャップバリア膜ＣＭ３は、アンモニア過水溶液を用いてウェットエッチングする。つまり、レジストマスクＰＲ２を用いて、第３キャップバリア膜ＣＭ３をパターニングする。
　次に、レジストマスクＰＲ２を除去する。そして、パターニングされたチタン（Ｔｉ）膜からなる第３キャップバリア膜ＣＭ３をハードマスクとして第２キャップバリア膜ＣＭ２をエッチングし、第２平面パターンＰ２を有する第２キャップバリア膜ＣＭ２を形成する。パラジウム（Ｐｄ）膜からなる第２キャップバリア膜ＣＭ２は、ヨウ素ヨウ化カリウム溶液を用いてウェットエッチングするが、ドライエッチング法でエッチングしても良い。つまり、第３キャップバリア膜ＣＭ３をマスクとして、第２キャップバリア膜ＣＭ２をパターニング（エッチング）する。
　第３キャップバリア膜ＣＭ３および第２キャップバリア膜ＣＭ２にウェットエッチングを施したとしても、再配線ＲＭの外側の領域である張り出し部ＰＰに下地金属膜ＵＭが存在しており、張り出し部ＰＰにおいて、キャップ金属膜ＣＭと下地金属膜ＵＭとが直接接しているので、再配線ＲＭにエッチング液が染み込むことはない。
　図１１は、図１０に続く、キャップ金属膜ＣＭを形成する工程の一部および下地金属膜ＵＭの加工工程を示している。第３キャップバリア膜ＣＭ３および第２キャップバリア膜ＣＭ２から露出した領域の第１キャップバリア膜ＣＭ１および下地金属膜ＵＭをエッチングして除去し、下地絶縁膜１１の上面を露出させる。第１キャップバリア膜ＣＭ１および下地金属膜ＵＭを、チタン（Ｔｉ）膜および窒化チタン（ＴｉＮ）膜で形成しているので、例えば、アンモニア過水溶液を用いたウェットエッチングにより、第１キャップバリア膜ＣＭ１および下地金属膜ＵＭを除去して、第２平面パターンＰ２を有する第１キャップバリア膜ＣＭ１および下地金属膜ＵＭを形成することができる。この時、チタン（Ｔｉ）膜で形成されている第３キャップバリア膜ＣＭ３も同時に除去され、第２キャップバリア膜ＣＭ２の上面が露出する。第１キャップバリア膜ＣＭ１および下地金属膜ＵＭのエッチング時間とほぼ等しくなるように第３キャップバリア膜ＣＭ３の膜厚を設定することで、第２キャップバリア膜ＣＭ２の端部に対する第１キャップバリア膜ＣＭ１および下地金属膜ＵＭのサイドエッチングを低減できる。
　上記工程を経て、隣り合う再配線ＲＭの上面および側面の覆うキャップ金属膜ＣＭおよび下面に接する下地金属膜ＵＭが分離され、等しい第２平面パターンＰ２を有するキャップ金属膜ＣＭと下地金属膜ＵＭとが形成される。ここで、「等しい」とは、上記のサイドエッチングによる寸法差が有る場合も含んでいる。
　第３キャップバリア膜ＣＭ３、第１キャップバリア膜ＣＭ１および下地金属膜ＵＭにウェットエッチングを施したとしても、再配線ＲＭの外側の領域である張り出し部ＰＰに下地金属膜ＵＭが存在しており、張り出し部ＰＰにおいて、キャップ金属膜ＣＭと下地金属膜ＵＭとが直接接しているので、再配線ＲＭにエッチング液が染み込むことはない。
　図１２は、保護膜１２の形成工程を示している。再配線ＲＭの上面および側面を覆い、再配線ＲＭの上面に設けられた外部パッド電極１８を露出する開口１２ａを有する保護膜１２を形成する。保護膜１２は、再配線ＲＭの膜厚よりも厚く、隣り合う再配線ＲＭの間の領域で、下地絶縁膜１１の上面と接している。保護膜１２として、例えば、感光性ポリイミド樹脂を用いる。再配線ＲＭ上に感光性ポリイミドを塗布、露光して外部パッド電極１８を露出させる開口１２ａを形成した後、キュアを行い硬化させる。
　図１３は、半導体チップ１Ａの実装工程を示している。上記工程の後、半導体チップ１Ａをダイパッド部２５Ｄ上に搭載し、再配線ＲＭとリード２５Ｌとをワイヤ２７で接続した後、リード２５Ｌの一部（インナーリード部）、ダイパッド部２５Ｄ、半導体チップ１Ａおよびワイヤ２７を、封止体（封止樹脂）２６で封止して、本実施の形態１の半導体装置（半導体集積回路装置）が完成する。
　図１３に示すように、複数の再配線ＲＭを有する半導体チップ１Ａは、ダイパッド部２５Ｄに搭載され、複数のリード２５Ｌにワイヤ２７で電気的に接続されている。リード２５Ｌの一部（インナーリード部）、ダイパッド部２５Ｄ、半導体チップ１Ａおよびワイヤ２７を、例えば熱硬化性エポキシ樹脂などの封止体（封止樹脂）２６で封止されている。また、封止体２６中には、エポキシ樹脂の他にシリカ（ＳｉＯ２）等のフィラーが含有している。リード２５は、封止体２６で覆われたインナーリード部から封止体２６の外側に延在するアウターリード部を有している。
　ワイヤ２７の一端は、図４又は図１２に示す半導体チップ１Ａの再配線ＲＭの上面に形成された外部パッド電極１８に接続され、他端は、リード２５Ｌのインナーリード部に接続されている。ダイパッド部２５Ｄおよび複数のリード２５Ｌは、例えば、銅（Ｃｕ）または４２アロイ（鉄ニッケル合金）からなり、ワイヤ２７は、銅（Ｃｕ）からなる。
　外部パッド電極１８の表面にはパラジウム（Ｐｄ）膜からなる第２キャップバリア膜ＣＭ２が露出しており、銅からなるワイヤ２７がパラジウム（Ｐｄ）膜からなる第２キャップバリア膜ＣＭ２にボンディング接続されるので、安定かつ十分なボンディング強度を有する接合が可能となり、シェア強度の高い高信頼性のボンディングが可能となる。
　なお、ワイヤ２７として、表面にパラジウム（Ｐｄ）を被覆した銅ワイヤ（ＰｄコートＣｕワイヤ）、金ワイヤ（Ａｕワイヤ）を用いても良い。
　第１キャップバリア膜ＣＭ１としてチタン（Ｔｉ）膜を用いたが、Ｎｉ、Ｍｏ、Ｗ、Ｃｏ、Ｒｕ、Ｔａ等を主成分とする合金やこれら金属の積層膜であっても良い。また、第３下地バリア膜ＵＭ３としてチタン（Ｔｉ）膜を用いたが、Ｎｉ、Ｍｏ、Ｗ、Ｃｏ、Ｒｕ、Ｔａ等の金属やその窒化物、炭化物など、これら金属を主成分とする合金やこれら金属の積層膜であっても良い。
＜半導体装置の製造方法の特徴＞
　以下に、本実施の形態１の半導体装置の製造方法の主な特徴を説明する。
　図１０および図１１を用いて説明したとおり、第２キャップバリア膜ＣＭ２のエッチング工程、ならびに、第１キャップバリア膜ＣＭ１および第３キャップバリア膜ＣＭ３のエッチング工程において、再配線ＲＭの外側の領域である張り出し部ＰＰに下地金属膜ＵＭが再配線ＲＭの下から連続的に延在している。また、再配線ＲＭの側面（側壁）上に形成されたキャップ金属膜ＣＭと下地絶縁膜１１との間に下地金属膜ＵＭが存在している。したがって、上記の両エッチング工程において、再配線ＲＭを形成する銅（Ｃｕ）膜が剥離するという不良の発生を防止することができる。次に、この効果について説明する。
　図１８と図１９は、本実施の形態１の比較例である半導体装置の製造工程中の断面図である。
　図１８は、図８を用いて説明したシード膜ＲＭ１の除去工程に続いて、メッキ膜ＲＭ２から露出した領域の下地金属膜ＵＭを除去した状態を示している。上記本実施の形態１の製造方法とは異なり、シード膜ＲＭ１を除去後に、メッキ膜ＲＭ２またはシード膜ＲＭ１から露出した領域の下地金属膜ＵＭを完全に除去するため、下地金属膜ＵＭのエッチング工程においてオーバーエッチが必須となる。つまり、図１８に示すように下地金属膜ＵＭの端部が再配線ＲＭの端部から後退するサイドエッチが発生し、下地金属膜ＵＭの端部から再配線ＲＭが庇状にせり出した構造となる。
　次に、図１９に示すようにキャップ金属膜ＣＭを再配線ＲＭの上面および側面上に堆積するが、図１９の破線Ｙで囲った部分において、「段切れ」と呼ばれるキャップ金属膜ＣＭの不連続部分が発生することが本願発明者の検討により判明した。また、この段切れは、上記の下地金属膜ＵＭのサイドエッチに起因して発生すること、さらに、キャップ金属膜ＣＭのエッチング工程において、段切れ部からエッチング液が再配線ＲＭまたは再配線ＲＭの下の下地金属膜ＵＭに染み込み、再配線ＲＭの一部が剥離することが判明した。
　比較例では、シード膜ＲＭ１を除去後に、連続して、メッキ膜ＲＭ２から露出した領域の下地金属膜ＵＭを完全に除去している。しかし、本実施の形態１では、再配線ＲＭの外側の領域のキャップ金属膜ＣＭを除去する段階まで下地金属膜ＵＭは残しておき、キャップ金属膜ＣＭの除去に続いて（同一工程であっても良い）、再配線ＲＭの外側の領域の下地金属膜ＵＭ除去するため、上記の段切れを防止することができ、再配線ＲＭの剥離を防止できる。
　また、外部パッド電極１８の表面にはパラジウム（Ｐｄ）膜からなる第２キャップバリア膜ＣＭ２が露出しており、銅からなるワイヤ２７がパラジウム（Ｐｄ）膜からなる第２キャップバリア膜ＣＭ２にボンディング接続されるので、安定かつ十分なボンディング強度を有する接合が可能となる。
　＜変形例１＞
　図１４は、本実施の形態１の変形例１である半導体装置の製造工程中の断面図である。
　半導体チップ１Ｂの製造方法では、図８を用いて説明したシード膜ＲＭ１の除去工程と、図９を用いて説明したキャップ金属膜ＣＭの形成工程との間に、再配線ＲＭの側面（側壁）を順テーパにする工程を追加する。具体的には、再配線ＲＭに対してアルゴン（Ａｒ）スパッタエッチングを施すことで、断面視にて、側面が順テーパとなった台形形状の再配線ＲＭａを得ることができる。台形形状とは、再配線ＲＭａの下面が上面よりも広い形状、または、断面視において、下面の幅が上面の幅よりも大きい形状とも言える。また、再配線ＲＭａは、シード膜ＲＭ１ａとメッキ膜ＲＭ２ａの積層構造となっており、シード膜ＲＭ１ａとメッキ膜ＲＭ２ａの側面は、連続的な順テーパとなっている。
　図７を用いて説明した電解めっき法でメッキ膜ＲＭ２を形成した場合、レジストマスクＰＲ１の側面が順テーパとなっているため、メッキ膜ＲＭ２の側面は逆テーパとなり、メッキ膜ＲＭ２の断面視における形状は逆台形形状となる。側面が逆テーパの場合、再配線ＲＭの側面を覆うように形成するキャップ金属膜ＣＭの被覆性が低下して、不連続部またはピンホールをともなうキャップ金属膜ＣＭとなってしまう。そのため、キャップ金属膜ＣＭのウェットエッチング工程でエッチング液が再配線ＲＭに染み込み、再配線ＲＭの側面がエッチングされる（異常エッチング）現象が発生することが、本願発明者の検討で判明した。
　再配線ＲＭの側面を順テーパにすることで、キャップ金属膜ＣＭの不連続部またはピンホールの発生を防止でき、再配線ＲＭの異常エッチングを防止することができる。
　上記工程の後、実施の形態１のキャップ金属膜ＣＭの形成工程が続く。
　＜変形例２＞
　図１５は、本実施の形態１の変形例２である半導体装置の製造工程中の断面図である。
　半導体チップ１Ｃの製造方法では、図８を用いて説明したシード膜ＲＭ１の除去工程と、図９を用いて説明したキャップ金属膜ＣＭの形成工程との間に、再配線ＲＭの肩部または側面全体を丸める工程を追加する。具体的には、再配線ＲＭにリフロー（熱処理）を施すことにより、肩部が丸くなった再配線ＲＭｂとすることができる。例えば、水素（Ｈ２）プラズマ処理や水素（Ｈ２）雰囲気で３００℃～４５０℃程度の温度でアニールすることにより再配線ＲＭの銅膜の表面の酸化膜を還元した上で、３００℃～４５０℃でアニールして銅膜をリフローする。また、再配線ＲＭｂは、シード膜ＲＭ１ｂとメッキ膜ＲＭ２ｂの積層構造となっている。
　再配線ＲＭの肩部が丸くなり、側面が滑らかになることで、キャップ金属膜ＣＭの被覆性が向上し、キャップ金属膜ＣＭの不連続部またはピンホールに起因する、再配線ＲＭの異常エッチングを防止することができる。
　上記工程の後、実施の形態１のキャップ金属膜ＣＭの形成工程が続く。
　＜変形例３＞
　図１６は、本実施の形態１の変形例３である半導体装置の製造工程中の断面図である。
　図１６は、図４に示す半導体チップ１Ａの変形例である半導体チップ１Ｄを示しており、半導体チップ１Ａと異なる点は、表面保護膜１０の上に下地絶縁膜１１を介在させることなく再配線ＲＭを配置している。下地金属膜ＵＭは、パッド電極９ａに接触して電気的に接続されており、表面保護膜１０のパッド開口１０ａにおいて、表面保護膜１０の側壁および上面に延在している。下地金属膜ＵＭの下面は、表面保護膜１０の上面に接している。再配線ＲＭの下面に接する下地金属膜ＵＭおよびキャップ金属膜ＣＭは、実施の形態１と同様である。また、その他の構造、製造方法も実施の形態１と同様である。
　再配線ＲＭの下面を下地金属膜ＵＭで、上面および側面をキャップ金属膜ＣＭで、完全に被覆し、張り出し部ＰＰで下地金属膜ＵＭとキャップ金属膜ＣＭとが直接接触した構造としたことで、再配線ＲＭを構成する銅が銅イオンとなって外部へ移動（拡散）するのを防止できる。また、保護膜１２または封止体２６に含まれる水分やハロゲンイオンなどにより再配線ＲＭを構成する銅膜が酸化されるのを防止することができる。つまり、隣り合う再配線ＲＭ間の電気的信頼性を向上できるため、図４に示した下地絶縁膜１１を省略することができる。
　再配線ＲＭおよび表面保護膜の上に、有機膜からなる保護膜１２を設けているので、半導体チップ１Ｄを、図１３に示すように、シリカを含む封止体２６で封止したとしても、封止体２６と表面保護膜１０とが接触することに起因する表面保護間膜１０のクラックを防止することができる。
　また、上記のとおり、隣り合う再配線ＲＭ間の電気的信頼性を向上できるので、下地絶縁膜１１だけでなく、保護膜１２も省略しても良い。封止体２６に水分やハロゲンイオンが含まれていたとしても、上記の構造としたことで、再配線ＲＭ中への水分やハロゲンイオンの侵入を防止することができる。
　＜変形例４＞
　図１７は、本実施の形態１の変形例４である半導体装置の製造工程中の断面図である。
　図１７は、図１３で説明した実装工程の変形例である。半導体チップ１Ａを、接着層３９を介して配線基板３０上に搭載し、再配線ＲＭとボンディングフィンガ３２とをワイヤ３７で接続した後、配線基板３０の上面側、半導体チップ１Ａ、および、ワイヤ３７を、封止体（封止樹脂）３８で封止して、変形例４の半導体装置（半導体集積回路装置）が完成する。
　図１７に示すように、配線基板３０は、絶縁層からなるコア層３１の上面には導体層からなる複数のボンディングフィンガ３２を有し、下面には導体層からなる複数のランド３３を有する。複数のボンディングフィンガ３２間および複数のランド３３間は、絶縁層からなるソルダレジスト３５によって電気的に絶縁されている。さらに、ボンディングフィンガ３２とランド３３とは、コア層３１に形成された導体層からなるビア内配線３４を介して電気的に接続されており、ランド３３には、半田からなるバンプ電極３６が接続されている。さらに、封止体３８は、熱硬化性エポキシ樹脂などからなり、シリカ（ＳｉＯ２）等のフィラーを含有している。
　ワイヤ３７の一端は、図４又は図１６に示す半導体チップ１Ａの再配線ＲＭの上面に形成された外部パッド電極１８に接続され、他端は、ボンディングフィンガ３２に接続されている。ワイヤ２７は、銅（Ｃｕ）ワイヤであるが、表面にパラジウム（Ｐｄ）を被覆した銅ワイヤ（ＰｄコートＣｕワイヤ）、金ワイヤ（Ａｕワイヤ）を用いても良い。
　また、外部パッド電極１８とボンディングフィンガ３２間をワイヤで電気的に接続する例を説明したが、再配線ＲＭの上面の外部パッド電極１８に半田ボールを形成し、半田ボールで外部パッド電極１８とボンディングフィンガ３２間を電気的に接続しても良い。その場合には、半導体チップ１Ａの再配線ＲＭが形成された側を、配線基板３０の上面側に対向させて、外部パッド電極１８とボンディングフィンガ３２間を半田ボールで接続すると良い。
　なお、半導体チップ１Ａに代えて、半導体チップ１Ｂ～１Ｆとしても良い。
（実施の形態２）
　実施の形態２は、実施の形態１の半導体装置の製造方法の変形例に対応している。
　図２０および図２１は、実施の形態２の半導体装置の製造工程中の断面図である。実施の形態１の半導体装置と区別するために、実施の形態２の半導体装置を半導体チップ１Ｅと表示している。実施の形態１の製造方法と共通する部分には同様の符号を付している。
　実施の形態１の図８を用いて説明したシード膜ＲＭ１の除去工程に続いて、シード膜ＲＭ１から露出した領域の下地金属膜ＵＭを除去する。実施の形態１の製造方法とは異なり、シード膜ＲＭ１を除去後に、シード膜ＲＭ１から露出した領域の下地金属膜ＵＭを完全に除去するため、下地金属膜ＵＭのエッチング工程においてオーバーエッチが必須となる。つまり、図２０に示すように下地金属膜ＵＭａの端部が再配線ＲＭの端部から後退するサイドエッチが発生し、下地金属膜ＵＭａの端部から再配線ＲＭが庇状にせり出した構造となる。つまり、再配線ＲＭにせり出し部が出来、再配線ＲＭと下地絶縁膜１１との間に空間（スリット、ギャップ）が出来てしまう。再配線ＲＭは、シード膜ＲＭ１とメッキ膜ＲＭ２の積層構造、下地金属膜ＵＭａは、第１下地バリア膜ＵＭ１ａ、第２下地バリア膜ＵＭ２ａ、および、第３下地バリア膜ＵＭ３ａの積層構造である。
　次に、再配線ＲＭにエッチングを施し、再配線ＲＭの側面が下地金属膜ＵＭａの側面と一致するまで、または、下地金属膜ＵＭａの側面よりも再配線ＲＭの内部側となるまで再配線ＲＭを削り込む。つまり、上記せり出し部をエッチングで除去する。こうして、図２１に示すように、下地金属膜ＵＭａの側面と一致した側面を有する再配線ＲＭｃを形成する。再配線ＲＭｃは、シード膜ＲＭ１ｃとメッキ膜ＲＭ２ｃの積層構造となっている。また、上記のとおり、再配線ＲＭｃの側面が、下地金属膜ＵＭａの側面よりも再配線ＲＭｃの内部側となっている方が好ましい。
　なお、上記の下地金属膜ＵＭに対するウェットエッチングは、例えば、アンモニア過水溶液を用いる。そして、再配線ＲＭに対するエッチングは、ウェットエッチングまたはドライエッチングのどちらでも良い。
　上記エッチング工程の後に、実施の形態１のキャップ金属膜ＣＭの形成工程以降の工程を実施して半導体チップ１Ｅを有する半導体装置が完成するが、上記せり出し部を除去しているので、キャップ金属膜ＣＭの段切れに起因する再配線ＲＭｃの剥離を防止することができる。そして、キャップ金属膜ＣＭの下面が、下地金属膜ＵＭの側面または上面と接触する構造にできるので、再配線ＲＭｃを構成する銅膜の酸化または銅イオンの移動（拡散）を防止することができる。
　＜変形例５＞
　変形例５は、実施の形態２の半導体装置の製造方法の変形例に対応している。
　図２２は、実施の形態２の変形例５である半導体装置の製造工程中の断面図である。実施の形態２の半導体装置と区別するために、変形例５の半導体装置を半導体チップ１Ｆと表示している。実施の形態１または２の製造方法と共通する部分には同様の符号を付している。
　実施の形態２において、図２０を用いて説明した下地金属膜ＵＭのエッチング工程の後に、再配線ＲＭのせり出し部の下の空間を埋めるために再配線ＲＭにスパッタエッチングを施す。図２０に示す再配線ＲＭに対して、アルゴン（Ａｒ）スパッタエッチングを施すことで、図２２に示すように、断面視にて、側面が順テーパとなった台形形状の再配線ＲＭｄを得ることができる。さらに、アルゴンスパッタエッチングの工程において、再配線ＲＭｃのせり出し部と下地絶縁膜１１の間をリデポ物（再付着物）１３で埋めることができる。再配線ＲＭｄは、シード膜ＲＭ１ｄとメッキ膜ＲＭ１ｄの積層構造である。
　上記スパッタエッチング工程の後に、実施の形態１のキャップ金属膜ＣＭの形成工程以降の工程を実施して半導体チップ１Ｆを有する半導体装置が完成する、上記空間が埋まっているので、キャップ金属膜ＣＭの段切れを防止することができ、再配線ＲＭｄの剥がれを防止することができる。
　以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
　例えば、実施の形態２において、せり出し部をエッチング除去する代わりに、変形例２のリフローを施すことで、再配線ＲＭのせり出し部と下地絶縁膜１１との間の空間をなくすこともできる。また、実施の形態２または変形例５の半導体チップ１Ｅまたは１Ｆに、変形例４の実装工程を適用しても良い。
　その他、上記実施の形態に記載された内容の一部を以下に記載する。
　［付記１］
　（ａ）半導体基板の主面上にパッド電極を形成する工程、
　（ｂ）前記パッド電極上に開口を有する第１絶縁膜を形成する工程、
　（ｃ）前記第１絶縁膜上に、前記開口を介して前記パッド電極に電気的に接続する下地金属膜を形成する工程、
　（ｄ）前記下地金属膜上に、前記下地金属膜を介して前記パッド電極に電気的に接続する再配線を形成する工程、
　（ｅ）前記再配線の上面および側面を覆うキャップ金属膜を形成する工程、
　を有し、
　前記工程（ｄ）は、
　（ｄ-１）前記下地金属膜上に、前記下地金属膜を介して前記パッド電極に電気的に接続する前記再配線を形成する工程、
　（ｄ-２）前記再配線から露出する領域の前記下地金属膜を完全にエッチングする工程、
　（ｄ-３）その後、前記再配線をウエットエッチして後退させる工程、
　を含み、
　前記工程（e）は、
　（ｅ-１）前記半導体基板の主面の全面上に、キャップバリア膜を形成する工程、
　（ｅ-２）前記キャップバリア膜をパターニングすることによって、前記キャップ金属膜を形成する工程、
　を含む、半導体装置の製造方法。
[付記２]
　前記付記１に記載の半導体装置の製造方法において、
　前記再配線は、Ｃｕ膜からなり、前記パッド電極はＡｌ膜からなる、半体装置の製造方法。
[付記３]
　前記付記１に記載の半導体装置の製造方法において、
　前記再配線の膜厚は、前記パッド電極の膜厚よりも厚く、前記パッド電極は複数の配線層の中で最も厚い、半導体装置の製造方法。
［付記４］
　半導体基板と、
　前記半導体基板上に形成された複数の配線層と、
　前記複数の配線層の最上層に形成されたパッド電極と、
　前記パッド電極上に開口を有する絶縁膜と、
　前記絶縁膜上に形成され、第１下面と第１上面を有する下地金属膜と、
　前記下地金属膜の前記第１上面に形成され、第２下面と第２上面と、側面とを有する再配線と、
　前記再配線の前記第２上面および前記側面を覆うように形成され、第３下面と第３上面を有するキャップ金属膜と、
　を有し、
　前記再配線は、第１平面パターンを有し、
　前記下地金属膜および前記キャップ金属膜は、前記第１平面パターンよりも大きい第２平面パターンを有し、
　前記再配線の外側において、前記下地金属膜の前記第１上面と前記キャップ金属膜の前記第３下面とは接している、半導体装置。
［付記５］
　前記付記４に記載の半導体装置において、
　前記第１平面パターンの全周囲において、前記第２平面パターンは、前記第１平面パターンよりも大きく、
　前記再配線の外側において、前記下地金属膜の前記第１上面と前記キャップ金属膜の前記第３下面とは接している、半導体装置。
ＣＭ　キャップ金属膜
ＣＭ１、ＣＭ２、ＣＭ３　キャップバリア膜
ＰＰ　張り出し部
ＰＲ　レジストマスク
ｐ１、ｐ２、ｐ３　プラグ
Ｐ１　第１平面パターン
Ｐ２　第２平面パターン
Ｑｎ　ｎチャネル型ＭＩＳトランジスタ
Ｑｐ　ｐチャネル型ＭＩＳトランジスタ
ＲＭ、ＲＭａ、ＲＭｂ、ＲＭｃ、ＲＭｄ、ＲＭＳ、ＲＭＶ　再配線
ＲＭ１　シード膜
ＲＭ２　メッキ膜
ＵＭ　下地金属膜
ＵＭａ、ＵＭ１、ＵＭ２、ＵＭ３　下地バリア膜
１Ａ、１Ｂ、１Ｃ、１Ｄ、１Ｅ、１Ｆ　半導体チップ
１Ｐ　半導体基板
２Ｐ　ｐ型ウエル
２Ｎ　ｎ型ウエル
３　素子分離溝
３ａ　素子分離絶縁膜
４，６，８　層間絶縁膜
５、７、９　Ａｌ配線
９ａ　パッド電極
１０　表面保護膜
１０ａ　パッド開口
１１　下地絶縁膜
１１ａ　開口
１２　保護膜
１３　再付着物
１８　外部パッド電極
２５Ｄ　ダイパッド部
２５Ｌ　リード
２６、３８　封止体
２７、３７　ワイヤ
３０　配線基板
３１　コア層
３２　ボンディングフィンガ
３３　ランド
３４　ビア内配線
３５　ソルダレジスト
３６　バンプ電極
３９　接着層

Claims (19)

  1. 　半導体基板と、
    　前記半導体基板上に形成された複数の配線層と、
    　前記複数の配線層の最上層に形成されたパッド電極と、
    　前記パッド電極上に開口を有する絶縁膜と、
    　前記絶縁膜上に形成された下地金属膜と、
    　前記下地金属膜上に形成された再配線と、
    　前記再配線の上面および側面を覆うように形成されたキャップ金属膜と、
    　を有し、
    　前記再配線の外側の領域において、前記再配線の側壁上に形成された前記キャップ金属膜と前記絶縁膜との間には、前記下地金属膜が形成されており、
    　前記再配線と前記下地金属膜は別材料で形成されており、
    　前記再配線と前記キャップ金属膜は別材料で形成されており、
    　前記再配線の外側の領域において、前記下地金属膜と前記キャップ金属膜とが直接接している、半導体装置。
  2. 　請求項１に記載の半導体装置であって、
    　前記再配線の外側の領域に存在する前記下地金属膜の膜厚と前記キャップ金属膜の膜厚の和は、前記再配線の下の前記下地金属膜の膜厚よりも厚い、半導体装置。
  3. 　請求項１に記載の半導体装置であって、
    　前記キャップ金属膜は、第１キャップバリア膜、第２キャップバリア膜を含む積層膜で形成されており、
    　前記第１キャップバリア膜はＴｉ膜であり、
    　前記第２キャップバリア膜はＰｄ膜であり、
    　前記下地金属膜はＴｉ膜およびＴｉＮ膜を含む積層膜である、半導体装置。
  4. 　請求項１に記載の半導体装置であって、
    　前記再配線はＣｕを主成分として構成されており、
    　前記パッド電極はＡｌを主成分として構成されており、
    　前記再配線の膜厚は前記パッド電極の膜厚よりも厚い、半導体装置。
  5. 　請求項３に記載の半導体装置において、
    　前記再配線の上に形成された前記第２キャップ金属膜上に、銅ワイヤを有する、半導体装置。
  6. 　（ａ）複数の配線層と、前記複数の配線層の最上層に形成されたパッド電極とを有する半導体基板を準備する工程、
    　（ｂ）前記パッド電極上に第１開口を有する第１絶縁膜を形成する工程、
    　（ｃ）前記第１絶縁膜上に、前記第１開口を介して前記パッド電極に電気的に接続する下地金属膜を形成する工程、
    　（ｄ）前記下地金属膜上に、前記下地金属膜を介して前記パッド電極に電気的に接続する再配線を形成する工程、
    　（ｅ）前記再配線の上面および側面を覆うキャップ金属膜を形成する工程、
    　を有し、
    　前記工程（ｅ）は、
    　（ｅ‐１）前記半導体基板の主面上に、キャップ金属材料膜を形成する工程と、
    　（ｅ‐２）前記第１絶縁膜上の前記キャップ金属材料膜をエッチングすることにより、前記キャップ金属膜を形成する工程と、を含み、
    　前記工程（ｅ‐２）における前記エッチングは、前記下地金属膜の一部が前記再配線の外側の領域に存在する状態において施され、
    　前記工程（ｅ‐２）の後では、前記再配線の外側の領域において、前記下地金属膜と前記キャップ金属膜とが直接接している、半導体装置の製造方法。
  7. 　請求項６に記載の半導体装置の製造方法において、
    　前記再配線と前記下地金属膜は別材料で形成されており、
    　前記再配線と前記キャップ金属膜は別材料で形成されている、半導体装置の製造方法。
  8. 　請求項６に記載の半導体装置の製造方法において、
    　前記キャップ金属材膜料は、第１キャップバリア膜、第２キャップバリア膜および第３キャップバリア膜を含む積層膜で形成されており、
    　前記下地金属膜と前記第３キャップバリア膜は同じ材料を含む、半導体装置の製造方法。
  9. 　請求項６に記載の半導体装置の製造方法において、
    　前記工程（d）は、
    　（ｄ‐１）前記下地金属膜上にシード膜を形成する工程と、
    　（ｄ‐２）前記シード膜上に前記シード膜の一部を露出するレジストパターンを形成する工程と、
    　（ｄ‐３）前記レジストパターンから露出する前記シード膜上に電気メッキにより前記再配線を形成する工程と、
    　（ｄ‐４）前記レジストパターンを除去する工程と、
    　（ｄ‐５）前記再配線の外側の領域の前記シード膜を除去する工程と、
    　を含み、
    　前記工程（ｅ）において、
    　前記キャップ金属膜は、前記シード膜の側面を覆うように形成される、半導体装置の製造方法。
  10. 　請求項６に記載の半導体装置の製造方法において、
    　前記工程（ｅ-２）は、前記下地金属膜のウエットエッチをおこなう工程を含む、半導体装置の製造方法。
  11. 　請求項６に記載の半導体装置の製造方法において、
    　前記再配線はＣｕを主成分として構成されており、
    　前記パッド電極はＡｌを主成分として構成されており、
    　前記再配線の膜厚は前記パッド電極の膜厚よりも厚い、半導体装置の製造方法。
  12. 　請求項６に記載の半導体装置の製造方法において、
    　前記第１絶縁膜と前記パッド電極の間には第２絶縁膜が形成されており、
    　前記第２絶縁膜は、前記第１絶縁膜の前記第１開口内に、前記第１開口より小さい第２開口を有する、半導体装置の製造方法。
  13. 　請求項６に記載の半導体装置の製造方法において、さらに、
    　前記工程（ｅ）の後、前記キャップ金属膜上に第３開口を有する第３絶縁膜を形成する工程、を有し、
    　前記第１絶縁膜と前記第３絶縁膜の夫々は、ポリイミド膜を含む、半導体装置の製造方法。
  14. 　請求項６に記載の半導体装置の製造方法において、
    　前記再配線の上の前記キャップ金属膜に、銅ワイヤを接続する、半導体装置の製造方法。
  15. 　請求項６に記載の半導体装置の製造方法において、さらに、
    　前記工程（ｄ）の後であって、前記工程（ｅ）の前に、
    　前記下地金属膜を一部エッチングする工程を有する、半導体装置の製造方法。
  16. 　（ａ）半導体基板を準備する工程、
    　（ｂ）前記半導体基板上に絶縁膜を形成する工程、
    　（ｃ）前記絶縁膜上に、下地金属膜を形成する工程、
    　（ｄ）前記下地金属膜上に、再配線を形成する工程、
    　（ｅ）前記再配線の上面および側面を覆うように、前記絶縁膜上に、第１キャップバリア膜、第１キャップバリア膜、および、第１キャップバリア膜を順番に形成する工程、
    　（ｆ）レジストマスクを用いて、前記再配線の上面上および側面上に前記第３キャップバリア膜を残しつつ、前記絶縁膜上に形成された前記第３キャップバリア膜をパターニングする工程と、
    　（ｇ）前記レジストマスクを除去する工程と、
    　（ｈ）パターニングされた前記第３キャップバリア膜をマスクとして、前記絶縁膜上に形成された前記第２キャップバリア膜をエッチングする工程と、
    　（ｉ）前記再配線の上面上および側面上の前記第３キャップバリア膜をエッチングすると共に、前記絶縁膜上の前記第１キャップバリア膜および前記下地金属膜をエッチングする工程と、
    を有する、半導体装置の製造方法。
  17. 　請求項１６に記載の半導体装置の製造方法において、
    　前記工程（ｉ）後に、前記再配線の外側の領域であって、且つ、前記絶縁膜上の領域には、前記下地金属膜と前記第１キャップバリア膜が存在しており、
    　前記再配線の外側の領域に存在する前記下地金属膜の膜厚と前記第１キャップバリア膜の膜厚の和は、前記再配線下の前記下地金属膜の膜厚よりも厚い、半導体装置の製造方法。
  18. 　請求項１６に記載の半導体装置の製造方法において、
    　前記第１、第２および第３キャップバリア膜は、それぞれＴｉ膜，Ｐｄ膜およびＴｉ膜であり、
    　前記下地金属膜は、Ｔｉ膜，ＴｉＮ膜およびＴｉ膜を含む積層膜である、半導体装置の製造方法。
  19. 　請求項１６に記載の半導体装置の製造方法において、
    　前記（ｉ）工程の後、前記再配線の上面に形成されている前記第２キャップバリア膜は露出しており、
    　前記（ｉ）工程の後に、更に、
    　（ｊ）前記第２キャップバリア膜上に、銅ワイヤを形成する工程、
    を有する、半導体装置の製造方法。
     
PCT/JP2014/080072 2014-11-13 2014-11-13 半導体装置およびその製造方法 WO2016075791A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP14890461.8A EP3220410A4 (en) 2014-11-13 2014-11-13 Semiconductor device and manufacturing method for same
JP2015545230A JPWO2016075791A1 (ja) 2014-11-13 2014-11-13 半導体装置およびその製造方法
PCT/JP2014/080072 WO2016075791A1 (ja) 2014-11-13 2014-11-13 半導体装置およびその製造方法
CN201480027415.6A CN105793964A (zh) 2014-11-13 2014-11-13 半导体器件及其制造方法
US14/891,319 US10083924B2 (en) 2014-11-13 2014-11-13 Semiconductor device and manufacturing method thereof
TW104135663A TW201630075A (zh) 2014-11-13 2015-10-29 半導體裝置及其製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/080072 WO2016075791A1 (ja) 2014-11-13 2014-11-13 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
WO2016075791A1 true WO2016075791A1 (ja) 2016-05-19

Family

ID=55953904

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/080072 WO2016075791A1 (ja) 2014-11-13 2014-11-13 半導体装置およびその製造方法

Country Status (6)

Country Link
US (1) US10083924B2 (ja)
EP (1) EP3220410A4 (ja)
JP (1) JPWO2016075791A1 (ja)
CN (1) CN105793964A (ja)
TW (1) TW201630075A (ja)
WO (1) WO2016075791A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018105258A1 (ja) * 2016-12-07 2018-06-14 日立オートモティブシステムズ株式会社 半導体装置
JP2021501459A (ja) * 2017-10-05 2021-01-14 日本テキサス・インスツルメンツ合同会社 半導体パッケージングのための構造及び方法
JP2022523016A (ja) * 2019-01-24 2022-04-21 アプライド マテリアルズ インコーポレイテッド 高度なパッケージング用途のための微細な再配線形成の方法

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102319186B1 (ko) * 2015-06-12 2021-10-28 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US9922922B1 (en) * 2016-09-16 2018-03-20 Omnivision Technologies, Inc. Microchip with cap layer for redistribution circuitry and method of manufacturing the same
CN106601715A (zh) * 2016-12-21 2017-04-26 成都芯源系统有限公司 集成电路芯片及其制作方法
JP6963396B2 (ja) * 2017-02-28 2021-11-10 キヤノン株式会社 電子部品の製造方法
JP6783688B2 (ja) * 2017-03-14 2020-11-11 エイブリック株式会社 半導体装置および半導体装置の製造方法
CN109273483B (zh) * 2017-07-17 2021-04-02 京东方科技集团股份有限公司 显示基板及其制备方法和显示装置
IT201700087318A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici e suo metodo di preparazione
IT201700087309A1 (it) * 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici
US10211052B1 (en) * 2017-09-22 2019-02-19 Lam Research Corporation Systems and methods for fabrication of a redistribution layer to avoid etching of the layer
KR102438179B1 (ko) * 2017-11-02 2022-08-30 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지, 및 상기 반도체 장치의 제조 방법
US10332792B1 (en) * 2017-12-14 2019-06-25 Micron Technology, Inc. Methods of fabricating conductive traces and resulting structures
US10651100B2 (en) 2018-05-16 2020-05-12 Micron Technology, Inc. Substrates, structures within a scribe-line area of a substrate, and methods of forming a conductive line of a redistribution layer of a substrate and of forming a structure within a scribe-line area of the substrate
US10847482B2 (en) * 2018-05-16 2020-11-24 Micron Technology, Inc. Integrated circuit structures and methods of forming an opening in a material
JP2020047792A (ja) * 2018-09-19 2020-03-26 株式会社東芝 半導体装置
JP2020150037A (ja) * 2019-03-11 2020-09-17 キオクシア株式会社 半導体装置およびその製造方法
US11189523B2 (en) * 2019-06-12 2021-11-30 Nanya Technology Corporation Semiconductor structure and fabrication method thereof
CN111128755B (zh) * 2019-12-30 2022-07-22 颀中科技（苏州）有限公司 封装结构及其成型方法
US11682630B2 (en) * 2020-07-31 2023-06-20 Samsung Electronics Co., Ltd. Semiconductor package
CN112888154B (zh) * 2021-01-14 2023-05-16 京东方科技集团股份有限公司 柔性线路板及制备方法、显示装置
JP2022154006A (ja) * 2021-03-30 2022-10-13 ローム株式会社 半導体装置、および半導体装置の製造方法
IT202100031340A1 (it) * 2021-12-14 2023-06-14 St Microelectronics Srl Metodo di fabbricazione di uno strato di ridistribuzione, strato di ridistribuzione, circuito integrato, e metodi per il test elettrico e la protezione del circuito integrato

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000306938A (ja) 1999-04-21 2000-11-02 Toshiba Corp 半導体集積回路装置およびその製造方法
JP2003037126A (ja) * 2001-07-24 2003-02-07 Toshiba Corp 半導体装置及びその製造方法
JP2003234348A (ja) 2002-02-08 2003-08-22 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2008042038A (ja) * 2006-08-08 2008-02-21 Renesas Technology Corp 電子装置および半導体装置
JP2010056136A (ja) * 2008-08-26 2010-03-11 Toshiba Mobile Display Co Ltd 配線、その製造方法、薄膜トランジスタおよび表示素子
JP2010171386A (ja) * 2008-12-26 2010-08-05 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2012004210A (ja) 2010-06-15 2012-01-05 Renesas Electronics Corp 半導体集積回路装置およびその製造方法
JP2012160512A (ja) * 2011-01-31 2012-08-23 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
JP2012191123A (ja) * 2011-03-14 2012-10-04 Renesas Electronics Corp 半導体集積回路装置およびその製造方法ならびにそれを用いた電子システム

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969424A (en) * 1997-03-19 1999-10-19 Fujitsu Limited Semiconductor device with pad structure
KR100306842B1 (ko) * 1999-09-30 2001-11-02 윤종용 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
JP4696532B2 (ja) 2004-05-20 2011-06-08 株式会社デンソー パワー複合集積型半導体装置およびその製造方法
TWI251284B (en) * 2004-11-12 2006-03-11 Advanced Semiconductor Eng Redistribution layer and circuit structure thereof
JP4777644B2 (ja) * 2004-12-24 2011-09-21 Ｏｋｉセミコンダクタ株式会社 半導体装置およびその製造方法
JP5007250B2 (ja) * 2008-02-14 2012-08-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2009246218A (ja) * 2008-03-31 2009-10-22 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US8841766B2 (en) * 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8324738B2 (en) * 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8450049B2 (en) * 2011-02-10 2013-05-28 Chipbond Technology Corporation Process for forming an anti-oxidant metal layer on an electronic device
JP6100480B2 (ja) * 2012-07-17 2017-03-22 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6235353B2 (ja) * 2014-01-22 2017-11-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6437246B2 (ja) * 2014-08-28 2018-12-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6355541B2 (ja) * 2014-12-04 2018-07-11 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6425532B2 (ja) * 2014-12-17 2018-11-21 ルネサスエレクトロニクス株式会社 半導体装置
JP2016127162A (ja) * 2015-01-05 2016-07-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6484490B2 (ja) * 2015-04-10 2019-03-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6456232B2 (ja) * 2015-04-30 2019-01-23 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2017045864A (ja) * 2015-08-26 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2017045900A (ja) * 2015-08-27 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000306938A (ja) 1999-04-21 2000-11-02 Toshiba Corp 半導体集積回路装置およびその製造方法
JP2003037126A (ja) * 2001-07-24 2003-02-07 Toshiba Corp 半導体装置及びその製造方法
JP2003234348A (ja) 2002-02-08 2003-08-22 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2008042038A (ja) * 2006-08-08 2008-02-21 Renesas Technology Corp 電子装置および半導体装置
JP2010056136A (ja) * 2008-08-26 2010-03-11 Toshiba Mobile Display Co Ltd 配線、その製造方法、薄膜トランジスタおよび表示素子
JP2010171386A (ja) * 2008-12-26 2010-08-05 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2012004210A (ja) 2010-06-15 2012-01-05 Renesas Electronics Corp 半導体集積回路装置およびその製造方法
JP2012160512A (ja) * 2011-01-31 2012-08-23 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
JP2012191123A (ja) * 2011-03-14 2012-10-04 Renesas Electronics Corp 半導体集積回路装置およびその製造方法ならびにそれを用いた電子システム

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of EP3220410A4
T. KANKI ET AL.: "Development of highly reliable Cu wiring of L/S=1/1 µm for chip to chip interconnection", INTERCONNECT TECHNOLOGY CONFERENCE, 2012 IEEE INTERNATIONAL, 4 June 2012 (2012-06-04)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018105258A1 (ja) * 2016-12-07 2018-06-14 日立オートモティブシステムズ株式会社 半導体装置
JP2018093129A (ja) * 2016-12-07 2018-06-14 日立オートモティブシステムズ株式会社 半導体装置
JP2021501459A (ja) * 2017-10-05 2021-01-14 日本テキサス・インスツルメンツ合同会社 半導体パッケージングのための構造及び方法
JP2022523016A (ja) * 2019-01-24 2022-04-21 アプライド マテリアルズ インコーポレイテッド 高度なパッケージング用途のための微細な再配線形成の方法
JP7423640B2 (ja) 2019-01-24 2024-01-29 アプライド マテリアルズ インコーポレイテッド 高度なパッケージング用途のための微細な再配線形成の方法

Also Published As

Publication number Publication date
EP3220410A1 (en) 2017-09-20
TW201630075A (zh) 2016-08-16
CN105793964A (zh) 2016-07-20
US20160379946A1 (en) 2016-12-29
US10083924B2 (en) 2018-09-25
EP3220410A4 (en) 2018-07-18
JPWO2016075791A1 (ja) 2017-08-24

Similar Documents

Publication Publication Date Title
WO2016075791A1 (ja) 半導体装置およびその製造方法
US10192755B2 (en) Semiconductor device and its manufacturing method
JP6355541B2 (ja) 半導体装置およびその製造方法
JP5607994B2 (ja) 半導体集積回路装置およびその製造方法
TWI536497B (zh) Semiconductor device manufacturing method and semiconductor device
JP6437246B2 (ja) 半導体装置およびその製造方法
WO2017056297A1 (ja) 半導体装置およびその製造方法
TW201903921A (zh) 半導體裝置及其製造方法
TW201921623A (zh) 半導體裝置及其製造方法
TW201816970A (zh) 半導體裝置及其製造方法
US10586777B2 (en) Semiconductor device and method of manufacturing the same
WO2014174825A1 (ja) 半導体装置
JP2015053371A (ja) 半導体装置およびその製造方法
JP2007115853A (ja) 半導体装置及びその製造方法
JP2023152318A (ja) 半導体装置およびその製造方法
JP2007258354A (ja) 半導体装置の製造方法
JP2007214363A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2015545230

Country of ref document: JP

Kind code of ref document: A

REEP Request for entry into the european phase

Ref document number: 2014890461

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014890461

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 14891319

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14890461

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE