TW201903921A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201903921A
TW201903921A TW107115517A TW107115517A TW201903921A TW 201903921 A TW201903921 A TW 201903921A TW 107115517 A TW107115517 A TW 107115517A TW 107115517 A TW107115517 A TW 107115517A TW 201903921 A TW201903921 A TW 201903921A
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Taiwan
Prior art keywords
insulating film
film
barrier metal
organic insulating
semiconductor device
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TW107115517A
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English (en)
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TWI768040B (zh
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宇佐美達矢
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日商瑞薩電子股份有限公司
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract

本發明旨在提高具有重配線之半導體裝置的可靠度或性能。 本發明之半導體裝置及其製造方法包含有形成於多層配線層中最上層之配線層的第1焊墊電極PD1、形成於第1焊墊電極PD1上之第1絕緣膜IF1、及形成於第1絕緣膜IF1上之第1有機絕緣膜PIQ1。又，半導體裝置及其製造方法包含有形成於第1有機絕緣膜PIQ1上且與第1焊墊電極PD1連接之障壁金屬膜BM3、及形成於障壁金屬膜BM3上之導電膜MF1。再者，在第1有機絕緣膜PIQ1之頂面，於障壁金屬膜BM3與第1有機絕緣膜PIQ1之間形成有由無機材料構成之第2絕緣膜IF2。

Description

半導體裝置及其製造方法
本發明係有關於半導體裝置及其製造方法，可利用於例如具有重配線之半導體裝置及其製造方法。
近年，因半導體裝置之運作高速化及小型化等要求，使用形成於半導體基板上之多層配線層的最上層配線之一部分亦即第1焊墊電極上、稱為重配線之配線。由於重配線為了使其配線電阻降低，主要使用以例如電鍍法形成之厚銅膜構成。重配線之頂面的一部分係用以與由凸塊電極或接合線等構成之外部連接用端子連接的區域，並構成第2焊墊電極。又，第2焊墊電極與印刷基板等電性連接。
舉例而言，於專利文獻1(日本專利公開公報2009-194144號)記載有於多層配線層上形成重配線之技術。 [先前技術文獻] [專利文獻]
[專利文獻1]日本專利公開公報2009-194144號
[發明欲解決之問題]
在使用重配線之半導體裝置中，為保護構成電路之配線避開水分等，而形成有聚醯亞胺等有機絕緣膜。又，重配線主要由以銅為主體之導電膜及形成於該導電膜與有機絕緣膜之間的障壁金屬膜構成。然而，在相鄰之重配線間的區域中，有製造製程進行中障壁金屬膜未去除殆盡而殘留於有機絕緣膜上之情形。結果，因本案發明人之檢討而清楚明白產生下列問題：產生相鄰之重配線間的漏電或相鄰之重配線間在HAST測試(Highly Accelerated Temperature and Humidity Stress Test：高加速溫濕度壓力測試)的壽命惡化。
又，因障壁金屬膜之材料與有機絕緣膜之材料反應，而產生障壁金屬膜含有高電阻之導電物的問題，而有重配線全體之電阻增加的問題。
再者，由於重配線周邊之層間絕緣膜構造使用聚醯亞胺等有機絕緣膜，故柔軟，重配線之機械強度弱。因此，有例如下列之問題：因於重配線上形成接合線之際的撞擊或將形成於重配線上之凸塊電極安裝於配線基板等之際的撞擊，重配線變形，抑或易於重配線產生碎裂。
其他之問題及新特徵應可從本說明書之記述及附加圖式清楚明白。 [解決問題之手段]
簡單地說明在本案揭示之實施形態中代表性者之概要，則如下述。
一實施形態之半導體裝置及其製造方法包含有形成於多層配線層中最上層之配線層的第1焊墊電極、形成於第1焊墊電極上之第1絕緣膜、及形成於第1絕緣膜上之第1有機絕緣膜。又，半導體裝置及其製造方法包含有形成於第1有機絕緣膜上且與第1焊墊電極連接之第1障壁金屬膜、及形成於第1障壁金屬膜上之第1導電膜。再者，在第1有機絕緣膜之頂面，於第1障壁金屬膜與第1有機絕緣膜之間形成有由無機材料構成之第2絕緣膜。 [發明之功效]
根據一實施形態，可使半導體裝置之可靠度提高。又，可使半導體裝置之性能提高。
[用以實施發明之形態]
在以下之實施形態中，為了方便而有其必要時，分成複數段或實施形態來說明，除了特別明示之情形外，該等並非彼此無關，有其中一者為另一者之一部分或全部之變形例、細節、補充說明等的關係。
又，在以下之實施形態，提及要件之數等(包含個數、數值、量、範圍等)時，除了特別明示之情形及原理上顯而易見地限定在特定數之情形等外，並非限定在該特定數，可為特定數以上或以下。
再者，在以下之實施形態中，其構成要件(也包含要件步驟等)除了特別明示之情形及認為原理上顯而易見為必要的情形等外，並非必要。
同樣地，在以下之實施形態中，提及構成要件等之形狀、位置關係等時，除了特別明示之情形及認為原理上顯而易見並非如此之情形等外，包含實質上與該形狀等近似或類似者等。此點在上述數值及範圍也相同。
又，在用以說明實施形態之所有圖式中，對同一構件原則上附上同一符號，而省略其反覆之說明。此外，為了易了解圖式，即使為平面圖，也有附上剖面線之情形。
＜本案發明人之檢討事項＞ 首先，使用圖18及圖19，以因本案發明人之檢討而得以明朗之問題點為檢討例來說明。
圖18顯示形成重配線RW之際的製造製程進行中之截面圖。多層配線層之最上層配線亦即第5配線M5的一部分構成第1焊墊電極PD1。由無機材料構成之絕緣膜IF1於第1焊墊電極PD1上形成為使第1焊墊電極PD1之一部分露出。於絕緣膜IF1上形成有由例如聚醯亞胺膜構成之有機絕緣膜PIQ1。於有機絕緣膜PIQ1形成有開口部OP0，重配線RW經由此開口部OP0與第1焊墊電極PD1連接。使用濺鍍法於開口部OP0內部及有機絕緣膜PIQ1上形成障壁金屬膜BM3及晶種層SD。接著，於晶種層SD上依序形成導電膜MF1及導電膜MF2。
接著，如圖19所示，在未形成導電膜MF1之區域，去除晶種層SD及障壁金屬層BM3。此時，有障壁金屬膜BM3之一部分殘留於有機絕緣膜PIQ1上的情形。因此障壁金屬膜BM3殘留於相鄰之重配線RW間(導電膜MF1間)，而產生了產生重配線RW間之漏電或在HAST測試之壽命惡化的問題。
關於此種問題之原因，將本案發明人之考察記述於以下。在此，以使用鈦作為障壁金屬膜BM3之材料且使用含有諸如C-H鍵等之碳的聚醯亞胺作為有機絕緣膜PIQ1之材料的情形說明。
障壁金屬膜BM3之鈦以濺鍍法形成於有機絕緣膜PIQ1上，此時，有鈦之一部分與聚醯亞胺中所含的碳反應而形成碳化鈦等反應產物RC之情形。此係因在濺鍍法之初始階段使用氬等氣體，因曝露在氬，聚醯亞胺表面之C-H鍵減弱。因此，形成為鈦易與聚醯亞胺反應之狀態。
由於未預料到在製造製程進行中，產生此種反應產物RC，故要以用以去除鈦之一般濕蝕刻完全除掉反應產物RC並不容易。
而且此反應產物RC具導電性。因此，當反應產物RC殘留於相鄰之重配線RW間時，有在相鄰之重配線RW間易產生漏電的問題。
又，亦有有機絕緣膜PIQ1與導電膜MF1下之障壁金屬膜BM3的一部分反應之情形。由於在此反應生成之碳化鈦電阻高於鈦，故障壁金屬膜BM3之電阻增高。即，亦有重配線RW全體之電阻增高的問題。
因而，重配線RW使用由聚醯亞胺等構成之有機絕緣膜PIQ1時，重要的是盡量抑制此種反應產物RC之產生。
(實施形態1) 本實施形態及以下實施形態之半導體裝置係包含有重配線之半導體裝置。
＜半導體裝置之構造＞ 就本實施形態之半導體裝置的構造，使用圖1及圖2來說明。圖1係本實施形態之半導體裝置亦即半導體晶片的平面佈置。圖2係圖1之A-A線的主要部分截面圖。
如圖1所示，本實施形態之半導體晶片CP俯視時呈矩形形狀。重配線RW藉由第1焊墊電極PD1與多層配線層連接，並於半導體晶片CP形成複數。重配線RW之一部分構成第2焊墊電極PD2。第2焊墊電極PD2係用以與凸塊電極或接合線等外部連接用端子TR連接之區域。此外，在圖1中，為易觀看重配線RW之形狀，而省略形成於重配線RW上之外部連接用端子TR及有機膜PIQ2。又，由於第1焊墊電極PD1實際上被重配線RW覆蓋，故以虛線顯示。
如圖2所示，在半導體晶片CP之上部，於層間絕緣膜IL4中形成有所謂金屬鑲嵌(Damascene)構造的第4配線M4。即，第4配線M4藉於形成在層間絕緣膜IL4中之溝內埋入以銅為主體之導電膜而形成。此外，在圖2中，為使說明簡略化，而顯示第4配線M4及其上層之構造，未顯示第4配線M4之下層的構造。下層之構造及其製造方法在後述圖3說明。
於第4配線M4上形成有層間絕緣膜IL5，於層間絕緣膜IL5中形成有通路V4。此外，層間絕緣膜IL5以例如氧化矽或添加了氟之氧化矽構成，通路V4由以例如鎢為主體之導電膜構成。
於層間絕緣膜IL5上形成有第5配線層M5，第5配線M5與第4配線M4藉由通路V4連接。第5配線M5係於多層配線層之最上層形成有複數之配線，其中之一部分形成為第1焊墊電極PD1。第1焊墊電極PD1以障壁金屬膜BM1、形成於障壁金屬膜BM1上之導電膜AL及形成於導電膜AL上之障壁金屬膜BM2構成。在此，障壁金屬膜BM1及障壁金屬膜BM2分別以氮化鈦或氮化鈦與鈦之積層膜構成。又，導電膜AL由以鋁為主體之導電膜構成。
於焊墊電極PD1上及層間絕緣膜IL5上形成有絕緣膜IF1。絕緣膜IF1主要為了防止水分之浸入而以耐濕性高之材料構成，由例如氮化矽或氮氧化矽構成。又，於絕緣膜IF1上形成由例如聚醯亞胺構成之有機絕緣膜PIQ1。
於有機絕緣膜PIQ1之一部分的表面上形成有絕緣膜IF2。絕緣膜IF2以無機材料構成，由例如氧化矽或氮化矽構成。換言之，絕緣膜IF2以硬度高於有機絕緣膜PIQ1及有機絕緣膜PIQ2任一者之材料形成。此外，在後述會詳細說明，在本實施形態中，絕緣膜IF2宜以不同於絕緣膜IF1之材料形成。舉例而言，以氮化矽形成絕緣膜IF1時，絕緣膜IF2宜以氧化矽形成。
焊墊電極PD1上之絕緣膜IF2一部分被去除，在由有機絕緣膜PIQ1及絕緣膜IF1構成之積層膜，開口部OP1形成為到達第1焊墊電極PD1。
又，在本實施形態中，圖示了去除開口部OP1之底面的障壁金屬膜BM2之情形。障壁金屬膜BM2係電阻高於導電膜AL之材料。因而，由於重配線RW可直接與導電膜AL連接，故可使第1焊墊電極PD1與重配線RW之間的電阻小。此外，障壁金屬膜BM2亦可不必被去除，當要使重配線RW與焊墊電極PD1間之電阻更低時，去除障壁金屬膜BM2為有效。
重配線RW形成於絕緣膜IF2上，且藉形成為填埋開口部OP1內而與第1焊墊電極PD1連接。重配線RW主要由導電膜MF1與障壁金屬膜BM3構成。在本實施形態中，例示了由障壁金屬膜BM3、形成於障壁金屬膜BM3上之晶種層SD、形成於晶種層SD上之導電膜MF1及形成於導電膜MF1上之導電膜MF2構成的重配線RW。
導電膜MF1及晶種層SD以導電膜構成，由以例如銅為主成分之材料構成。晶種層SD最後被裝入導電膜MF1而一體化，而在此為易理解發明，個別分開顯示。
導電膜MF2由不同於導電膜MF1之材料構成，由例如鎳構成。又，導電膜MF2亦可為鎳膜與金膜之積層膜。導電膜MF2係為提高與外部連接用端子TR之密合性而設的膜，當獲得所期之密合性時，亦可不形成。即，導電膜MF2與外部連接用端子TR之密合性高於導電膜MF1與外部連接用端子TR之密合性。又，為降低重配線RW全體之電阻，導電膜MF1以薄膜電阻低於導電膜MF2之材料形成，且以厚於導電膜MF2之膜厚形成。又，因同樣之理由，導電膜MF1以薄膜電阻低於障壁金屬膜BM3之材料形成，以厚於障壁金屬膜BM3之膜厚形成。
障壁金屬膜BM3係含有例如鈦、鉭或鉻之導電膜，具有防止導電膜MF1(銅)之擴散的功能。又，障壁金屬膜BM3亦可為上述材料之單層膜，亦可為也形成有例如氮化鈦或氮化鉭這樣的氮化膜之積層膜。
於重配線RW上及有機絕緣膜PIQ1上形成有有機絕緣膜PIQ2。有機絕緣膜PIQ2以與有機絕緣膜PIQ1相同之材料構成，以由例如聚醯亞胺構成之絕緣膜構成。在此，重配線RW之一部分係用以與外部連接用端子TR連接之區域，在本實施形態中，以第2焊墊電極PD2顯示。在有機絕緣膜PIQ2，開口部OP2設成使重配線RW之一部分的區域露出，即，使第2焊墊電極PD2露出。
外部連接用端子TR經由開口部OP2與重配線RW連接。外部連接用端子TR係例如凸塊電極或接合線。凸塊電極之材料可使用例如焊料或金。接合線之材料可使用例如銅或金。此外，在本實施形態中，例示了使用凸塊電極作為外部連接用端子TR之情形。
此外，在本實施形態中，例示了使用有機絕緣膜PIQ2之情形，亦可省略有機絕緣膜PIQ2。即，亦可不形成有機絕緣膜PIQ2，而於重配線RW之第2焊墊電極直接形成外部連接用端子TR。然而，由於形成有機絕緣膜PIQ2對水分從外部浸入等之抵抗性較高，故要更提高製品之可靠度時，形成有機絕緣膜PIQ2較佳。
又，在本實施形態中，去除了從重配線RW露出之區域的絕緣膜IF2。即，在相鄰之重配線RW間的區域中，去除了絕緣膜IF2。此理由係因有機絕緣膜PIQ1與有機絕緣膜PIQ2之密合性高於絕緣膜IF2與有機絕緣膜PIQ1之密合性或絕緣膜IF2與有機絕緣膜PIQ2之密合性。藉此，可使有機絕緣膜PIQ2剝離之風險減低。此外，不使用有機絕緣膜PIQ2時，亦是去除重配線RW間之絕緣膜IF2較佳。
＜半導體裝置之構造的主要特徵＞ 本實施形態之半導體裝置的構造之主要特徵係於有機絕緣膜PIQ1與障壁金屬膜BM3之間形成有無機材料之絕緣膜IF2。藉此，由於在有機絕緣膜PIQ1之頂面障壁金屬膜BM3不致與有機絕緣膜PIQ1接合，故不致形成構成有機絕緣膜PIQ1之C-H鍵與障壁金屬膜BM3反應而生成的導電性反應產物RC。
因而，未於相鄰之重配線RW間的有機絕緣膜PIQ1上產生反應產物RC。藉此，可抑制在重配線RW間產生漏電或在重配線RW間之HAST壽命降低的問題。是故，可使半導體裝置之可靠度提高。
又，由於導電膜MF1下之障壁金屬膜BM3的一部分亦不致與有機絕緣膜PIQ1反應，故不會形成碳化鈦等高電阻材料。由於絕緣膜IF2由無機材料構成，故即使障壁金屬膜BM3與絕緣膜IF2接合，亦不致生成諸如碳化鈦之金屬碳化物。因此，可防止障壁金屬膜BM3之電阻增高，而可抑制重配線RW全體之電阻增高的問題。是故，可使半導體裝置之性能提高。
又，以往，重配線RW周邊之層間絕緣膜構造由有機絕緣膜PIQ1與有機絕緣膜PIQ2構成，重配線RW之機械強度弱。因此，有下列問題：因於重配線RW上形成接合線之際的撞擊或將凸塊電極安裝於配線基板等之際的撞擊，重配線RW變形，抑或於重配線RW產生碎裂。然而，如本實施形態般，藉於導電膜MF1下之障壁金屬膜BM3與有機絕緣膜PIQ1之間形成由硬度高於有機絕緣膜PIQ1及有機絕緣膜PIQ2任一者之無機材料構成的絕緣膜IF2，可提高重配線RW之機械強度。是故，可使半導體裝置之可靠度提高。
＜半導體裝置之製造方法＞ 參照圖3~圖13，說明本實施形態之半導體裝置之製造方法。圖3係顯示第4配線M4及其下層之截面圖，圖4~圖13係顯示第4配線M4及其上層之構造的截面圖。此外，該等截面圖與圖2同樣地，對應圖1之A-A截面。
又，在此，就以5層配線層構成多層配線層作說明，積層之配線層的數可少於或多於5層。又，由於本實施形態之主要特徵在於多層配線層之上方的構造體及其製造方法，故關於形成於半導體基板之主面附近的半導體元件之具體製造方法的說明省略一部分。
首先，如圖3所示，準備由具有例如1~10Ωcm之比電阻的p型單晶矽等構成之半導體基板(半導體晶圓)SUB。然後，於半導體基板SUB形成規定活性區域之複數的元件分離區域STI。元件分離區域STI藉將由例如主要以氧化矽構成之絕緣膜埋入形成於半導體基板SUB之溝內而形成。
接著，於半導體基板SUB導入雜質而形成阱WL後，分別形成具有隔著閘極絕緣膜形成於阱WL上之閘極電極及形成於阱WL內之源極汲極區域的MISFETQ1及MISFETQ2。
然後，於半導體基板SUB上形成覆蓋MISFETQ1及MISFETQ2之層間絕緣膜IL0。層間絕緣膜IL0由例如氧化矽膜構成，可使用例如CVD法等形成。之後，使用光刻技術及乾蝕刻法，於層間絕緣膜IL0內形成接觸孔。然後，藉將由例如鎢構成之金屬膜埋入接觸孔內，而形成插栓PLG。插栓PLG連接於MISFETQ1或MISFETQ2等。
接著，於埋入了插栓PLG之層間絕緣膜IL0上形成層間絕緣膜IL1。層間絕緣膜IL1以介電常數低於氧化矽之材料構成，以諸如SiOC之含有碳的氧化矽構成。第1配線M1使用所謂之金屬鑲嵌技術形成。即，於層間絕緣膜IL1內形成溝，使用CMP(Chemical Mechanical Polishing：化學機械研磨)法埋入以例如銅為主體之導電膜，藉此，形成第1配線M1。此外，亦可於銅與層間絕緣膜IL1之間形成防止銅之擴散的障壁金屬膜。另，第1配線M1連接於插栓PLG之頂面。
接著，於層間絕緣膜IL1上將層間絕緣膜IL2形成為覆蓋第1配線M1。層間絕緣膜IL2以與層間絕緣膜相IL1相同之材料構成。又，於第1配線M1之表面形成有具有防止銅之擴散的功能且由例如碳氮化矽構成之位障絕緣膜，在此省略圖示。然後，於層間絕緣膜IL2形成通路孔及配線用溝，使用CMP法埋入以例如銅為主體之導電膜，藉此，形成通路V1及第2配線M2。即，通路V1與第2配線M2以金屬鑲嵌法之一種亦即(Dual Damascene：雙鑲嵌)法形成，而一體化。此外，亦可於銅與層間絕緣膜IL2之間形成防止銅之擴散的障壁金屬膜。此外，通路V1連接於第1配線M1之頂面。
然後，於層間絕緣膜IL2上及第2配線M2上形成層間絕緣膜IL3。之後，使用與形成通路V1及第2配線M2時相同之手法，於層間絕緣膜IL3形成通路V2與第3配線M3。接著，於層間絕緣膜IL3上及第3配線M3上形成層間絕緣膜IL4。之後，使用與形成通路V1及第2配線M2時相同之手法，於層間絕緣膜IL4形成通路V3與第4配線M4。此外，層間絕緣膜IL3及層間絕緣膜IL4之材料與層間絕緣膜IL2相同。
然後，如圖4所示，於層間絕緣膜IL4上將層間絕緣膜IL5形成為覆蓋第4配線M4。層間絕緣膜IF5由無機絕緣膜構成，由例如氧化矽或添加了氟之氧化矽構成。又，於第4配線M4之表面形成有具有防止銅之擴散的功能且由例如碳氮化矽構成之位障絕緣膜，在此省略圖示。之後，使用光刻技術及乾蝕刻法，於層間絕緣膜IL5形成通路孔。然後，藉於通路孔內埋入例如鎢之金屬膜，而形成通路V4。此外，通路V4連接於第4配線M4之頂面。
接著，於層間絕緣膜IL5上形成第5配線M5。首先，使用CVD法或濺鍍法，使障壁金屬膜BM1、導電膜AL及障壁金屬膜BM2依序積層於層間絕緣膜IL5上。之後，藉使用光刻技術及乾蝕刻法進行圖形化，而形成第5配線M5。第5配線M5係於多層配線層之最上層形成有複數之配線，其中之一部分形成為第1焊墊電極PD1。在此，障壁金屬膜BM1及障壁金屬膜BM2分別以氮化鈦或氮化鈦與鈦之積層膜構成。又，導電膜AL由以鋁為主體之導電膜構成。又，障壁金屬膜BM1之膜厚為30~100nm左右，導電膜AL之膜厚為1~4μm左右，障壁金屬膜BM2之膜厚為30~100nm左右。又，亦可不形成障壁金屬膜BM2，在本實施形態中，以形成障壁金屬膜BM2之情形來說明。此外，第5配線M5(第1焊墊電極PD1)連接於通路V4之頂面。
接著，於層間絕緣膜IL5上將絕緣膜IF1形成為覆蓋第5配線M5。絕緣膜IF1係使用CVD法形成之無機絕緣膜，由例如氮化矽或氮氧化矽構成。又，絕緣膜IF1亦可以最先形成氧化矽膜並於該氧化矽膜上形成氮化矽膜之積層膜構成。此外，絕緣膜IF1之膜厚為100~200nm左右。
經過以上之製程，可準備半導體基板SUB、形成於半導體基板SUB上之多層配線層、形成於多層配線層中最上層之配線層的第1焊墊電極PD1、形成為覆蓋第1焊墊電極PD1且由無機材料構成之第1絕緣膜IF1。
接著，如圖5所示，於絕緣膜IF1上形成有機絕緣膜PIQ1。有機絕緣膜PIQ1係使用塗佈法形成之有機樹脂膜，由例如聚醯亞胺構成。此外，有機絕緣膜PIQ1之膜厚係3~7μm左右。之後，對有機絕緣膜PIQ1施行熱處理使其硬化。
然後，於有機絕緣膜PIQ1上形成絕緣膜IF2。絕緣膜IF2係使用低溫之電漿CVD法形成的無機材料之絕緣膜，由例如氧化矽或氮化矽構成。又，絕緣膜IF2係硬度高於有機絕緣膜PIQ1及後述有機絕緣膜PIQ2任一者之材料。又，在此使用之電漿CVD法宜在有機絕緣膜PIQ1之組成不致分解的低溫進行，以在例如350℃以下進行為佳。更佳係此電漿CVD法在200~300℃左右進行。此外，絕緣膜IF2之膜厚為100~500nm左右。
接著，於絕緣膜IF2上形成抗蝕圖形RP1，進行蝕刻處理，藉此，選擇性地去除位於第1焊墊電極PD1上之絕緣膜IF2。
然後，如圖6所示，去除抗蝕圖形RP1、及位於第1焊墊電極PD1上之有機絕緣膜PIQ1。換言之，去除抗蝕圖形RP1及未被絕緣膜IF2覆蓋之區域的有機絕緣膜PIQ1。該等可藉進行乾蝕刻處理同時去除。藉此，第1焊墊電極PD1上之絕緣膜IF1露出。
接著，如圖7所示，去除第1焊墊電極PD1上之絕緣膜IF1的一部分，而使第1焊墊電極PD1露出。藉此，於絕緣膜IF1、有機絕緣膜PIQ1及絕緣膜IF2形成開口部OP1。此製程使用乾蝕刻或濕蝕刻進行，以絕緣膜IF1被去除且絕緣膜IF2保留之條件進行。即，以絕緣膜IF2為遮罩，蝕刻絕緣膜IF1。此時，藉將絕緣膜IF1與絕緣膜IF2以相互不同之材料形成，可使蝕刻具選擇性。舉例而言，當絕緣膜IF1由氮化矽構成時，絕緣膜IF2以氧化矽形成。以磷酸或乾蝕刻去除氮化矽之際，氧化矽不被蝕刻而保留。因而，去除絕緣膜IF1之際，不需追加之遮罩，而可抑制製造製程成本之增加。
此時，亦可去除開口部OP1之底面的障壁金屬膜BM2。如上述，亦可不必去除障壁金屬膜BM2，要使重配線RW與焊墊電極PD1間之電阻更低時，去除障壁金屬膜BM2為有效。在之後的說明中，圖示去除位於開口部OP1之底部的障壁金屬膜BM2之情形。
又，在本實施形態中，僅以1個遮罩蝕刻絕緣膜IF2、有機絕緣膜PIQ1、絕緣膜IF1及障壁金屬膜BM2。通常於形成有機絕緣膜PIQ1前，蝕刻絕緣膜IF1及障壁金屬膜BM2而於第1焊墊電極PD1上形成開口部。之後，於第1焊墊電極PD1上形成有機絕緣膜PIQ1，接著，以另一遮罩於有機絕緣膜PIQ1形成另一開口部。如此，根據本實施形態，於第1焊墊電極PD1上形成開口部OP1之際，可比習知技術減少遮罩片數。
然後，如圖8所示，使用例如CVD法或濺鍍法，於絕緣膜IF2上及開口部OP1內形成障壁金屬膜BM3。此時，施加200~250℃左右之熱處理，由於有機絕緣膜PIQ1之頂面以絕緣膜IF2覆蓋，故無產生障壁金屬膜BM3與有機絕緣膜PIQ1反應而形成的上述反應產物RC之風險。又，由於絕緣膜IF2由無機材料構成，故障壁金屬膜BM3不易與絕緣膜IF2反應，再者，即使反應，亦不致形成金屬碳化物。障壁金屬膜BM3係含有例如鈦、鉭或鉻之導電膜，具有防止導電膜MF1(銅)之擴散的功能。又，障壁金屬膜BM3亦可為上述材料之單層膜，亦可為還形成有例如氮化鈦或氮化鉭之氮化膜的積層膜。此外，障壁金屬膜BM3之膜厚為50~200nm左右。接著，使用濺鍍法，於障壁金屬膜BM3上形成晶種層SD。晶種層SD以與下個製程之導電膜MF1相同的材料構成，由例如銅構成。此外，晶種層SD之膜厚為100~300nm左右。
接著，如圖9所示，於晶種層SD上形成使形成重配線RW之區域開口的抗蝕圖形RP2。
然後，如圖10所示，形成導電膜MF1及導電膜MF2。導電膜MF1以電鍍法形成於晶種層SD上且從抗蝕圖形RP2露出之區域上。之後，藉在有抗蝕圖形RP2之狀態下進行電鍍法，而於導電膜MF1上形成導電膜MF2。導電膜MF1為重配線RW之主要成分，為低電阻化而以薄膜電阻低於導電膜MF2之材料構成，由例如銅構成。又，導電膜MF1之膜厚比導電膜MF2之膜厚厚，為5~10μm左右。
導電膜MF2由不同於導電膜MF1之材料構成，由例如鎳構成。又，導電膜MF2亦可為鎳膜與金膜之積層膜。導電膜MF2係為提高與外部連接用端子TR之密合性而設的膜，即，導電膜MF2與外部連接用端子TR之密合性高於導電膜MF1與外部連接用端子TR之密合性。導電膜MF2之膜厚為1~4μm左右。此外，只要對外部連接用端子TR之密合性足夠，不形成導電膜MF2亦可。
接著，如圖11所示，以灰化處理去除抗蝕圖形RP2。然後，如圖12所示，在從導電膜MF1與導電膜MF2露出之區域(未形成導電膜MF1與導電膜MF2之區域)，以蝕刻依序去除晶種層SD、障壁金屬膜BM3及絕緣膜IF2。藉此，形成重配線RW。
此外，絕緣膜IF2之蝕刻處理宜以濕蝕刻進行。相較於障壁金屬膜BM3與有機絕緣膜PIQ1反應之情形，障壁金屬膜BM3與絕緣膜IF2不易反應。然而，考慮若於絕緣膜IF2之頂面產生了極少數之反應產物時，藉使用濕蝕刻，可將絕緣膜IF2及形成於絕緣膜IF2之頂面的反應產物一起去除。即，可以所謂掀離之手法去除反應產物。從此種觀點，也宜去除從重配線RW露出之區域的絕緣膜IF2。
接著，如圖13所示，於有機絕緣膜PIQ1上將有機絕緣膜PIQ2形成為覆蓋重配線RW。有機絕緣膜PIQ2由與有機絕緣膜PIQ1相同之材料構成。當使用有機絕緣膜PIQ2時，去除從重配線RW露出之區域的絕緣膜IF2特佳。此係當於相鄰之重配線RW間殘留絕緣膜IF2時，會形成有機絕緣膜PIQ2與絕緣膜IF2之界面。在此種界面，由於各介電常數產生差異，故電力線不穩定，在重配線RW之端部易產生電場集中。即，因此界面，易產生在相鄰之重配線RW間產生漏電或在重配線RW間之HAST壽命降低的問題。因而，在本實施形態中，去除了從重配線RW露出之區域的絕緣膜IF2。
又，藉去除從重配線RW露出之區域的絕緣膜IF2，可使有機絕緣膜PIQ1與有機絕緣膜PIQ2直接接觸。藉此，相較於在絕緣膜IF2上形成有機絕緣膜PIQ2之情形，可使有機絕緣膜PIQ2剝離之風險減低。
此外，亦可不形成有機絕緣膜PIQ2。然而，要確保更高之可靠度時，形成有機絕緣膜PIQ2較佳。
接著，如圖2所示，於有機絕緣膜PIQ2選擇性地設開口部OP2。重配線RW之一部分構成用以與外部連接用端子TR連接之區域亦即第2焊墊電極PD2，開口部OP2設成使此第2焊墊電極PD2露出。之後，於第2焊墊電極PD2形成外部連接用端子TR。此外，在本實施形態中，例示了使用凸塊電極作為外部連接用端子TR之情形。藉以上，可形成本實施形態之半導體裝置。
(實施形態2) 圖14係實施形態2之半導體裝置的主要部分截面圖，為圖1之A-A線的主要部分截面圖。在實施形態2中，以有機絕緣膜PIQ3及絕緣膜IF3對應實施形態1之有機絕緣膜PIQ1及絕緣膜IF2的情形來說明。
在前述實施形態1中，在有機絕緣膜PIQ1之頂面，於障壁金屬膜BM3與有機絕緣膜PIQ1之間形成了由無機材料構成之絕緣膜IF2。
在實施形態2，如圖14所示，不僅有機絕緣膜PIQ3之頂面，開口部OP3內之有機絕緣膜PIQ3的側面亦形成有絕緣膜IF3。絕緣膜IF3係無機材料之絕緣膜，由例如氮化矽或氧化矽構成。
藉此，可防止在開口部OP3內，障壁金屬膜BM3與有機絕緣膜PIQ3反應而形成反應產物PC。又，由於絕緣膜IF3由無機材料構成，故即使障壁金屬膜BM3與絕緣膜IF3接合，亦不致生成諸如碳化鈦之金屬碳化物。是故，障壁金屬膜BM3之一部分形成為碳化鈦等高電阻之導電體，而可防止障壁金屬膜BM3之電阻上升。因而，相較於實施形態1，可更降低開口部OP3內之障壁金屬膜BM3的電阻。即，實施形態2之半導體裝置不僅具有與實施形態1相同之效果，亦可更降低重配線RW全體之電阻。
又，藉於開口部OP3內之有機絕緣膜PIQ3的側面形成硬度高於有機絕緣膜PIQ3之無機材料的絕緣膜IF3，相較於實施形態1，可更提高重配線RW之機械強度。
圖15~圖17顯示實施形態2之半導體裝置的製造製程之一部分，顯示實施形態1之圖4以後的製程。
如圖15所示，於絕緣膜IF1上形成有機絕緣膜PIQ3。有機絕緣膜PIQ3係使用塗佈法形成之有機樹脂膜，為添加了感光劑之膜，由例如感光性聚醯亞胺構成。接著，藉將有機絕緣膜PIQ3之一部分感光，進行圖形化，而於有機絕緣膜PIQ3形成開口部OP3。之後，進行熱處理，使有機絕緣膜PIQ3硬化。
接著，於有機絕緣膜PIQ3上及開口部OP3內形成絕緣膜IF3。絕緣膜IF3係使用低溫之電漿CVD法形成之無機材料的絕緣膜，由例如氮化矽或氧化矽構成。又，絕緣膜IF3係硬度高於有機絕緣膜PIQ3及有機絕緣膜PIQ2任一者之材料。又，電漿CVD法之條件與實施形態1之絕緣膜IF2相同。此外，絕緣膜IF3之膜厚為50~300nm左右。
然後，如圖16所示，於絕緣膜IF3上形成諸如使第1焊墊電極PD1上開口之抗蝕圖形RP3。接著，以乾蝕刻或濕蝕刻，依序去除位於從抗蝕圖形RP3露出之區域的絕緣膜IF3及絕緣膜IF1。藉此，開口部OP3到達第1焊墊電極PD1。
在實施形態1中，由於以絕緣膜IF2為遮罩去除了絕緣膜IF1，故絕緣膜IF2與絕緣膜IF1宜以相互不同之材料構成。相對於此，在實施形態2中，絕緣膜IF3與絕緣膜IF1可為相同之材料，亦可為不同之材料。然而，為相同之材料時，不需變更用於乾蝕刻之蝕刻氣體的種類、或用於濕蝕刻之藥液的種類。即，由於可在相同之裝置內，且以相同之條件連續進行蝕刻處理，故可使製造製程簡略化。
又，亦可與實施形態1同樣地，去除位於開口部OP3之底部的障壁金屬膜BM2。此時，與實施形態1同樣地，可使第1焊墊電極PD1與重配線RW之間的電阻小。在以後之說明中，顯示了去除開口部OP3之底面的障壁金屬膜BM2之情形。
接著，如圖17所示，以灰化處理等，去除抗蝕圖形RP3。此後由於與實施形態1之圖8以後的製程相同，故省略說明。
以上，將由本案發明人們所作出之發明依據各實施形態具體地作了說明，本發明不限於該等實施形態，可在不脫離其要旨之範圍進行各種變更。
舉例而言，關於各配線M1~M4，以以銅為主體之金屬鑲嵌構造記載，而將以鋁為主體之導電膜圖形化而形成之配線構造亦可獲得相同之效果。
AL‧‧‧導電膜
A-A‧‧‧線
BM1‧‧‧障壁金屬膜
BM2‧‧‧障壁金屬膜
BM3‧‧‧障壁金屬膜
CP‧‧‧半導體晶片
IF1‧‧‧絕緣膜
IF2‧‧‧絕緣膜
IF3‧‧‧絕緣膜
IL0‧‧‧層間絕緣膜
IL1‧‧‧層間絕緣膜
IL2‧‧‧層間絕緣膜
IL3‧‧‧層間絕緣膜
IL4‧‧‧層間絕緣膜
IL5‧‧‧層間絕緣膜
M1‧‧‧第1配線
M2‧‧‧第2配線
M3‧‧‧第3配線
M4‧‧‧第4配線
M5‧‧‧第5配線
MF1‧‧‧導電膜
MF2‧‧‧導電膜
OP0‧‧‧開口部
OP1‧‧‧開口部
OP2‧‧‧開口部
OP3‧‧‧開口部
PD1‧‧‧第1焊墊電極
PD2‧‧‧第2焊墊電極
PIQ1‧‧‧有機絕緣膜
PIQ2‧‧‧有機絕緣膜
PIQ3‧‧‧有機絕緣膜
PLG‧‧‧插栓
Q1‧‧‧MISFET
Q2‧‧‧MISFET
RC‧‧‧反應產物
RP1‧‧‧抗蝕圖形
RP2‧‧‧抗蝕圖形
RP3‧‧‧抗蝕圖形
RW‧‧‧重配線
SD‧‧‧晶種層
STI‧‧‧元件分離區域
SUB‧‧‧半導體基板
TR‧‧‧外部連接用端子
V1‧‧‧通路
V2‧‧‧通路
V3‧‧‧通路
V4‧‧‧通路
WL‧‧‧阱
圖1係實施形態1之半導體裝置的平面圖。 圖2係實施形態1之半導體裝置的截面圖。 圖3係實施形態1之半導體裝置的截面圖。 圖4係實施形態1之半導體裝置的製造製程進行中之截面圖。 圖5係接續圖4之半導體裝置的製造製程進行中之截面圖。 圖6係接續圖5之半導體裝置的製造製程進行中之截面圖。 圖7係接續圖6之半導體裝置的製造製程進行中之截面圖。 圖8係接續圖7之半導體裝置的製造製程進行中之截面圖。 圖9係接續圖8之半導體裝置的製造製程進行中之截面圖。 圖10係接續圖9之半導體裝置的製造製程進行中之截面圖。 圖11係接續圖10之半導體裝置的製造製程進行中之截面圖。 圖12係接續圖11之半導體裝置的製造製程進行中之截面圖。 圖13係接續圖12之半導體裝置的製造製程進行中之截面圖。 圖14係實施形態2之半導體裝置的截面圖。 圖15係實施形態2之半導體裝置的製造製程進行中之截面圖。 圖16係接續圖15之半導體裝置的製造製程進行中之截面圖。 圖17係接續圖16之半導體裝置的製造製程進行中之截面圖。 圖18係檢討例之半導體裝置的截面圖。 圖19係檢討例之半導體裝置的截面圖。

Claims (20)

  1. 一種半導體裝置，包含： 多層配線層，形成於半導體基板上； 第1焊墊電極，形成於該多層配線層中最上層之配線層； 第1絕緣膜，由無機材料構成且形成為覆蓋該第1焊墊電極； 第1有機絕緣膜，形成於該第1絕緣膜上； 第1開口部，設於該第1有機絕緣膜中及該第1絕緣膜中，且形成為到達該第1焊墊電極； 第1障壁金屬膜，形成於該第1有機絕緣膜上且經由該第1開口部與該第1焊墊電極連接；及 第1導電膜，形成於該第1障壁金屬膜上； 在該第1有機絕緣膜之頂面，於該第1障壁金屬膜與該第1有機絕緣膜之間形成有由無機材料構成之第2絕緣膜。
  2. 如申請專利範圍第1項之半導體裝置，其中， 在該第1開口部內之該第1有機絕緣膜的側面，於該第1障壁金屬膜與該第1有機絕緣膜之間形成有該第2絕緣膜。
  3. 如申請專利範圍第1項之半導體裝置，其中， 該第1焊墊電極具有：第2導電膜、及形成於該第2導電膜上之第2障壁金屬膜； 在該第1開口部之底面，該第2障壁金屬膜被去除，該第1障壁金屬膜與該第2導電膜直接接合。
  4. 如申請專利範圍第1項之半導體裝置，其中， 形成具有該第1障壁金屬膜與該第1導電膜的複數之重配線； 於相鄰之該重配線間的該第1有機絕緣膜之頂面，未形成該第1有機絕緣膜與該第1障壁金屬膜之反應產物。
  5. 如申請專利範圍第4項之半導體裝置，其中， 於該第1有機絕緣膜上以覆蓋該複數之重配線的方式形成第2有機絕緣膜； 在相鄰之該重配線間的區域，該第2絕緣膜被去除，該第1有機絕緣膜與該第2有機絕緣膜直接接合。
  6. 如申請專利範圍第1項之半導體裝置，其中， 該第1有機絕緣膜由聚醯亞胺構成， 該第1障壁金屬膜由含有鈦、鉭或鉻之材料構成， 該第1導電膜由以銅為主成分之材料構成， 該第2絕緣膜由含有氧化矽或氮化矽之材料構成。
  7. 一種半導體裝置之製造方法，包含下列製程： (a)準備半導體基板、形成於該半導體基板上之多層配線層、形成於該多層配線層的最上層之配線層的第1焊墊電極、由無機材料構成且形成為覆蓋該第1焊墊電極之第1絕緣膜； (b)於該第1絕緣膜上形成第1有機絕緣膜； (c)於該第1有機絕緣膜上形成由無機材料構成之第2絕緣膜； (d)於該第2絕緣膜上形成第1抗蝕圖形； (e)藉由以該第1抗蝕圖形為遮罩來進行蝕刻處理，而選擇性地去除位於該第1焊墊電極上之該第2絕緣膜； (f)於該(e)製程後，去除該第1抗蝕圖形及位於該第1焊墊電極上之該第1有機絕緣膜； (g)於該(f)製程之後，藉由在該第2絕緣膜殘留之狀態下，進行蝕刻處理，而選擇性地去除位於該第1焊墊電極上之該第1絕緣膜，形成到達該第1焊墊電極之第1開口部； (h)於該第2絕緣膜上及該第1開口部內，形成與該第1焊墊電極連接之第1障壁金屬膜； (i)於該第1障壁金屬膜上形成第2抗蝕圖形；及 (j)在從該第2抗蝕圖形露出之區域，利用電鍍法於該第1障壁金屬膜上形成第1導電膜。
  8. 如申請專利範圍第7項之半導體裝置之製造方法，其中， 該第2絕緣膜係由不同於該第1絕緣膜之材料構成。
  9. 如申請專利範圍第7項之半導體裝置之製造方法，其中， 該第1焊墊電極包含第2導電膜及形成於該第2導電膜上之第2障壁金屬膜， 在該(g)製程與該(h)製程之間，更包含有在該第1開口部之底面去除該第2障壁金屬膜之製程； 在該(h)製程，該第1障壁金屬膜與該第2導電膜直接接合。
  10. 如申請專利範圍第7項之半導體裝置之製造方法，更包含有下列製程： (k)於該(j)製程後，去除該第2抗蝕圖形； (l)於該(k)製程後，在從該第1導電膜露出之區域，去除該第1障壁金屬膜。
  11. 如申請專利範圍第10項之半導體裝置之製造方法，更包含有下列製程： (m)於該(l)製程後，在從該第1導電膜露出之區域，去除該第2絕緣膜； (n)於該(m)製程後，在該第1有機絕緣膜上將第2有機絕緣膜形成為覆蓋該第1導電膜； 在從該第1導電膜露出之區域，該第1有機絕緣膜與該第2有機絕緣膜直接接合。
  12. 如申請專利範圍第7項之半導體裝置之製造方法，其中， 該第1有機絕緣膜由聚醯亞胺構成， 該第1障壁金屬膜由含有鈦、鉭或鉻之材料構成， 該第1導電膜由以銅為主成分之材料構成， 該第2絕緣膜由含有氧化矽或氮化矽之材料構成。
  13. 如申請專利範圍第7項之半導體裝置之製造方法，其中， 該第2絕緣膜使用350℃以下之電漿CVD法形成。
  14. 一種半導體裝置之製造方法，包含下列製程： (a)準備半導體基板、形成於該半導體基板上之多層配線層、形成於該多層配線層的最上層之配線層的第1焊墊電極、由無機材料構成且形成為覆蓋該第1焊墊電極之第1絕緣膜； (b)於該第1絕緣膜上形成第1有機絕緣膜； (c)於該第1有機絕緣膜形成到達該第1焊墊電極之第1開口部； (d)於該第1有機絕緣膜上及該第1開口部內，形成由無機材料構成之第2絕緣膜； (e)於該第2絕緣膜上形成第1抗蝕圖形； (f)藉由以該第1抗蝕圖形為遮罩來進行蝕刻處理，而選擇性地去除位於該第1焊墊電極上之該第2絕緣膜； (g)於該(f)製程後，選擇性地去除位於該第1焊墊電極上之該第1絕緣膜； (h)於該(g)製程後，在該第2絕緣膜上及該第1開口部內形成與該第1焊墊電極連接之第1障壁金屬膜； (i)於該第1障壁金屬膜上形成第2抗蝕圖形；及 (j)在從該第2抗蝕圖形露出之區域，利用電鍍法於該第1障壁金屬膜上形成第1導電膜。
  15. 如申請專利範圍第14項之半導體裝置之製造方法，其中， 該第2絕緣膜係由與該第1絕緣膜相同之材料構成， 該(f)製程與該(g)製程係以相同之條件連續進行蝕刻處理。
  16. 如申請專利範圍第14項之半導體裝置之製造方法，其中， 該第1焊墊電極包含第2導電膜、及形成於該第2導電膜上之第2障壁金屬膜； 於該(g)製程與該(h)製程之間更包含有在該第1開口部之底面去除該第2障壁金屬膜之製程， 在該(h)製程，該第1障壁金屬膜與該第2導電膜直接接合。
  17. 如申請專利範圍第14項之半導體裝置之製造方法，更包含有下列製程： (k)於該(j)製程後，去除該第2抗蝕圖形； (l)於該(k)製程後，在從該第1導電膜露出之區域，去除該第1障壁金屬膜。
  18. 如申請專利範圍第17項之半導體裝置之製造方法，更包含有下列製程： (m)於該(l)製程後，在從該第1導電膜露出之區域，去除該第1絕緣膜； (n)於該(m)製程後，在該第1有機絕緣膜上將第2有機絕緣膜形成為覆蓋該第1導電膜； 在從該第1導電膜露出之區域，該第1有機絕緣膜與該第2有機絕緣膜直接接合。
  19. 如申請專利範圍第14項之半導體裝置之製造方法，其中， 該第1有機絕緣膜由聚醯亞胺構成， 該第1障壁金屬膜係由含有鈦、鉭或鉻之材料構成， 該第1導電膜係由以銅為主成分之材料構成， 該第2絕緣膜係由含有氧化矽或氮化矽之材料構成。
  20. 如申請專利範圍第14項之半導體裝置之製造方法，其中， 該第2絕緣膜係使用350℃以下之電漿CVD法形成。
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