CN106601715A - 集成电路芯片及其制作方法 - Google Patents

集成电路芯片及其制作方法 Download PDF

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Publication number
CN106601715A
CN106601715A CN201611190566.0A CN201611190566A CN106601715A CN 106601715 A CN106601715 A CN 106601715A CN 201611190566 A CN201611190566 A CN 201611190566A CN 106601715 A CN106601715 A CN 106601715A
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China
Prior art keywords
layer
chip
medium
medium layer
metal level
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CN201611190566.0A
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English (en)
Inventor
肖明
姚泽强
李恒
银发友
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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Application filed by Chengdu Monolithic Power Systems Co Ltd filed Critical Chengdu Monolithic Power Systems Co Ltd
Priority to CN201611190566.0A priority Critical patent/CN106601715A/zh
Publication of CN106601715A publication Critical patent/CN106601715A/zh
Priority to US15/839,818 priority patent/US20180174992A1/en
Pending legal-status Critical Current

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Abstract

公开了一种包括再布线层和焊接凸起结构的集成电路芯片及其制作方法。所述集成电路芯片在再布线层上表面以及侧面覆盖第一介质层，以及在第一介质层上表面的部分区域、侧面以及钝化层的部分区域覆盖第二介质层。通过覆盖第一介质层和第二介质层的方法，阻止了再布线层的离子迁移，并且可以有效的防止不同焊接凸起结构由于变形或者溅落所导致的短路现象。

Description

集成电路芯片及其制作方法
技术领域
本发明涉及集成电路芯片，尤其涉及一种集成电路芯片与外部电路的连接结构和制作方法。
技术背景
随着微电子封装尺寸越来越小，倒装芯片封装逐渐代替传统的导线封装成为主流。
倒装芯片封装利用铜柱加焊料凸块将芯片的电极耦接到封装框架、封装衬底或者电路板。其中芯片可能包括多个电极用于接收或者传输信号。
随着芯片面积越来越小，连接不同电极的相邻金属走线之间的间隙越来越小。此时，芯片若工作于高压高湿的环境中或者芯片自身具有大功率的情况下，很容易在连接不同电极的相邻金属走线之间发生离子迁移现象，从而导致连接不同电极的相邻金属走线之间发生短接，从而导致芯片失效。
因此需要一种技术可以在金属走线相邻间隙越来越小的情况下显著减小或者避免离子迁移现象的发生。
发明内容
本发明一实施例提出了一种集成电路芯片，该集成电路芯片包括：衬底，制作有集成电路和金属层，其中金属层电气耦接至集成电路；钝化层，覆盖在衬底上；通孔，位于钝化层中；再布线层，分布于通孔中和钝化层的部分区域上，通过通孔电气耦接至金属层，再布线层具有上表面和侧面；第一介质层，分布在再布线层的上表面和侧面，第一介质层具有上表面和侧面；以及第二介质层，分布在第一介质层上表面的部分区域、侧面以及钝化层的剩余区域。
本发明一实施例提出了一种集成电路芯片，该集成电路芯片包括：衬底，制作有集成电路和金属层，其中金属层电气耦接至集成电路；钝化层，覆盖在衬底上；第一连接单元和第二连接单元，每个连接单元各包括：通孔，分布在钝化层中；再布线层，分布于通孔中和钝化层的部分区域上，通过通孔电气耦接至金属层，再布线层具有上表面和侧面；以及第一介质层，覆盖在再布线层的上表面和侧面，第一介质层具有上表面和侧面；以及第二介质层，覆盖在第一介质层上表面的部分区域、侧面以及钝化层的剩余区域上。
本发明一实施例提出了一种制造集成电路芯片的方法，该方法包括：在制作有集成电路和金属层的衬底上形成钝化层；在钝化层中形成通孔；在钝化层表面的部分区域以及通孔中形成再布线层；以化学镀的方法在再布线层的上表面和侧面形成第一介质层；以及在第一介质层上以及钝化层表面的剩余区域上形成第二介质层。
根据本申请提供的集成电路芯片及其制作方法，通过给再布线层的上表面和侧面电镀第一介质层，且在第一介质层上表面的部分区域以及钝化层的部分区域覆盖第二介质层，阻止了再布线层离子迁移，并且可以有效的防止不同焊接凸起结构由于变形或者溅落所导致的短路现象。
附图说明
为了更好的理解本发明，将根据以下附图对本发明的实施例进行描述。这些附图仅用于示例。附图通常仅示出实施例中的部分特征，并且附图不一定是按比例绘制的。
图1给出了根据本发明一实施例的集成电路芯片100的局部示意图。
图2给出了根据本发明另一实施例的集成电路芯片200的局部示意图。
图3给出了根据本发明又一实施例的集成电路芯片300的局部示意图。
图4-16给出了制作如图1所示集成电路芯片100的流程剖面图。
不同示意图中的相同的附图标记表示相同或者相似的部分或特征。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是，不必采用这些特定细节来实行本发明。在其它实施例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
在本公开的说明书及权利要求书中，若采用了诸如“左、右、内、外、上、下、之上、之下”等一类词，均只是为了便于描述，而不表示组件/结构的必然或者永久的相对位置。本领域的技术人员应该理解这类词在合适的情况下是可以互换的，例如，以使的本公开的实施例可以在不同于本说明书描绘的方向下仍可以运作。在本公开的上下文中，将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者他们之间可以存在居中层/元件。此外“耦接”一词意味着以直接或者间接的电气的或者非电气的方式连接。“一个/这个/那个”并不用于特指单数，而可能涵盖复数形式。整个说明书的各个地方出现的短语“一个实施例”、“实施例”、“一个示例”、“示例”不一定都指同一个实施例或者示例。本领域普通技术人员应该理解，在本公开说明书的一个或者多个实施例中公开的各个具体特征、结构或者参数、步骤等可以以任何合适的方式组合。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
图1给出了根据本发明一实施例的集成电路芯片100的局部示意图。集成电路芯片100包括制作含有集成电路(图中未示出)的衬底101，所述集成电路包括例如DC-DC转换器电路、微控制器电路等等。衬底101还包括金属层102，其位于衬底101上部且电气耦接至集成电路。本领域技术人员应当理解，在某些实施例中，金属层102可以包括单层金属或者多层金属。在金属层102包括多层金属的实施例中，本发明上下文中描述的金属层102与其它结构的连接是指多层金属的最顶层金属与其它结构的连接。本领域技术人员还应当理解，在某些实施例中，制作于衬底101中的集成电路可能包括连接不同信号的多个电极，在这样的实施例中，金属层102包括不同走线(如图1所示102-1和102-2)，其可将集成电路中的各个电极耦接至集成电路芯片100外部的电路。在一实施例中，衬底101还可以包括多层中间介质层。
在图1的示例性实施例中，集成电路芯片100还包括位于衬底101上的钝化层103。在一实施例中，钝化层103包括二氧化硅、氮化硅或者二氧化硅和氮化硅的混合物。在另一实施例中，钝化层103包括例如氮化硅-二氧化硅堆栈层，其中二氧化硅层分布于衬底101上，而氮化硅层分布于二氧化硅层上。
在图1所示实施例中，集成电路芯片100还包括通孔105，通孔105位于钝化层103中，通孔105将金属层102的一部分暴露以便使金属层102与下文将要描述的再布线层106电气耦接。更进一步的，在某些实施例中，通孔105位于金属层102上方的钝化层103中。在一实施例中，每个通孔105的长×宽可以具有例如3μm×3μm或者6μm×3μm的尺寸。本领域技术人员应当理解，在图1所示实施例中，通孔105为多个，然而，在其它一些实施例中，通孔105也可以仅为一个。在图1的示例性实施例中，集成电路芯片100还包括分布于通孔105中和钝化层103部分区域上的再布线层106，再布线层106通过通孔105和金属层102之间电气耦接起来，再布线层106具有上表面和侧面。在一实施例中，再布线层106包括铜。在一实施例中，再布线层106具有第一厚度T1，所述第一厚度T1根据实际应用设计。在一实施例中，第一厚度T1为1μm至30μm。在另一实施例中，第一厚度T1为5μm至10μm。
在图1所示实施例中，集成电路芯片100还可以包括位于再布线层106和钝化层103之间以及再布线层106与金属层102之间的种子层104，用于改善再布线层106和钝化层103之间以及再布线层106与金属层102之间的粘着力，并且可以防止再布线层106和钝化层103之间以及再布线层106与金属层102之间的金属互相扩散。在一实施例中，种子层104包括铜。
在图1所示实施例中，集成电路芯片100还包括第一介质层107。第一介质层107覆盖于再布线层106的上表面和侧面。第一介质层107具有上表面S1和侧面S2。在一实施例中，第一介质层107包括锡。在另一实施例中，第一介质层107包括金、铅、铂、镍、钯或者钛。在一实施例中，采用化学镀的方法形成第一介质层107，在一实施例中，以再布线层106为基体，采用化学镀的方法将金属锡原子沉积于再布线层106的上表面和侧面形成第一介质层107。在另一实施例中，采用化学镀金、铅、铂、镍、钯或者钛的方法形成第一介质层107。在图1所示实施例中，第一介质层107的厚度根据实际应用设计。在一实施例中，第一介质层107的厚度范围为至在另一实施例中，第一介质层107的厚度范围为至
在图1所示实施例中，集成电路芯片100还包括第二介质层111。第二介质层111分布在第一介质层107上表面S1的部分区域、侧面S2以及钝化层103表面的剩余区域(除去覆盖有再布线106和第一介质层107的区域)。在一实施例中，第二介质层111包括聚酰亚胺树脂(Polyimide)。在另一实施例中，第二介质层111包括聚对苯撑苯并二噁唑(PBO)。在一实施例中，第二介质层111的厚度范围在1μm至20μm之间。在另一实施例中，第二介质层111的厚度范围在5μm至10μm之间。
继续图1的说明，集成电路芯片100进一步包括焊接凸起结构110，其位于第一介质层107上表面S1的剩余区域上并与第一介质层107电气耦接。焊接凸起结构110包括铜柱108和焊料凸起109，铜柱108位于第一介质层107上表面S1的剩余区域并且与第一介质层107电气耦接，焊料凸起109位于铜柱108上并且与铜柱108电气连接。需要说明的是，此处焊料凸起109中所称的“焊料”可示例性地包括锡或者锡合金。
在图1所示实施例中，集成电路芯片100包括制作有集成电路(图1中未示出)和金属层102的衬底101，覆盖在衬底101上的钝化层103，第一连接单元A和第二连接单元B以及第二介质层111。
其中每个连接单元各包括：分布在钝化层103中的通孔105；分布在钝化层103部分区域上和通孔105中的再布线层106以及第一介质层107。其中再布线层106通过通孔105耦接至金属层102，再布线层106具有上表面和侧面。第一介质层107覆盖在再布线层106的上表面和侧面。在一实施例中，第一介质层107具有上表面S1和侧面S2。在一实施例中，第一介质层107包括锡。在另一实施例中，第一介质层107包括金、铅、铂、镍、钯或者钛。在一实施例中，采用化学镀的方法形成第一介质层107。在一实施例中，以再布线层106为基体，采用化学镀的方法将金属锡原子沉积于再布线层106的上表面和侧面形成第一介质层107。在另一实施例中，采用化学镀金、铅、铂、镍、钯或者钛的方法形成第一介质层107。在图1所示实施例中，第一介质层107的厚度根据实际应用设计。在一实施例中，第一介质层107的厚度范围为至在另一实施例中，第一介质层107的厚度范围为至
第二介质层111覆盖在第一介质层107上表面S1的部分区域和侧面S2以及钝化层103的剩余区域(除去覆盖有再布线106和第一介质层107的区域)。在一实施例中，第二介质层111包括聚酰亚胺树脂(Polyimide)。在另一实施例中，第二介质层111包括聚对苯撑苯并二噁唑(PBO)。在一实施例中，第二介质层111的厚度范围在1μm至20μm之间。在另一实施例中，第二介质层111的厚度范围在5μm至10μm之间。
每个连接单元还可以包括分布在第一介质层107上表面S1的剩余区域上的焊接凸起结构110，焊接凸起结构110与第一介质层107电气耦接。焊接凸起结构110包括铜柱108和焊料凸起109，铜柱108位于第一介质层107上表面S1的剩余区域上并且与第一介质层107电气耦接，焊料凸起109位于铜柱108上并且与铜柱108电气连接。需要说明的是，此处焊料凸起109中所称的“焊料”可示例性地包括锡或者锡合金。
继续参考图1，在一些实施例中，再布线层106包括不同的走线(如图1所示106-1和106-2)，其耦接于相应的金属层102中相应的金属层走线(如图1所示102-1和102-2)从而将集成电路中的各个电极耦接至集成电路芯片100外部。在封装过程中，集成电路芯片100被塑封在塑封料中(图1中未示出)。在传统技术中，由于再布线层106的侧面不具有第一介质层107，再布线层106中不同的两个走线106-1和走线106-2容易在电场的作用下发生离子迁移从而导致短路。例如，金属层102包括不同走线(如图1所示102-1和102-2)，走线106-1和106-2为铜走线，铜走线106-1和106-2容易在电场作用下发生铜离子迁移从而导致短路。在本发明实施例中，再布线层106的上表面和侧面覆盖有第一介质层107，第一介质层107阻止了再布线层106的离子迁移。
继续参考图1，在封装过程中，比如说形成焊接凸起结构110或者是对焊接凸起结构110进行热处理的过程，焊接凸起结构110容易发生变形或者溅落从而落入再布线层106中不同走线之间的间隙区域(如图1所示的区域112)，从而导致连接不同电极的再布线层106中的走线106-1和走线106-2之间短接。在本发明中，由于第二介质层111的存在，可以有效的避免这种短路现象。
图2给出了根据本发明又一实施例的集成电路芯片200的局部示意图。图2所示集成电路芯片200与图1所示集成电路芯片100相比，给出了另一种焊接凸起结构110。图2所示的焊接凸起结构110包括焊球，其中焊球可以是锡或者锡合金。
图3给出了根据本发明又一实施例的集成电路芯片300的局部示意图。图3所示金属层102中的金属走线102-1耦接于两个焊接凸起结构110。应当知晓，在其它实施例中，金属走线102-1耦接的焊接凸起结构110可以是多个，此处的两个只是举例说明。
图4-16给出了制作图1所示集成电路芯片100的流程剖面图。为了简明起见，图4-16仅示出了一个连接单元，但是应该理解集成电路芯片100可以包含多个连接单元。
首先参考图4，在衬底101上制作集成电路和金属层102，金属层102耦接至所述集成电路。
在某些实施例中，金属层102可以包括单层金属或者多层金属。在金属层102包括多层金属的实施例中，此处示出的金属层102指的是多层金属的最顶层金属。在一实施例中金属层102包括铝。在图4的示例中，进一步在衬底101和金属层102上制作钝化层103。在一实施例中，钝化层103包括氮化硅-二氧化硅堆栈层，其中氮化硅-二氧化硅堆栈层中的二氧化硅层形成于衬底101上，而氮化硅层形成于二氧化硅层上。
下面参考图5，随后在钝化层103中位于金属层102上方的部分制作通孔105。通孔105的长×宽可以具有例如3μm×3μm或者6μm×3μm的尺寸。进一步地，在钝化层103的表面以及通孔105暴露的金属层102的表面形成种子层104。在一实施例中，采用溅射的方法形成种子层104。
接下来参考图6，在种子层104上制作掩膜PR1。掩膜PR1包括感光性材料，例如光刻胶。掩膜PR1用于界定制作再布线层106的区域。
接下来如图7示例，以掩膜PR1为掩蔽在种子层104上形成再布线层106。在一实施例中，采用电镀铜的方式来形成再布线层106。在一实施例中，再布线层106具有第一厚度T1，所述第一厚度T1根据实际应用设计。在一实施例中，第一厚度T1为1μm至30μm。在另一实施例中，第一厚度T1为5μm至10μm。
接下来如图8示例，去除掩膜PR1。在一实施例中。掩膜PR1可以采用感光性材料(例如光刻胶)的剥除工艺去除。掩膜PR1去除后，去除掉种子层104上没有被再布线层106覆盖的区域。在一实施例中，通过刻蚀的方法来去除种子层104上没有被再布线层106覆盖的区域。
本领域普通技术人员应当理解，在某些实施例中，上述形成种子层104的步骤是可选的，可根据实际需要省略掉形成种子层104的步骤。在这样的实施例中，掩膜PR1和再布线层106可以制作在钝化层103上。当然，在这样的实施例中，不存在如图8所示实施例中的去除种子层104的步骤。
接下来进行到图9，在再布线层106的上表面和侧面采用化学镀的方法形成第一介质层107。第一介质层107具有上表面S1和侧面S2。在一实施例中，第一介质层107包括锡。在另一实施例中，第一介质层107包括金、铅、镍、钯、铂或者钛。第一介质层107的厚度根据实际应用设计。在一实施例中，第一介质层107的厚度范围为至在另一实施例中，第一介质层107的厚度范围为至
接下来参考图10，在第一介质层107上表面S1、侧面S2以及钝化层103的剩余区域(除去覆盖有再布线106和第一介质层107的区域)上形成第二介质层111。在一实施例中，第二介质层111包括聚酰亚胺树脂(Polyimide)。在另一实施例中，第二介质层111包括聚对苯撑苯并二噁唑(PBO)。在一实施例中，采用涂抹聚酰亚胺树脂(Polyimide)或聚对苯撑苯并二噁唑(PBO)形成第二介质层111。
接下来参考图11，在第二介质层111上制作掩膜PR2，掩膜PR2可以包括感光性材料，例如光刻胶。掩膜PR2用于界定制作焊接凸起结构110的区域。在图11的示例中，掩膜PR2将第二介质层111上即将用于形成铜柱108的部分区域111S暴露，并将第二介质层111的其余部分掩盖，然后通过曝光以及显影将第二介质层111的部分区域111S去除以暴露出如图12所示的第一介质层107的部分区域107S。
接下来如图13所示，继续以掩膜PR2为掩蔽在第一介质层107的部分区域107S上制作焊接凸起结构110。在一实施例中，采用电镀的方式制作焊接凸起结构110。在一实施例中，制作焊接凸起结构110包括如图13所示电镀铜形成铜柱108和如图14所示在铜柱108上再次电镀制作锡形成焊料层209。其中铜柱108具有第二高度T2，所述第二高度T2根据实际应用设计，在一实施例中，第二高度T2为35μm至65μm。在另一实施例中，第二高度T2为55μm至65μm。
接下来参考图15，将掩膜PR2去除。然后将图15所示的结构进行热处理。在一实施例中，可以采用回流工艺。回流工艺的步骤包括把图15所示的结构置于回流炉中或者其它热炉中使其历经热能梯度。在回流工艺步骤中提供的热能使得焊料层209形成焊料凸起109，从而得到如图16所示的结构示意图。其中焊料凸起109具有第三高度T3，所述第三高度T3根据实际应用设计，在一实施例中，第三高度T3为10μm至50μm。在另一实施例中，第三高度T3为25μm至50μm。
上述的一些特定实施例仅仅以示例性的方式对本发明进行说明。这些实施例不是完全详尽的，并不用于限定本发明的范围。对于公开的实施例进行变化和修改都是可能的，其它可行的选择性实施例和对实施例中元件的等同变化可以被本技术领域的普通技术人员所了解。本发明所公开的实施例的其它变化和修改并不超出本发明的精神和权利要求限定的保护范围。

Claims (13)

1.一种集成电路芯片，包括：
衬底，制作有集成电路和金属层，其中金属层电气耦接至集成电路；
钝化层，覆盖在衬底上；
通孔，位于钝化层中；
再布线层，分布于通孔中和钝化层的部分区域上，通过通孔电气耦接至金属层，再布线层具有上表面和侧面；
第一介质层，分布在再布线层的上表面和侧面，第一介质层具有上表面和侧面；以及
第二介质层，分布在第一介质层上表面的部分区域、侧面以及钝化层的剩余区域。
2.如权利要求1所述的集成电路芯片，还包括焊接凸起结构，分布在第一介质层上表面的剩余区域。
3.如权利要求1所述的集成电路芯片，其中所述第一介质层包括锡、金、铅、铂、镍、钯或者钛。
4.如权利要求1所述的集成电路芯片，其中所述第二介质层包括聚酰亚胺树脂或者聚对苯撑苯并二噁唑。
5.一种集成电路芯片，包括：
衬底，制作有集成电路和金属层，其中金属层电气耦接至集成电路；
钝化层，覆盖在衬底上；
第一连接单元和第二连接单元，每个连接单元各包括：
通孔，分布在钝化层中；
再布线层，分布于通孔中和钝化层的部分区域上，通过通孔电气耦接至金属层，再布线层具有上表面和侧面；以及
第一介质层，覆盖在再布线层的上表面和侧面，第一介质层具有上表面和侧面，以及
第二介质层，覆盖在第一介质层上表面的部分区域、侧面以及钝化层的剩余区域上。
6.如权利要求5所述的集成电路芯片，其中每个连接单元还包括焊接凸起结构，分布在第一介质层上表面的剩余区域上。
7.如权利要求5所述的集成电路芯片，其中所述第一介质层包括锡、金、铅、铂、镍、钯或者钛。
8.如权利要求5所述的集成电路芯片，其中所述第二介质层包括聚酰亚胺树脂或者聚对苯撑苯并二噁唑。
9.一种制作集成电路芯片的方法，包括：
在制作有集成电路和金属层的衬底上形成钝化层；
在钝化层中形成通孔；
在钝化层表面的部分区域以及通孔中形成再布线层；
以化学镀的方法在再布线层的上表面和侧面形成第一介质层；以及
在第一介质层上以及钝化层表面的剩余区域上形成第二介质层。
10.如权利要求9所述的制造集成电路芯片的方法，还包括对第二介质层进行显影以及曝光形成窗口以漏出第一介质层的部分区域，以及在第一介质层的部分区域上形成焊接凸起结构。
11.如权利要求9所述的制造集成电路芯片的方法，其中所述第一介质层包括锡、金、铅、铂、镍、钯或者钛。
12.如权利要求9所述的制造集成电路芯片的方法，其中所述第二介质层包括聚酰亚胺树脂或者聚对苯撑苯并二噁唑。
13.如权利要求9所述的制造集成电路芯片的方法，其中通过涂抹的方法形成第二介质层。
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