TWI402939B - 包含一矽貫通電極之積體電路結構及形成該積體電路結構之方法 - Google Patents

包含一矽貫通電極之積體電路結構及形成該積體電路結構之方法 Download PDF

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TWI402939B
TWI402939B TW097109167A TW97109167A TWI402939B TW I402939 B TWI402939 B TW I402939B TW 097109167 A TW097109167 A TW 097109167A TW 97109167 A TW97109167 A TW 97109167A TW I402939 B TWI402939 B TW I402939B
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electrode
layer
forming
wafer
transfer pad
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TW200919632A (en
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Chihhua Chen
Chen Shien Chen
Chencheng Kuo
Kuoching Hsu
Kaiming Ching
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Taiwan Semiconductor Mfg
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Description

包含一矽貫通電極之積體電路結構及形成該積體電路結構之方法
本發明是有關於一種積體電路結構，且特別是有關於一種包含一矽貫通電極之積體電路及形成該積體電路之方法。
自從積體電路發明後，半導體工業即開始因為各種電子元件(如電晶體、二極體、電阻、電容等等)積體密度的提升而持續地快速成長。積體密度的提升係由於最小線寬在技術演進下持續地下降，使更多的元件可以被整合入一個晶片區之中。
上述的積體密度之改進，著重於二維平面上，因為電子原件係排列於半導體晶圓的表面上。雖然在二維平面的積體電路上具有相當大的進步，但是二維平面密度將會受到物理上的限制。其中一項限制是這些元件所能達到的最小尺寸。其次，當更多的元件被放入一個晶片中，將須要更複雜的設計以完成電路。
尚有一個限制是因為電子元件的數目增加後，電子元件彼此間的連接線之數目及長度都因而增加許多。電阻電容延遲效應及功率消耗都會因此跟著上升。
解決上述問題的方法，目前以三維積體電路及堆疊晶粒(Stacked die)最為常見。矽貫通電極(Through－silicon via；TSV)常見於三維積體電路及堆疊晶粒中，用以連接各晶片。矽貫通電極可將晶片上之積體電路連接至晶片之背側，更可用以提供一接地路徑以將積體電路由晶片之背側接地。其中晶片之背側多以一接地之鋁薄膜覆蓋。
第1圖繪示了一傳統矽貫通電極之形成過程之一步驟中，積體電路結構之側視圖，包含一矽基板2，一層間介電層4及一保護層6。電極轉接墊8形成於保護層6下且由保護層6之一開口曝露於外。矽貫通電極10形成並穿置於電極轉接墊8之一開口，延伸至層間介電層4及矽基板2中。
第1圖所示之結構將受到晶片面積的限制，因為矽貫通電極為電極轉接墊8所環繞，電極轉接墊8佔據了相大大的面積，且對應至電極轉接墊8下方的晶片區無法用以形成半導體元件。更進一步地，要形成矽貫通電極10，必須包含形成並圖案化複數個絕緣薄膜的步驟，造成了生產成本較高的結果。
因此，能提供一新的矽貫通電極積體電路結構及形成方法，乃為此一業界亟待解決的問題。
因此本發明的目的就是在提供一種積體電路結構，包含：一基板；一矽貫通電極，係延伸入基板中；一矽貫通電極轉接墊，係與矽貫通電極間隔一距離設置；以及一金屬線，電性連接於矽貫通電極及一矽貫通電極轉接墊。
本發明的另一目的是在提供一種積體電路結構，包含：一半導體基板；複數個介電層，係位於半導體基板上；一矽貫通電極，係穿越介電層及半導體基板，其中矽貫通電極延伸至半導體基板之一背側；一矽貫通電極轉接墊，係位於介電層上，其中矽貫通電極係僅於矽貫通電極轉接墊之一側水平設置；以及一金屬線，係位於矽貫通電極及矽貫通電極轉接墊上，且金屬線與矽貫通電極及矽貫通電極轉接墊電性連接。
本發明的又一目的是在提供一種形成一積體電路結構之方法，包含下列步驟：提供一晶圓，晶圓包含：一半導體基板以及一位於半導體基板上之矽貫通電極轉接墊；形成一矽貫通電極開口，自該晶圓之一上表面延伸至該半導體基板，其中該矽貫通電極開口係與該矽貫通電極轉接墊間隔一距離設置；形成一矽貫通電極於該矽貫通電極開口；形成一金屬線電性連接該矽貫通電極及該矽貫通電極轉接墊。
本發明的又一目的是在提供一種形成一積體電路結構之方法，包含下列步驟：提供一晶圓，晶圓包含：一半導體基板以及一位於半導體基板上之矽貫通電極轉接墊；形成一擴散障蔽層於該晶圓上，其中該擴散障蔽層延伸至一矽貫通電極開口；形成一銅晶種層(Copper seed layer)於該擴散障蔽層上；形成並圖案化一光罩層，以曝露該矽貫通電極轉接墊、該矽貫通電極開口及一位於該矽貫通電極開口及該矽貫通電極轉接墊之一區域；選擇性地形成一銅層於該銅晶種層上，其中該同層填滿該矽貫通電極開口以形成一矽貫通電極，且該銅層延伸至該矽貫通電極轉接墊；移除該光罩層以曝露部份該銅晶種層及該擴散障蔽層；蝕刻該銅晶種層之該曝露部份；以及蝕刻該擴散障蔽層之該曝露部份。
由上述本發明較佳實施例可知，應用本發明之積體電路結構及方法，可以減少製程步驟，並降低生產成本及增加晶片面積使用效率之優點。
雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
請參照第2圖，其繪示依照本發明一較佳實施例的一種側視圖，係為本發明中，形成包含一矽貫通電極之一積體電路之結構，其過程之一步驟中，積體電路結構之側視圖。提供一包含一基板20之晶圓18。基板20晶圓通常為一半導體基板，如一矽基板，或包含其他半導體材質如第三、第四或第五族元素。半導體元件如金屬氧化半導體(未繪示)可以形成於基板20之一上表面。複數個介電層22形成於基板20上，係包含複數個金屬線及電極。介電層22可包含層間介電層或層間金屬介電層，也可包含低介電常數之介電物質。矽貫通電極轉接墊24形成於介電層22上，可連接至基板20之上表面之半導體元件。第2圖亦繪示了連接墊26，係用於將晶片上的積體電路連接至外部元件。矽貫通電極轉接墊24及連接墊26係形成於一最上層之介電層28中。矽貫通電極轉接墊24及連接墊26之材質可為鋁、鎢、銀、銅其中之一或其組合。保護層30形成於矽貫通電極轉接墊24及連接墊26上，且矽貫通電極轉接墊24及連接墊26藉由複數個保護層30上的開口曝露於外。保護層30之材質係為氧化矽或氮化矽。
第3圖繪示了光阻32之形成及圖案化。首先實施蝕刻以於保護層30、介電層28及介電層22形成一開口34。基板20接著沿開口34被蝕刻，其蝕刻方式以乾性蝕刻為佳。形成開口34後，光阻32即被移除，而形成如第4圖所示之結構。
第5圖和第6圖繪示了絕緣層38的形成。請參照第5圖，絕緣層38形成並覆蓋第4圖之結構上。絕緣層38可為如氮化矽、碳化矽、氧化矽或其他性質相似之物質。光阻40接著被形成及圖案化。圖案化後，光阻40於矽貫通電極轉接墊24及連接墊26上方之部份被移除，所曝露出的絕緣層38接著被蝕刻以曝露矽貫通電極轉接墊24及連接墊26。接著光阻40被移除而形成如第6圖所示之結構。
參照第7圖，擴散障蔽層42，有時被稱作膠層，形成並覆蓋於第6圖之結構上。絕緣層38可為如鈦、氮化鈦、鉭、氮化鉭或其他性質相似之物質。擴散障蔽層42可由物理氣相沉積或濺鍍之方式形成。
一薄晶種層44，有時被稱作覆晶球下金屬層(Under－bump metallurgy；UBM)，接著被形成於擴散障蔽層42上。薄晶種層44可為如銅、銅合金、銀、金、鋁其中之一或其組合形成。於本實施例中，薄晶種層44係由濺鍍而形成，於其他實施例中亦可由物理氣相沉積或無電鍍(Electroless plating)之方法形成。薄晶種層44之厚度以2um為佳。
第8圖繪示了光罩46的形成。光罩46於本實施例中為一乾膜光罩。於其他實施例亦可由其他物質形成。於本實施例中乾膜光罩46包含一有機物質如Ajinimoto buildup film(ABF)。於其他實施例亦可包含預浸料(Prepreg)及背膠銅箔基板(Resin－coated copper；RCC)。接著施加熱及壓力於乾膜光罩46上，以軟化乾膜光罩46形成一平坦之上表面。乾膜光罩46之厚度以5um以上為佳，尤以10um至100um的範圍內為最佳。熟知此技術者當可輕易得知上述的尺寸僅為一範例，係可隨積體電路尺寸之縮減而縮減。
乾膜光罩46接著被圖案化。在一實施例中，所要形成之矽貫通電極須透過矽貫通電極轉接墊24與基板20之上表面之積體電路相電性連接。因此開口48形成於乾膜光罩46，曝露矽貫通電極轉接墊24、開口34及一位於該矽貫通電極轉接墊24及開口34間之一區域上之部份擴散障蔽層42及薄晶種層44。
第9圖中，開口34選擇性地被填充一金屬物質以形成矽貫通電極50於開口34中。金屬物質包含銅或銅合金，然而於其他實施例中如鋁、銀、金其中之一或其組合亦可用以形成金屬物質。此填充之過程可由濺鍍、電鍍、無電鍍或化學氣相沉積法形成。
開口34被填充後，開口48亦連續地被同樣的金屬物質所填充，形成金屬線52，或被稱為後保護層連接線52(Post－passivation interconnect；PPI)，係用以電性連接矽貫通電極轉接墊24及矽貫通電極50。金屬線52之較佳厚度為小於30um，尤其於2um至25um係為最佳之範圍。
於第10圖中，乾膜光罩46被一鹼性容液移除，因此，位於乾膜光罩46下之部份薄晶種層44被曝露。被曝露之部份薄晶種層44接著被移除。一轉接墊開口步驟被執行，擴散障蔽層42之曝露部份被移除。被用以蝕刻擴散障蔽層42之物質以不侵蝕金屬線52為佳。接著連接墊26亦被曝露。於一實施例中，被用以蝕刻擴散障蔽層42之物質係為以氟為主要元素之蝕刻氣體，且蝕刻過程係為非等向性。在以下的圖示中，薄晶種層44將不再繪示，因為薄晶種層44與矽貫通電極50及金屬線52係由相似的物質所形成，因此與矽貫通電極50及金屬線52係已合為一體，故不再繪示。
第11圖繪示保護層56之形成。保護層56接著被圖案化以曝露連接墊26。保護層56包含一有機且不導電之物質。金屬線52及矽貫通電極50係為保護層56所覆蓋。
玻璃晶圓58接著藉由一高分子膠60黏合至晶圓18之上表面。接著實施一研磨於基板20之一背側直到矽貫通電極50曝露。玻璃晶圓58接著被移除以使一紫外光照射高分子膠60，俾使高分子膠60失去其黏性，而成為如第12圖之結構。
第13圖中，導電層64形成於晶圓之背側，導電層64於本實施中係為一鋁金屬層。接著一鎳銀合金66以無電鍍方式形成於導電層64上。鎳銀合金66及導電層64係電性連接於矽貫通電極50。因此，矽貫通電極50可為晶片上之積體電路之一接地路徑。於其他實施例中，係不形成導電層，而形成一連接墊於曝露之矽貫通電極50上，連接墊可電性連接於另一半導體晶片或一封裝基板。在又一實施例中，係不形成連接墊，矽貫通電極50以一銅柱之形式連接至另一半導體晶片或一封裝基板。
本發明之實施例與傳統之矽貫通電極相較下，使用了較小的晶片面積，因為矽貫通電極轉接墊不須再環繞矽貫通電極。更進一步地，積體電路之製程亦隨之簡化。
雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．矽貫通電極
18．．．晶圓
2．．．矽基板
20．．．基板
22．．．介電層
24．．．矽貫通電極轉接墊
26．．．連接墊
28．．．最上層介電層
30．．．保護層
32．．．光阻
34．．．開口
38．．．絕緣層
4．．．層間介電層
40．．．光阻
42．．．擴散障蔽層
44．．．薄晶種層
46．．．乾膜光罩
48．．．開口
50．．．矽貫通電極
52．．．金屬線
56．．．保護層
58．．．玻璃晶圓
6．．．保護層
60．．．高分子膠
64．．．導電層
66．．．鎳銀合金
8．．．電極轉接墊
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之詳細說明如下：第1圖係為先前技術中，一矽貫通電極結構之示意圖，其中矽貫通電極形成於一電極轉接墊之開口中；以及第2圖至第13圖係為本發明一實施例之各製造階段之側剖面圖，其中矽貫通電極係與矽貫通電極轉接墊間隔一距離設置。
18．．．晶圓
2．．．矽基板
20．．．基板
22．．．介電層
24．．．矽貫通電極轉接墊
26．．．連接墊
28．．．最上層介電層
30．．．保護層
38．．．絕緣層
42．．．擴散障蔽層
50．．．矽貫通電極
52．．．金屬線
56．．．防焊層
64．．．導電層
66．．．鎳銀合金

Claims (10)

  1. 一種形成一積體電路結構之方法，包含下列步驟：提供一晶圓，該晶圓包含：一半導體基板；以及一矽貫通電極轉接墊，係位於該半導體基板上；形成一矽貫通電極開口，自該晶圓之一上表面延伸至該半導體基板，其中該矽貫通電極開口係與該矽貫通電極轉接墊間隔一距離設置，俾不環繞該矽貫通電極；形成一光罩覆蓋該晶圓；圖案化該光罩以曝露該矽貫通電極開口、該矽貫通電極轉接墊及一位於該矽貫通電極開口及該矽貫通電極轉接墊之一區域；選擇性地填充一導電物質於該矽貫通電極開口以形成一矽貫通電極，直到該導電物質高於該矽貫通電極與該矽貫通電極轉接墊電性連接之一上表面；移除該光罩；以及形成一金屬線電性連接該矽貫通電極及該矽貫通電極轉接墊。
  2. 如申請專利範圍第1項所述之方法，於填充該導電物質前更包含：形成一絕緣物質；圖案化該絕緣物質以曝露該矽貫通電極轉接墊。
  3. 如申請專利範圍第1項所述之方法，更包含一步驟：形成一防焊層，覆蓋該金屬線。
  4. 如申請專利範圍第3項所述之方法，其中該晶圓更包含一連接墊，係位於與該矽貫通電極轉接墊所在相同之該介電層上，其中形成該防焊層更包含一步驟：圖案化該防焊層以曝露出該連接墊。
  5. 如申請專利範圍第1項所述之方法，更包含一步驟：研磨該晶圓之一背表面以曝露該矽貫通電極。
  6. 如申請專利範圍第5項所述之方法，於研磨該晶圓之該背表面之步驟後，更包含一步驟：形成一導電層於該晶圓之該背表面，其中該導電層係電性連接於該矽貫通電極。
  7. 一種形成一積體電路結構之方法，包含下列步驟：提供一晶圓，該晶圓包含：一半導體基板；以及一矽貫通電極轉接墊，係位於該半導體基板上；形成一擴散障蔽層於該晶圓上，其中該擴散障蔽層延伸至一矽貫通電極開口，其中該矽貫通電極開口不為該矽貫通電極所環繞； 形成一銅晶種層(Copper seed layer)於該擴散障蔽層上；形成並圖案化一光罩層，以曝露該矽貫通電極轉接墊、該矽貫通電極開口及一位於該矽貫通電極開口及該矽貫通電極轉接墊之一區域；選擇性地形成一銅層於該銅晶種層上，其中該銅層填滿該矽貫通電極開口以形成一矽貫通電極，且該銅層延伸至該矽貫通電極轉接墊；移除該光罩層以曝露部份該銅晶種層及該擴散障蔽層；蝕刻該銅晶種層之該曝露部份；以及蝕刻該擴散障蔽層之該曝露部份。
  8. 如申請專利範圍第7項所述之方法，更包含：於該晶圓上之一上表面塗佈一高分子膠；藉由該高分子膠黏著一玻璃晶圓於該晶圓上；以及研磨該晶圓之一背側以曝露該矽貫通電極。
  9. 如申請專利範圍第7項所述之方法，其中該銅晶種層係藉由濺鍍方式形成且該銅層係由電鍍形成。
  10. 如申請專利範圍第7項所述之方法，於形成該擴散障蔽層前更包含一步驟：形成一絕緣層及圖案化該絕緣層以曝露該矽貫通電極轉接墊。
TW097109167A 2007-10-17 2008-03-14 包含一矽貫通電極之積體電路結構及形成該積體電路結構之方法 TWI402939B (zh)

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