TW201532221A - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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Publication number
TW201532221A
TW201532221A TW103145299A TW103145299A TW201532221A TW 201532221 A TW201532221 A TW 201532221A TW 103145299 A TW103145299 A TW 103145299A TW 103145299 A TW103145299 A TW 103145299A TW 201532221 A TW201532221 A TW 201532221A
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Taiwan
Prior art keywords
substrate
component
surface mount
mount component
solder resist
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TW103145299A
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English (en)
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TWI550795B (zh
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Hsien-Wei Chen
Ying-Ju Chen
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201532221A publication Critical patent/TW201532221A/zh
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Publication of TWI550795B publication Critical patent/TWI550795B/zh

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Abstract

本揭露之實施例包含元件及其製造方法。一實施例為一種元件，包含抗焊塗層位於基板的第一側上方、晶粒的主動面藉由第一連接件接合於基板的第一側、以及表面安裝元件藉由第二組連接件安裝在晶粒上，表面安裝元件介於晶粒與基板之第一側之間，表面安裝元件與抗焊塗層分隔。

Description

包含嵌入式表面安裝元件的半導體元件及 其製造方法 【相關申請案之交互參照】
本申請案與2014年2月13日申請之共同擁有的審查中專利申請案第14/180,084號，名稱為「包含嵌入式表面安裝元件之半導體封裝及其製造方法」有關，在此一併列入參考。
本發明是有關於一種半導體元件製作技術，且特別是有關於一種半導體元件及其製造方法。
半導體元件係使用在各種的電子應用上，例如個人電腦、行動電話、數位相機以及其他電子裝置。半導體元件的製作通常是在半導體基板上依序沉積絕緣或介電層、導電層以及半導體層材料，並利用微影來圖案化各個材料層，以形成電路構件和元件在半導體基板上。
由於各種電子元件(例如，電晶體、二極體、電阻器、電容器等)之積集密度的增加，半導體工業已經歷快速的 成長。積集密度之增進大部分的原因是半導體製程節點之縮小化(例如，製程節點朝次20奈米節點縮小)。隨著近來對於微型化、更高速度、更高頻寬、及更低能量損耗以及延遲之需求的成長，而對於更小及更具創造性之半導體晶粒封裝技術的需求成長。
一實施例為一種元件，包含抗焊塗層位於基板的第一側上方、晶粒的主動面藉由第一連接件接合於基板的第一側、以及表面安裝元件藉由第二組連接件安裝在晶粒上，表面安裝元件介於晶粒與基板之第一側之間，表面安裝元件與該抗焊塗層分隔。
另一實施例為一種元件，包含抗焊塗層位於印刷電路板的第一側、第一導電連接件耦合於印刷電路板的第一側、以及半導體晶粒藉由第一導電連接件接合於印刷電路板。此元件更包含表面安裝元件耦合於半導體晶粒，表面安裝元件位於半導體晶粒與印刷電路板之間，印刷電路板之第一側的第一部分係暴露在表面安裝元件的上方。
又一實施例為一種製造元件之方法，此方法包含形成抗焊塗層在基板之第一側上方，基板之第一側的第一部分係暴露於抗焊塗層之複數個部分之間；安裝表面安裝元件至半導體晶粒之主動面；以及利用第一導電連接件，將半導體晶粒之主動面安裝至基板的第一側，基板之第一側的第一部分係位於表面安裝元件之上方。
100‧‧‧半導體元件
102‧‧‧基板
104‧‧‧金屬化層
106‧‧‧介電窗
110‧‧‧抗焊塗層
120‧‧‧表面安裝元件
122‧‧‧導電連接件
124‧‧‧元件墊/凸塊下金屬化層
130‧‧‧連接件
132‧‧‧接合墊/凸塊下金屬化層
134‧‧‧接合墊/凸塊下金屬化層
150‧‧‧半導體晶粒/晶片/晶粒
200‧‧‧半導體元件
300‧‧‧半導體元件
302‧‧‧凹陷
400‧‧‧半導體元件
402‧‧‧開口
D1‧‧‧距離
D3‧‧‧距離
D4‧‧‧距離
H1‧‧‧高度
H2‧‧‧高度
H3‧‧‧間距高度
L1‧‧‧長度
L2‧‧‧長度
L3‧‧‧長度
L4‧‧‧長度
從以下結合所附圖式所做的詳細描述，可對本揭露之態樣有更佳的了解。需注意的是，根據業界的標準實務，各特徵並未依比例繪示。事實上，為了使討論更為清楚，各特徵的尺寸可任意地增加或減少。
圖1A及圖1B係分別繪示依照本發明之一些實施方式之一半導體元件之剖面視圖以及平面視圖。
圖2A及圖2B係分別繪示依照本發明之一些實施方式之一半導體元件之剖面視圖以及平面視圖。
圖3係繪示依照本發明之一些實施方式之一半導體元件之剖面視圖。
圖4A及圖4B係分別繪示依照本發明之一些實施方式之一半導體元件之剖面視圖以及平面視圖。
以下的揭露提供了許多不同的實施例或例子，以實施發明之不同特徵。以下所描述之構件與安排的特定例子係用以簡化本揭露。當然這些僅為例子，並非用以作為限制。舉例而言，在描述中，第一特徵形成於第二特徵上方或上，可能包含第一特徵與第二特徵以直接接觸的方式形成的實施例，而也可能包含額外特徵可能形成在第一特徵與第二特徵之間的實施例，如此第一特徵與第二特徵可能不會直接接觸。此外， 本揭露可能會在各例子中重複參考數字及/或文字。這樣的重複係基於簡單與清楚之目的，以其本身而言並非用以指定所討論之各實施例及/或配置之間的關係。
另外，在此可能會使用空間相對用語，例如「向下(beneath)」、「下方(below)」、「較低(lower)」、「上方(above)」、「較高(upper)」等等，以方便描述來說明如圖式所繪示之一元件或一特徵與另一(另一些)元件或特徵之關係。除了在圖中所繪示之方向外，這些空間相對用詞意欲含括元件在使用或操作中的不同方位。設備可能以不同方式定位(旋轉90度或在其他方位上)，因此可利用同樣的方式來解釋在此所使用之空間相對描述符號。
將以有關特定內容，也就是包含表面安裝元件之半導體元件的製造與使用來描述實施方式。然而，其他實施方式亦可應用於其他電性連接之構件，包含(但不限於)層疊封裝(PoP)組件、晶粒接合(die-to-die)組件、晶圓接合(wafer-to-wafer)組件、晶粒與基板接合(die-to-substrate)組件、裝配中封裝、處理中基板、中介層、基板或其類似物、或安裝輸入構件、板材、晶粒或其他構件、或用於任何類型的積體電路或電子構件之連接封裝或安裝的組合。
圖1A及圖1B係分別繪示依照本發明之一些實施方式之一半導體元件100之剖面視圖以及平面視圖。圖1A繪示半導體元件100包含具有金屬化層104以及介電窗106的基板102、抗焊塗層110、半導體晶粒150、耦合基板102與半導體晶粒150的導電連接件130、以及位於半導體晶粒150與基板 102之間並耦合於半導體晶粒150的表面安裝元件120。如圖1A所繪示，移除半導體晶粒150上方的抗焊塗層110的一部分，以提供在半導體晶粒150與基板102之間的表面安裝元件120足夠的空間。
基板102可由半導體材料，例如矽、鍺、鑽石或其類似物所形成。替代地，亦可使用複合材料例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷鎵、磷化銦鎵、前述之組合或其類似物。此外，基板102可為絕緣底矽(silicon-on-insulator，SOI)基板。一般而言，絕緣底矽基板包含一層半導體材料，例如磊晶矽、鍺、矽鍺、絕緣底矽、絕緣底矽鍺(silicon germanium on insulator，SGOI)或前述之組合。在一替代實施例中，基板102係建立於絕緣芯板上，例如玻璃纖維強化樹脂芯板。一個芯板材料的例子為玻璃纖維樹脂，例如FR4。芯板材料的替代物包含雙馬來醯亞胺-三氮雜苯(bismaleimide-triazine，BT)樹脂，或者替代地，其他印刷電路板材料或薄膜。基板102亦可使用增層膜，例如Ajinomoto公司所供應的增層膜材料(Ajinomoto build-up film，ABF)或其他層壓板。
基板102可包含主動及被動元件(未繪示於圖1A中)。在此技術領域中具有通常知識者將了解，可使用各種元件，像是電晶體、電容器、電阻器、前述之組合、及其類似物，來產生半導體元件100在設計上的結構及功能需求。這些元件可利用任何合適的方式形成。
基板102亦可包含金屬化層104。這些金屬化層104可形成在主動與被動元件上，且設計來連接各元件，以形成功能電路系統。金屬化層104可由介電(例如低介電常數介電材料)與導電材料(例如銅)之交錯層，且以介電窗106連接導電材料層所形成，且金屬化層104可利用任何適合的製程(例如沉積、鑲嵌、雙鑲嵌或其類似方法)製作。
基板102包含至少一個接合墊134。接合墊134可形成於基板102的第一側中。在一些實施例中，利用在基板102或基板102上的鈍化層(圖未示)中形成凹陷的方式形成接合墊134。這些凹陷的形成可讓接合墊134嵌入於基板102或鈍化層中。在其他實施例中，可以省略這些凹陷，而接合墊134可形成於基板102的第一側上。接合墊134將後續接合的半導體晶粒150電性耦接至金屬化層104、基板102的主動與被動元件(圖未示)及/或基板102之第二側上的連接件(圖未示)。在一些實施例中，接合墊134包含例如使用物理氣相沉積(physical vapor deposition，PVD)、化學氣相沉積(chemical vapor deposition，CVD)、原子層沉積(atomic layer deposition，ALD)、其類似方法或前述之組合而沉積在基板102上的薄晶種層(圖未示)。晶種層可由銅、鈦、鎳、金、其類似物或前述之組合所製成。接合墊134的導電材料可沉積在薄晶種層上。導電材料可透過電化學電鍍、化學氣相沉積、原子層沉積、物理氣相沉積、其類似方法或前述方法之組合來製作。在一實施例中，接合墊134的導電材料為銅、鎢、鋁、銀、金、其類似物或前述之組合。
在一實施例中，接合墊134為凸塊下金屬化層(under bump metallization，UBM)134，且包含三層導電材料，例如一層鈦、一層銅以及一層鎳。然而，在此技術領域中具有通常知識者將了解，有許多適合的材料及層的配置，例如鉻/鉻-銅合金/銅/金的配置、鈦/鈦鎢/銅的配置、或銅/鎳/金的配置，都適合來形成凸塊下金屬化層134。意欲將任何可用來作為凸塊下金屬化層134之適合材料及層完全涵蓋在本申請案的範圍中。
半導體晶粒150包含在半導體晶粒150的主動面上的元件墊124以及至少一接合墊132，主動面與半導體晶粒150的背面相對。半導體晶粒150(有時稱為晶片150或晶粒150)可為具有積體電路元件，例如電晶體、電容器、電感器、電阻器(未繪示)及其類似物的元件晶粒。此外，半導體晶粒150可為具有核心電路的邏輯晶粒，且可為例如中央處理單元(central processing unit，CPU)晶粒。在一些實施例中，半導體晶粒150包含多個晶粒堆疊，如記憶體堆疊。
在一些實施例中，利用於半導體晶粒150中或半導體晶粒150上的鈍化層(未繪示)中形成凹陷(未繪示)的方式形成元件墊124以及接合墊132。這些凹陷的形成可使元件墊124以及接合墊132嵌入於半導體晶粒150或鈍化層中。在其他實施例中，可以省略這些凹陷，而元件墊124以及接合墊132可形成於半導體晶粒150的主動面上。元件墊124將後續接合之表面安裝元件120電性耦合至半導體晶粒150，且接合墊132透過導電連接件130將後續接合之半導體晶粒150電性耦合至 基板102。在一些實施例中，元件墊124與接合墊132包含例如使用物理氣相沉積、化學氣相沉積、原子層沉積、其類似方法或前述之組合而沉積在半導體晶粒150上的薄晶種層(圖未示)。晶種層可由銅、鈦、鎳、金、其類似物或前述之組合所製成。元件墊124與接合墊132的導電材料可沉積在薄晶種層上。導電材料可透過電化學電鍍製程、化學氣相沉積、原子層沉積、物理氣相沉積、其類似方法或前述方法之組合所製作。在一實施例中，元件墊124與接合墊132的導電材料為銅、鎢、鋁、銀、金、其類似物或前述之組合。
在一實施例中，元件墊124與接合墊132為凸塊下金屬化層124及132，且包含三層導電材料，例如一層鈦、一層銅以及一層鎳。然而，在此技術領域中具有通常知識者將了解，有許多適合的材料及層的配置，例如鉻/鉻-銅合金/銅/金的配置、鈦/鈦鎢/銅的配置、或銅/鎳/金的配置，都適合形成凸塊下金屬化層124及132。意欲將任何可用來作為凸塊下金屬化層124及132之適合材料及層完全涵蓋在本申請案的範圍中。
表面安裝元件120透過導電連接件122以及元件墊124安裝在半導體晶粒150的主動面。在一實施例中，表面安裝元件102具有兩個接觸點，其透過導電連接件122以及元件墊124電性耦合至半導體晶粒150。在一些實施例中，形成導電連接件122使其具有高度H1，其係從半導體晶粒150之主動面垂直量到導電連接件122的一表面。在一實施例中，高度H1從約20μm至約30μm。
表面安裝元件120可為被動元件，例如電容器、電阻器、電感器、其類似物或前述之組合。在一實施例中，表面安裝元件120實質由一個或多個被動元件所組成，而不包含主動元件，例如電晶體。在一些實施例中，表面安裝元件120包含一個或多個主動元件，例如電晶體。如圖1A所示，表面安裝元件120可包含兩個由導電材料例如焊料、聚合物其類似材料或合金及前述之組合所形成之導電連接件122。在一些實施例中，表面安裝元件120具有高度H2，其係從表面安裝元件120與導電連接件122接觸的第一面垂直量到相對於第一面之第二面。在一實施例中，高度H2可達150μm。
導電連接件122可由金屬膏印刷製程所形成，其可施加在半導體晶粒150的主動面上的元件墊124上。根據元件墊124的位置，可使用印刷模板來將金屬膏印刷在半導體晶粒150上之元件墊124的頂部。對半導體元件施加回焊製程，如此金屬膏可與半導體晶粒150之元件墊124之頂部上的導電連接件122接合。
替代地，可利用設置光阻(未繪示)在半導體晶粒150上、圖案化光阻以在半導體晶粒150的元件墊124上形成複數個開口、以適合的材料例如焊料或其類似材料填充開口、回焊焊料、以及移除光阻以暴露導電連接件122之方式形成導電連接件122。
在一些實施例中，導電連接件122係形成在表面安裝元件120上，而不是形成在半導體晶粒150上。
在導電連接件122形成後，可利用例如安置工具，將表面安裝元件120放置在半導體晶粒150上。在一實施例中，表面安裝元件120係藉由回焊製程而接合在半導體晶粒150上。在此回焊製程中，半導體晶粒150上的元件墊124係與導電連接件122接觸，以將表面安裝元件120實體且電性地耦接至半導體晶粒150。
抗焊塗層110可在導電連接件130形成在接合墊134上方之前，形成在基板102之第一側的部分上。在一實施例中，抗焊塗層110為聚合物、環氧樹脂、其類似材料或前述之組合。在一些實施例中，將抗焊塗層110形成為厚度從約10μm到約40μm。如圖1A所示，抗焊塗層110並未形成於基板102的第一部分上，在半導體晶粒150透過導電連接件130接合至基板102後，第一部分係位於表面安裝元件120的上方。
在表面安裝元件120安裝在半導體晶粒150上，以及在抗焊塗層110形成在基板102的第一側上後，半導體晶粒150的主動面係藉由導電連接件130、接合墊132與134而接合於基板102的第一側。
導電連接件130可為焊球、金屬柱、控制崩潰晶片接合(controlled collapse chip connection，C4)凸塊、微凸塊、無電鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold，ENEPIG)凸塊或其類似物。導電連接件130可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似物或前述之組合。在導電連接件130為焊接凸塊的實施例中，導電連接件130之製作係先透過常見的方 法，例如蒸鍍、電鍍、印刷、移焊、植球或其類似方法形成一層焊料。當一層焊料已形成在結構上後，可進行回焊，以將材料塑形成所需之凸塊形狀。在另一實施例中，導電連接件130為透過濺鍍、印刷、電鍍、無電電鍍、化學氣相沉積或類似方法所形成的金屬柱(例如銅柱)。金屬柱可為無焊料且具有實質垂直的側壁。在一些實施例中，金屬帽層(未繪示)形成於金屬柱連接件130的頂端。金屬帽層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、其類似物或前述之組合，且可利用電鍍製程來製作。
半導體晶粒150以及基板102間的接合可為焊料接合或金屬對金屬(例如銅接銅或錫接錫)直接接合。在一實施例中，半導體晶粒150係透過回焊製程接合於基板102。在此回焊製程期間，導電連接件130係接觸接合墊132與134，以將半導體晶粒150實體且電性耦接至基板102。
在半導體晶粒接合至基板102之後，半導體元件100具有介於抗焊塗層110之表面與半導體晶粒150之主動面之間的間距高度H3。在一實施例中，間距高度H3從約140μm至約170μm。
如圖1A及1B所繪示，表面安裝元件120的側壁以及抗焊塗層110的側壁隔開一段距離D1。在一實施例中，此距離D1大於或等於約10μm，以確保表面安裝元件120在接合後的半導體元件100中具有足夠的空間。例如，在一特定實施例中，表面安裝元件的高度H2約為150μm，導電連接件122的高度H1約為25μm，半導體元件100的間距高度H3約為155μm， 以及抗焊塗層110的厚度約為30μm。在本實施例中，高度H1以及高度H2的總高度為175μm(25μm+150μm)，但間距高度H3只有155μm。然而，在本實施例中，透過移除表面安裝元件120上方的抗焊塗層110，可提供表面安裝元件120約30μm的多餘空間(即抗焊塗層110的厚度)，且表面安裝元件120可安裝在半導體晶粒150以及基板102之間。因此，在本實施例中，若沒有移除表面安裝元件120上方的抗焊塗層110，表面安裝元件120則不能安裝在半導體晶粒150以及基板102之間，且表面安裝元件120可能會受損，並會導致接合墊132及134與導電連接件130之間的接合缺陷或其他各種缺陷及/或問題。
如圖1B所繪示，在平面視角上，抗焊塗層110的移除部分的形狀近似於表面安裝元件120的形狀。然而，在其他實施例中，抗焊塗層110之移除部分的形狀不同於表面安裝元件120的形狀。例如，抗焊塗層110的移除部分在平面視角上實質可為圓形，而表面安裝元件120在平面視角上實質可為方型或矩形。
底部填充材料(未繪示)可透過注入或透過其他的方式成形成在半導體晶粒150與基板102之間的空間中，並且圍繞表面安裝元件120以及導電連接件130。底部填充材料可例如為液態環氧樹脂、塑形膠、矽膠或其類似物，其係施放在半導體晶粒150與基板102之間，然後硬化。底部填充材料使用在其他物件之間，以降低對保護表面安裝元件120以及連接器130的損傷並可保護表面安裝元件120以及連接器130。
應注意的是，圖1A及圖1B所繪示之半導體晶粒(例如半導體晶粒150)、表面安裝元件(例如表面安裝元件120)以及導電連接件(例如導電連接件130及122)的數量僅為示範例子。可有多種變化、修改及替代方案。例如，熟習此項技藝者將了解半導體元件100可容納任何數量的半導體晶粒、表面安裝元件以及導電連接件。
相較於將表面安裝元件安裝在基板上靠近半導體晶粒的位置、或半導體元件上的其他地方，透過將表面安裝元件嵌入半導體晶粒與基板之間的方式，可降低半導體元件的形狀因子。此外，可改善表面安裝元件的信號完整性，故不需要長金屬導線，例如重新分布線(redistribution line)或互連結構來將半導體晶粒耦接至表面安裝元件。再者，由於表面安裝元件上方之抗焊塗層的部分可於導電連接件形成及圖案化的相同製程中形成以及圖案化，故不會產生額外的步驟或花費。
圖2A及圖2B係分別繪示依照本發明之一些實施方式之一半導體元件200之剖面視圖以及平面視圖。在本實施例中，藉由確保元件墊124在平行於半導體晶粒150之主動面的平面中相對於在同一平面中之表面安裝元件120的總面積具有之至少至少最小面積，可進一步控制導電連接件122的高度H1。而且，在本實施例中，表面安裝元件120最靠近基板102的表面與基板102的表面相隔一段距離D3。在一些實施例中，距離D3至少為10μm。有關本實施例的細節與前述實施例類似，在此將不再重述。
表面安裝元件120具有沿著第一側的長度L1，以及沿著第二側的長度L2，其中第一側實質垂直於第一側。在一些實施例中，長度L1從約300μm至約2000μm，且長度L2從約300μm至約2000μm。每一個元件墊124具有沿著第一側的長度L3，以及沿著第二側的長度L4，其中第二側實質垂直於第一側。在一實施例中，所有元件墊124在平行於半導體晶粒150的主動面之一平面中的總面積(例如元件墊的數量x(L3xL4))為同一平面中的表面安裝元件120的總面積(例如L1xL2)的至少十分之一。在一具有兩個元件墊124的實施例中，每一個元件墊124在平行於半導體晶粒150的主動面之一平面中的面積(例如L3xL4)為同一平面中的表面安裝元件120的總面積(例如L1xL2)的至少二十分之一。
透過確保表面安裝元件之元件墊的最小面積，得以控制形成在元件墊上方之導電連接件的總高度。
圖3係繪示依照本發明之一些實施方式之一半導體元件300之剖面視圖。在本實施例中，除了移除表面安裝元件120上方的抗焊塗層110外，基板102係於表面安裝元件120上方凹入一段距離D4。有關本實施例的細節與前述實施例類似，在此將不重述。
在將半導體晶粒150接合至基板102之前，可在基板102之第一側的第一部分中形成凹陷302，當表面安裝元件120接合在半導體元件300中的基板102時，基板102的第一部分係位於表面安裝元件120上方。在一實施例中，從基板102之第一側至凹陷302中之表面的距離D4係大於約10μm。可透 過適合的製程，例如蝕刻製程、雷射、其類似製程或前述製程之組合來形成凹陷302。如圖3所繪示，可設計基板102中的金屬化層104，成藉此使得凹陷302不會與任一金屬化層104衝突。在一些實施例中，凹陷302的側壁實質上對齊於抗焊塗層110之側壁。
透過在表面安裝元件上方形成凹陷於基板中的方式，可增加表面安裝元件的製程窗，以使具有較大高度的表面安裝元件可安裝在基板以及半導體晶粒之間。
圖4A及圖4B係分別繪示依照本發明之一些實施方式之一半導體元件400之剖面視圖以及平面視圖。在本實施例中，基板102具有延伸穿過基板102並且位於表面安裝元件120上方之開口402。有關本實施例的細節與前述實施例類似，在此不重述。
在將半導體晶粒150接合至基板102之前，在基板102的第一部分中形成開口402，當表面安裝元件120接合在半導體元件400中的基板102時，基板102的第一部分係位於表面安裝元件120上方。可透過適合的製程，例如蝕刻製程、雷射、其類似製程或前述製程之組合來形成開口402。如圖4A所繪示，可設計基板102中的金屬化層104，藉此使得開口402不會與任一金屬化層104衝突。在一些實施例中，開口402的側壁實質上對齊於抗焊塗層110之側壁。
透過在表面安裝元件上方形成開口穿過基板的方式，可增加表面安裝元件的製程窗，以使具有較大高度的表面安裝元件可安裝在基板以及半導體晶粒之間。
具有表面安裝元件嵌入於半導體晶粒以及基板之間的半導體元件可提供多個優點，例如相較於表面安裝元件安裝在基板上靠近半導體晶粒的位置或在半導體元件上的其他地方的元件，可降低半導體元件的形狀因子。此外，可改善表面安裝元件的信號完整性，而不需要長金屬導線，例如重新分布線或互連結構來將半導體晶粒耦接至表面安裝元件。再者，由於表面安裝元件上方之抗焊塗層的部分可於導電連接件形成及圖案化的相同製程中形成以及圖案化，故不會產生額外的處理步驟或花費。
一實施例為一種元件，包含抗焊塗層位於基板的第一側上方、晶粒的主動面藉由第一連接件接合於基板的第一側、以及表面安裝元件藉由第二組連接件安裝在晶粒上，表面安裝元件介於晶粒與基板之第一側之間，表面安裝元件與該抗焊塗層分隔。
另一實施例為一種元件，包含抗焊塗層位於印刷電路板的第一側、第一導電連接件耦合於印刷電路板的第一側、以及半導體晶粒藉由第一導電連接件接合於印刷電路板。此元件更包含表面安裝元件耦合於半導體晶粒，表面安裝元件位於半導體晶粒與印刷電路板之間，印刷電路板之第一側的第一部分係暴露在表面安裝元件的上方。
又一實施例為一種製造元件之方法，此方法包含形成抗焊塗層在基板之第一側上方，基板之第一側的第一部分係暴露於抗焊塗層之複數個部分之間；安裝表面安裝元件至半導體晶粒之主動面；以及利用第一導電連接件，將半導體晶粒 之主動面安裝至基板的第一側，基板之第一側的第一部分係位於表面安裝元件之上方。
上述已概述數個實施例的特徵，因此熟習此技藝者可更了解本揭露之態樣。熟習此技藝者應了解到，其可輕易地利用本揭露作為基礎，來設計或潤飾其他製程與結構，以實現與在此所介紹之實施例相同之目的及/或達到相同的優點。熟習此技藝者也應了解到，這類對等架構並未脫離本揭露之精神和範圍，且熟習此技藝者可在不脫離本揭露之精神和範圍下，在此進行各種之更動、取代與修改。
100‧‧‧半導體元件
102‧‧‧基板
104‧‧‧金屬化層
106‧‧‧介電窗
110‧‧‧抗焊塗層
120‧‧‧表面安裝元件
122‧‧‧導電連接件
124‧‧‧元件墊/凸塊下金屬化層
130‧‧‧連接件
132‧‧‧接合墊/凸塊下金屬化層
134‧‧‧接合墊/凸塊下金屬化層
150‧‧‧半導體晶粒/晶片/晶粒
D1‧‧‧距離
H1‧‧‧高度
H2‧‧‧高度
H3‧‧‧間距高度

Claims (20)

  1. 一種元件，包含：一抗焊塗層位於一基板的一第一側上方；一晶粒的一主動面藉由一第一連接件接合於該基板的該第一側；以及一表面安裝元件藉由一第二組連接件安裝在該晶粒上，該表面安裝元件介於該晶粒與該基板之該第一側之間，該表面安裝元件與該抗焊塗層分隔。
  2. 如申請專利範圍第1項所述之元件，更包含一開口，位於該基板之該第一側的一第一部分上方的該抗焊塗層中，該第一部分位於該表面安裝元件的上方。
  3. 如申請專利範圍第2項所述之元件，其中該表面安裝元件之一側壁與該抗焊塗層的一側壁間隔至少10μm。
  4. 如申請專利範圍第2項所述之元件，其中從該晶粒之該主動面量到該表面安裝元件之一第一表面之該表面安裝元件與該第二組連接件的一總高度大於從該晶粒的該主動面到該抗焊塗層的一第一表面之一間距高度，該抗焊塗層的該第一表面遠離該基板的該第一側。
  5. 如申請專利範圍第2項所述之元件，更包含一凹陷，位於該基板之該第一側之一第一部分中，該基板之該第一側之該第一部分係在該表面安裝元件上方。
  6. 如申請專利範圍第5項所述之元件，其中該凹陷的側壁實質上對齊該抗焊層之側壁。
  7. 如申請專利範圍第5項所述之元件，其中該凹陷具有至少10μm之深度。
  8. 如申請專利範圍第1項所述之元件，更包含一開口延伸穿過該基板，該開口位於該表面安裝元件之上方。
  9. 如申請專利範圍第8項所述之元件，其中該開口之側壁實質上對齊該抗焊塗層之側壁。
  10. 一種元件，包含：一抗焊塗層位於一印刷電路板的一第一側；一第一導電連接件耦合於該印刷電路板的該第一側；一半導體晶粒藉由該第一導電連接件接合於該印刷電路板；以及一表面安裝元件耦合於該半導體晶粒，該表面安裝元件位於該半導體晶粒與該印刷電路板之間，該印刷電路板的該第一側的一第一部分係暴露在該表面安裝元件的上方。
  11. 如申請專利範圍第10項所述之元件，其中該抗焊塗層的側壁與該表面安裝元件的側壁相隔至少10μm。
  12. 如申請專利範圍第10項所述之元件，更包含該抗焊塗層的一部分位於該表面安裝元件與該第一導電連接件之間。
  13. 如申請專利範圍第10項所述之元件，更包含一底部填充材料位於該半導體晶粒與該印刷電路板的該第一側之間，該底部填充材料包圍該表面安裝元件以及該第一導電連接件。
  14. 如申請專利範圍第10項所述之元件，更包含：一第一組接合墊位於該半導體晶粒上；以及一第二組導電連接件位於且耦合於該第一組接合墊上，該表面安裝元件耦合於該第二組導電連接件。
  15. 如申請專利範圍第10項所述之元件，其中該印刷電路板之該第一側的該第一部分係比該印刷電路板之該第一側的另一部分凹入至少10μm。
  16. 一種元件之製造方法，該製造方法包含： 形成一抗焊塗層在一基板之一第一側上方，該基板之該第一側的一第一部分係暴露於該抗焊塗層之複數個部分之間；安裝一表面安裝元件至一半導體晶粒之一主動面；以及利用一第一導電連接件，將該半導體晶粒之該主動面安裝至該基板的該第一側，該基板之該第一側的該第一部分係位於該表面安裝元件之上方。
  17. 如申請專利範圍第16項所述之製造方法，其中該表面安裝元件之一側壁與該抗焊塗層的一側壁相隔至少10μm。
  18. 如申請專利範圍第16項所述之製造方法，更包含將該基板之該第一側的該第一部分凹入。
  19. 如申請專利範圍第18項所述之製造方法，其中將該第一部分凹入至少10μm。
  20. 如申請專利範圍第16項所述之製造方法，更包含形成一開口貫穿該基板，該開口對齊於該基板之該第一側的該第一部分。
TW103145299A 2014-02-13 2014-12-24 半導體元件及其製造方法 TWI550795B (zh)

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US20150228580A1 (en) 2015-08-13
US20160079171A1 (en) 2016-03-17
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US9224709B2 (en) 2015-12-29
CN104851842A (zh) 2015-08-19
US9196586B2 (en) 2015-11-24
US20160133606A1 (en) 2016-05-12
CN111613612B (zh) 2022-03-29
TW201532234A (zh) 2015-08-16
KR20150095551A (ko) 2015-08-21
TWI550795B (zh) 2016-09-21
CN104851841A (zh) 2015-08-19
CN111613612A (zh) 2020-09-01
US9589938B2 (en) 2017-03-07
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US9461020B2 (en) 2016-10-04
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