CN104851841A - 包括嵌入式表面贴装器件的半导体封装件及其形成方法 - Google Patents

包括嵌入式表面贴装器件的半导体封装件及其形成方法 Download PDF

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Publication number
CN104851841A
CN104851841A CN201410163132.6A CN201410163132A CN104851841A CN 104851841 A CN104851841 A CN 104851841A CN 201410163132 A CN201410163132 A CN 201410163132A CN 104851841 A CN104851841 A CN 104851841A
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China
Prior art keywords
packaging part
mount device
semiconductor package
surface mount
interconnection structure
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CN201410163132.6A
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English (en)
Inventor
陈宪伟
陈英儒
邱铭彦
叶德强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN202010404784.XA priority Critical patent/CN111613612B/zh
Publication of CN104851841A publication Critical patent/CN104851841A/zh
Pending legal-status Critical Current

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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

本发明的实施例包括半导体封装件及其形成方法。实施例是一种半导体封装件，其包括含有一个或多个管芯的第一封装件和通过第一组连接件接合至第一封装件的第一面的封装衬底。该半导体封装件还包括安装至第一封装件的第一面的表面贴装器件，该表面贴装器件基本由一个或多个无源器件构成。

Description

包括嵌入式表面贴装器件的半导体封装件及其形成方法
相关申请的交叉引用
本申请涉及共同拥有并且共同待决的于2014年2月13日提交的第14/180,138号、标题为“Semiconductor Device including an Embedded SurfaceMount Device and Method of Forming the Same(代理案号TSM13-1758)的专利申请，且全部内容结合于此作为参考。
技术领域
本发明一般地涉及半导体技术领域，更具体地涉及半导体封装件。
背景技术
例如，半导体器件用于各种电子应用中，诸如个人电脑、手机、数码相机以及其他电子设备。通常通过下列步骤制造半导体器件：在半导体衬底的上方顺序沉积绝缘或介电层、导电层和半导体材料层，然后利用光刻工艺图案化各种材料层以形成衬底上的电路部件和元件。
由于各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成度的提高，半导体行业发展迅速。在多数情况下，半导体工艺节点的缩小(例如，将工艺节点缩小至20nm以下的节点)导致了集成度的提高。随着近来对小型化、更高的速度和更宽的宽带以及更低的功耗和时延的需求的增长，对半导体管芯的较小和更具创造性的封装技术的要求也会增长。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体封装件，包括：第一封装件，包括一个或多个管芯；封装衬底，通过第一组连接件接合至所述第一封装件的第一面；以及表面贴装器件，安装至所述第一封装件的第一面，所述表面贴装器件基本由一个或多个无源器件构成。
在该半导体封装件中，所述第一封装件还包括所述第一封装件的第一面上的互连结构，所述表面贴装器件安装在所述互连结构的凹槽内。
在该半导体封装件中，所述凹槽的深度介于约10μm至约30μm之间。
该半导体封装件还包括：位于所述凹槽内且环绕所述表面贴装器件的一部分的密封剂。
在该半导体封装件中，所述表面贴装器件具有两个导电连接件。
该半导体封装件还包括：第二封装件，通过第二组导电连接件接合至所述第一封装件的第二面，所述第二面与所述第一面相对，所述第二封装件包括一个或多个管芯。
在该半导体封装件中，所述第一封装件还包括：电连接件，从所述第一封装件的第二面延伸至所述第一封装件的第一面，所述第二面与所述第一面相对，所述电连接件与所述第一封装件的一个或多个管芯间隔开；以及模塑材料，环绕所述第一封装件的一个或多个管芯和所述第一封装件的电连接件。
在该半导体封装件中，所述表面贴装器件中的一个或多个无源器件选自由电容器、电阻器、电感器或它们的组合所组成的组。
根据本发明的另一方面，提供了一种半导体封装件，包括：第一封装件，包括：第一管芯，具有第一面和第二面，所述第二面与所述第一面相对；互连结构，位于所述第一管芯的第一面的上方，所述互连结构包括N个金属层和M个钝化层；表面贴装器件，安装至所述互连结构的第一部分内的所述N个金属层中的一个，所述第一部分具有的钝化层数量少于M个；和一组凸块下金属化层(UBM)，连接至所述第一封装件的互连结构的第N个金属层，所述第N个金属层是距离所述第一管芯的第一面最远的金属层；第一组导电连接件，连接至所述一组UBM；以及封装衬底，接合至所述第一组导电连接件。
在该半导体封装件中，所述表面贴装器件安装至所述互连结构的第N个金属层。
在该半导体封装件中，所述表面贴装器件安装至所述互连结构的第一金属层，所述第一金属层是距离所述管芯的第一面最近的金属层。
在该半导体封装件中，所述互连结构的第一部分具有M-1个钝化层。
在该半导体封装件中，所述互连结构的第一部分具有一个钝化层。
在该半导体封装件中，所述表面贴装器件的侧壁与第M个钝化层的侧壁至少间隔10μm。
在该半导体封装件中，所述表面贴装器件基本由一个或多个无源器件构成。
该半导体封装件还包括：第二封装件，包括第二管芯，所述第二封装件通过第二组连接件接合至所述第一管芯的第二面。
根据本发明的又一方面，提供了一种方法，包括：形成第一封装件，包括：在第一管芯的第一面的上方形成互连结构；使所述互连结构的一部分凹进；和将表面贴装器件安装在所述互连结构的凹进部分中；以及使用第一组导电连接件将所述第一封装件的互连结构接合至封装衬底。
该方法还包括：对所述互连结构的凹进部分内的所述表面贴装器件进行封装。
在该方法中，使所述互连结构的一部分凹进还包括：从所述互连结构的该部分上去除至少一个钝化层。
在该方法中，使所述互连结构的一部分凹进还包括：从所述互连结构的该部分上去除至少一个钝化层和至少一个金属层。
附图说明
当结合附图进行阅读时，通过以下详细描述可以更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚地讨论，各种部件的尺寸可以被任意地增大或减小。
图1示出了根据一些实施例的半导体封装件。
图2示出了根据一些实施例的半导体封装件。
图3示出了根据一些实施例的半导体封装件。
具体实施方式
以下发明内容提供了多种不同实施例或实例，以实现本发明的不同特征。以下将描述部件和布置的特定实例以简化本发明。当然，这些仅是实例而不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括以直接接触的方式形成第一部件和第二部件的实施例，也可以包括附加部件形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。此外，本发明可在各种实例中重复使用参考数字和/或字母。这种重复出于简化和清楚的目的，但且其本身并不表示所述多个实施例和/或配置之间的关系。
此外，本发明可使用空间相对术语，诸如，“在…之下”、“在…下面”、“下面的”、“在…上面”、以及“上面的”等，以易于描述如图所示的一个元件或部件与另一元件或部件的关系。空间关系术语意欲包括除附图所示的方位之外的处于使用或操作中的装置的不同的方位。装置可以以其他方式定位(旋转90度或在其他方位)，也可相应地对本发明所使用的空间关系描述符做出解释。
参照具体语境(即，制造和使用包括表面贴装器件的半导体封装件)来描述实施例。然而，其他实施例也可应用于其他电连接部件，包括但不限于层叠封装组件、管芯-管芯组件、晶圆-晶圆组件、管芯-衬底组件；正在组装的封装、正在处理的衬底、中介层、衬底等；或安装输入部件、面板、管芯或其他部件；或者封装或安装任何类型的集成电路或电组件的组合的连接。
图1示出了根据一些实施例的半导体封装件400。该半导体封装件400包括衬底102、衬底102上方的第一封装件200以及第一封装件200上方的第二封装件300。
衬底102可由半导体材料制成，诸如，硅、锗、金刚石等。可选地，也可使用复合材料，诸如，硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷铟化镓及它们的组合等。此外，衬底102可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料层。在一个可选实施例中，衬底102基于绝缘芯，诸如，玻璃纤维增强的树脂芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的替换物包括双马来酰亚胺三嗪(BT)树脂，或者可选地，其他PC板材料或膜。累积膜(如Ajinomoto增层膜(ABF))或其他层压件可用于衬底102。衬底102可被称为封装衬底102。
衬底102可包括有源和无源器件(图1中未示出)。本领域的技术人员应该意识到，诸如晶体管、电容器、电阻器及它们的组合等各种器件可用于满足半导体封装件400设计的结构和功能的要求。使用任何合适的方法可形成这些器件。
衬底102也可包括金属化层(未示出)。金属化层可形成在有源和无源器件的上方并且被设计为连接各种器件以形成功能性电路。金属化层可由交替的介电层(例如，低k介电材料)和导电材料层(例如，铜)形成，其中，通孔互连各导电材料层，并且可通过任何合适的工艺(诸如，沉积、镶嵌、双镶嵌等)来形成该通孔。在一些实施例中，衬底102基本没有有源和无源器件。
衬底102包括接合焊盘104。接合焊盘104可形成在衬底102的第一面内。在一些实施例中，通过使凹槽(未示出)形成在衬底102或其上的钝化层(未示出)中来形成接合焊盘104。可形成凹槽以允许接合焊盘104嵌入到衬底102或钝化层中。在其他实施例中，由于接合焊盘104可形成在衬底102的第一面上，所以可省去凹槽。接合焊盘104将随后接合的第一200封装件和/或第二封装件300电和/或物理连接至衬底102的有源和无源器件(如果存在)和/或衬底102的第二面上的连接件(未示出)。在一些实施例中，接合焊盘104包括通过诸如物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)等或它们的组合而沉积在衬底102上的薄晶种层(未示出)。晶种层可由铜、钛、镍、金等或它们的组合制成。接合焊盘104的导电材料可沉积在薄晶种层的上方。导电材料可通过电化学镀工艺、CVD、ALD、PVD等或它们的组合形成。在一个实施例中，接合焊盘104的导电材料是铜、钨、铝、银、金等或它们的组合。
在一个实施例中，接合焊盘包括三层导电材料，诸如，钛层、铜层和镍层。然而，本领域的技术人员会意识到，存在很多合适的材料和层的布置，诸如，铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置，这些布置适合形成接合焊盘104。可用于接合焊盘104的任何合适的材料或材料层全部包含在本申请的范围内。
第一封装件200包括封装在模塑材料208内的一个或多个管芯202(202A和202B)。管芯202连接至第一面上的一组接合焊盘205并且在第二面上具有一组接触区210，第二面与第一面相对。一组电连接件206从接合焊盘204延伸穿过与管芯202相邻的模塑材料208。电连接件206从管芯202的第一面延伸至管芯202的第二面。互连结构212形成在管芯202的第二面和电连接件206的上方。互连结构212包括交替的钝化层(P1、PN和PN+1)和金属化层(M1和MX)，其中，金属化层通过延伸穿过钝化层的通孔连接。表面贴装器件250直接连接至金属化层MX。
在一个实施例中，通过在载体衬底(未示出)的上方形成接合焊盘204和205来形成第一封装件200。接合焊盘204和205可由与上述的接合焊盘104相似的材料形成并且通过与上述的接合焊盘104相似的工艺形成，因此，此处不再重复描述，但是接合焊盘204和205以及接合焊盘104无需相同。
电连接件206可以是通过以下步骤所形成的柱形凸块(stud bump)：通过引线接合在接合焊盘204上并且切割接合引线，从而保留的部分接合引线附接至相应的接合焊球。例如，在图1中，电连接件206包括下部和上部，其中，下部可以是在引线接合过程中所形成的接合焊球，而上部可以是剩余的接合引线。电连接件206的上部可具有一致的宽度和一致的形状，即，在该上部的整个顶部、中部和底部均具有一致的宽度和一致的形状。电连接件206由可通过引线接合器(wire bonder)接合的非焊料金属材料形成。在一些实施例中，电连接件206由铜线、金线等或它们的组合制成，并且可具有包括多层的复合结构。
在可选实施例中，通过电镀形成电连接件206。在这些实施例中，电连接件206由铜、铝、镍、金、银、钯等或它们的组合制成，并且可具有包括多层的复合结构。在这些实施例中，牺牲层(未示出)形成在载体衬底的上方。多个开口形成在牺牲层中，以露出下面的接合焊盘204。然后进行镀步骤，以电镀电连接件206。在电连接件206形成之后，去除牺牲层。
在形成接合焊盘205之后，管芯202的第一面可连接至接合焊盘205。管芯202(202A和202B)可以是单个管芯或可以是两个以上的管芯。管芯202可包括逻辑管芯，诸如中央处理器(CPU)、图形处理器(GPU)等或它们的组合。在一些实施例中，管芯202包括管芯堆叠件(未示出)，其可同时包括逻辑管芯和存储器管芯。管芯202可包括输入/输出(I/O)管芯，诸如宽I/O管芯，该宽I/O管芯提供了第一封装件200和随后附接的第二封装件300之间的连接。
管芯202的第二面上的接触区210可与上述的接合焊盘104相似，此处不再重复描述，但是接触区210和接合焊盘104无需相同。
然后可封装管芯202和电连接件206。在一些实施例中，管芯202和电连接件206通过模塑材料208进行封装。例如，可使用压缩模塑将模塑材料208模制在管芯202和电连接件206上。在一些实施例中，模塑材料208由模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合制成。可进行固化步骤，以固化模塑材料208，其中，固化可以是热固化、紫外线(UV)固化等。
在一些实施例中，管芯202、接触区210和电连接件206被埋于模塑材料208中，并且在固化模塑材料208之后，进行平坦化步骤(诸如，研磨)以去除模塑材料208的多余部分，其中，多余部分位于接触区210和电连接件206的顶面的上方。在一些实施例中，接触区210的表面和电连接件206的表面露出，并且与模塑材料208的表面平齐。电连接件206可被称为模塑通孔(TMV，molding vias)并且在下文将被称为TMV206。
互连结构212可形成在管芯202的接触区210和TMV206的上方并且与它们电连接。互连结构包括一个以上的钝化层，即，P1、PN和PN+1，其中，钝化层P1是紧接接触区210和TMV206的钝化层，而钝化层PN+1(有时被称为顶部钝化层PN+1)是紧接凸块下金属化层(UBM)220的钝化层。互连结构212还包括一个以上的金属层，即，M1和MX，其中，金属层M1是紧接钝化层P1的金属层，而金属层MX(有时也被称为顶部金属层MX)是紧接UMB220的金属层。在整篇描述中，术语“金属层”是指同一层内的金属线的集合。
钝化层(P1、PN和PN+1)可以是氮化硅、碳化硅、氧化硅、低k电介质(诸如，掺杂碳的氧化物)、超低k电介质(诸如，掺多孔碳的二氧化硅)、聚合物(诸如，环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO))等或它们的组合，但是也可使用其他相对柔软、通常为有机的介电材料，并且通过CVD、PVD、ALD、旋涂电介质工艺等或它们的组合来沉积钝化层。在一个实施例中，形成的每个钝化层(P1、PN和PN+1)的厚度都介于约2μm和约15μm之间。
可使用单和/或双镶嵌工艺、先通孔工艺或先金属工艺来形成金属层M1和MX。金属层(M1和MX)和通孔可由导电材料(诸如，铜、铝、钛等或它们的组合)形成，并且具有或没有阻挡层。在一个实施例中，金属层M1至MX中的每一层的厚度都在约1μm至约12μm之间的范围内。
镶嵌工艺是形成嵌入另一层内的图案化层，使得两层的顶面共面。仅仅产生沟槽或通孔的镶嵌工艺被称为单镶嵌工艺。一次产生沟槽和通孔的镶嵌工艺被称为双镶嵌工艺。
在一个示例性实施例中，使用双镶嵌工艺形成金属层M1至MX。在该实例中，可以从在钝化层P1上形成蚀刻停止层(未示出)和在蚀刻停止层上形成钝化层PN开始形成M1层。一旦沉积了钝化层PN，钝化层PN的部分可被蚀刻掉以形成凹槽部件(诸如，沟槽和通孔)，其能够用导电材料填充以连接互连结构212的不同区域并且容置金属线和通孔。可对直至MX的剩余金属层重复进行该工艺。
金属层M1至MX的数量和钝化层P1至PN+1的数量仅用于说明的目的而不用于限制。其他数量的金属层可以大于或少于所示出的两个金属层。可具有不同于图1所示的其他数量的钝化层和其他数量的金属层。
UMB220可形成在金属层MX的上方并且与其电连接。可形成穿过钝化层PN+1的一组开口(未示出)以露出金属层MX内的金属线的表面。UMB220可延伸穿过钝化层PN+1内的这些开口并且也沿着钝化层PN+1的表面延伸。UMB220可包括三个导电材料层，诸如，钛层、铜层和镍层。然而，本领域的技术人员会意识到，具有很多合适的材料和层的布置，诸如，铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置，这些布置适合形成UBM220。可用于UBM220的任何合适的材料或材料层完全包含在本申请的范围内。
表面贴装器件250经由导电连接件260直接安装至顶部金属层MX的一条或多条金属线270。通过合适的工艺(诸如，蚀刻工艺、激光等或它们的组合)，可去除顶部钝化层PN+1中覆盖金属线270的部分。通过去除顶部钝化层PN+1的部分而形成的凹槽的深度为距离D1。在一个实施例中，距离D1介于约10μm至约30μm之间。
在一个实施例中，表面贴装器件250具有两个接触件，其通过导电连接件260和金属线270电连接至互连结构212。在一些实施例中，形成的导电连接件260具有从表面贴装器件250到导电连接件260的表面之间所垂直测量的高度，该高度介于约10μm至约30μm之间。
表面贴装器件250可包括一个或多个无源部件，诸如，电容器、电阻器、电感器等或它们的组合。在一个实施例中，表面贴装器件250基本由一个或多个无源器件构成而不包括诸如晶体管的有源器件。如图1所示，表面贴装器件250可包括由导电材料(诸如，焊料等或它们的组合)形成的两个导电连接件260。在一些实施例中，表面贴装器件250具有介于约0.4mm至约1.5mm之间的长度、介于约0.1mm至约0.8mm之间的宽度以及介于约0.1mm至约0.2mm之间的厚度。
可通过应用于金属线270的金属焊膏印刷工艺来形成导电连接件260。根据金属线270的位置，可使用模板以在金属线270的顶部上印刷金属焊膏。将回流工艺应用于半导体封装件，使得金属焊膏可接合为互连结构212的金属线270的顶部上的导电连接件260。
可选地，可通过以下步骤来形成导电连接件260：在互连结构212的上方设置光刻胶(未示出)、图案化光刻胶以在互连结构212的金属线270的上方形成多个开口、用合适的材料(诸如，焊料等)填充开口、使焊料回流以及去除光刻胶以露出导电连接件260。
在一些实施例中，导电连接件260形成在表面贴装器件250上，而不是形成在互连结构212上。
在形成导电连接件260之后，例如，可通过拾取和放置工具将表面贴装器件250放置在互连结构212的凹槽内。在一个实施例中，表面贴装器件250通过回流工艺接合至互连结构212。在该回流工艺过程中，互连结构212的金属线270与导电连接件260接触，以将表面贴装器件250物理并且电连接至互连结构212。
由于表面贴装器件250安装至金属线270，所以，表面贴装器件250中距离钝化层PN最近的表面以距离D2与钝化层PN间隔开，在一个实施例中，该距离D2介于约10μm至约30μm之间。金属线270和导电连接件260的侧壁以距离D3与顶部钝化层PN+1的侧壁间隔开，在一个实施例中，该距离D3大于10μm。
将表面贴装器件250安装至金属线270之后，第一封装件200通过导电连接件230、UBM220和接合焊盘104接合至衬底102。将第一封装件200接合至衬底102之前，可切割第一封装件200(如有必要)并且可去除载体衬底(未示出)。
导电连接件230可以是焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍钯浸金技术(ENEPIG)形成的凸块等。导电连接件230可包括导电材料，诸如，焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在导电连接件230是焊料凸块的实施例中，通过常用方法(诸如，蒸发、电镀、印刷、移焊、植球等)先形成焊料层来形成导电连接件230。一旦在结构上已形成焊料层，就可以进行回流以使材料成型为预期的凸块形状。在另一个实施例中，导电连接件230是通过溅射、印刷、电镀、化学镀、CVD等所形成的金属柱(诸如，铜柱)。金属柱可无焊料并且具有大致垂直的侧壁。在一些实施例中，金属保护层(未示出)形成在金属柱连接件230的顶部。金属保护层可包括镍、锡、锡-铅、金、银、钯、铟、镍钯金、镍-金等、或它们的组合，并且可通过镀工艺来形成。
第一封装件200和衬底102之间的接合可以是焊料接合或直接金属与金属(诸如，铜与铜或锡与锡)接合。在一个实施例中，第一封装件200通过回流工艺接合至衬底102。在该回流工艺过程中，导电连接件230与接合焊盘104和UBM220接触以将第一封装件200物理并且电连接至衬底102。
在第一封装件200接合至衬底102之前或之后，可形成第二封装件300并且将其接合至第一封装件200。第二封装件300包括衬底302和连接至衬底302的一个或多个堆叠的管芯310。
衬底302可具有衬底302的第一面上的接合焊盘304以连接至堆叠的管芯310，并且具有衬底302的第二面上的接合焊盘306以连接至导电连接件308，衬底302的第一面与第二面相对。衬底302可与上述的衬底102相似，因此此处不再重复描述，但是衬底302和102无需相同。在一些实施例中，衬底302可包括形成于其上的电子部件和元件，或者可选地，衬底302可没有电子部件和元件。
在所示的实施例中，堆叠的管芯310通过接合引线312连接至衬底302，但是可使用诸如导电凸块的其他连接。在一个实施例中，堆叠的管芯310是堆叠的存储器管芯。例如，堆叠的存储管芯310可包括低功率(LP)双倍数据速率(DDR)存储模块，诸如，LPDDR1、LPDDR2、LPDDR3等存储模块。堆叠的存储管芯310可通过接合引线312、接合焊盘304和306以及导电连接件308连接至第一封装件200。
在一些实施例中，模塑材料314可封装堆叠的管芯310和接合引线312。例如，可使用压缩模塑工艺将模塑材料314模制在堆叠的管芯310和接合引线312上。在一些实施例中，模塑材料314是模塑料、聚合物、环氧树脂、氧化硅填充物材料等或它们的组合。可进行固化步骤以固化模塑材料314，其中，固化可以是热固化、UV固化等。
在一些实施例中，堆叠的管芯310和接合引线312埋入模塑材料314中，并且在固化模塑材料314之后，进行平坦化步骤(诸如，研磨)以去除模塑材料314的多余部分并且提供第二封装件300的大致平坦的表面。
在第二封装件300形成之后，第二封装件300通过导电连接件308和接合焊盘306和204而接合至第一封装件200。
导电连接件308可与上述的导电连接件230相似，因此此处不再重复描述，但是导电连接件308和230无需相同。
第二封装件300和第二封装件200之间的接合可以是焊料接合或直接金属与金属(诸如，铜与铜或锡与锡)接合。在一个实施例中，第二封装件300通过回流工艺接合至第一封装件200。在该回流工艺过程中，导电连接件308与结合焊盘306和204接触，以将第二封装件300物理连接并且电连接至第一封装件200。
底部填充材料(未示出)可被注入或以其他方式形成在第一封装件200和第二封装件300之间的空间内并且环绕导电连接件308。此外，底部填充材料(未示出)可被注入或以其他方式形成在第一封装件200和衬底102之间的空间内并且环绕表面贴装器件250和导电连接件230。例如，底部填充材料可以是分散于各个结构之间的液态环氧树脂、可变形凝胶、硅橡胶等，然后使其固化变硬。除此之外，使用该底部填充材料，以减少对表面贴装器件250和导电连接件230和308的损害并且保护表面贴装器件250和导电连接件230和308。
应该注意，图1中所示的半导体管芯(例如，半导体管芯202)、表面贴装器件(例如，表面贴装器件250)以及导电连接件(例如，导电连接件230和308)的数量仅为实例。可以有很多变化、修改和替代。例如，本领域的技术人员将会意识到，半导体封装件400可容置任何数量的半导体管芯、表面贴装器件和导电连接件。
通过将表面贴装器件嵌入封装件和封装衬底之间，与其中表面贴装器件安装在与封装件邻近的封装衬底上或半导体封装件的其他位置的封装件相比，半导体封装件的形状因数能够被降低。此外，因为无需长的金属导体(诸如，再分布线或互连件)将互连件和/或管芯连接至表面贴装器件，所以提高了表面贴装器件的信号完整性。
图2示出了根据一些实施例的半导体封装件600。除了半导体封装件600包括表面贴装器件250直接安装至第一金属层M1内的金属线的第一封装件500之外，半导体封装件600与上述的半导体封装件400相似。本实施例与先前所述实施例相似的具体细节此处不再重复。
在该实施例中，表面贴装器件250通过导电连接件260直接安装至第一金属层M1的一条或多条金属线280。除了P1之外的所有钝化层(例如，PN和PN+1)中的覆盖金属线280的部分可通过合适的工艺(诸如，蚀刻工艺、激光等或它们的组合)来去除。通过去除除了P1之外的所有钝化层(例如，PN和PN+1)中的覆盖金属线280的部分所形成的凹槽的深度为距离D4。在一个实施例中，距离D4介于约15μm至约40μm之间。
例如，可通过拾取和放置工具将表面贴装器件250放置于互连结构212上。在一个实施例中，表面贴装器件250通过回流工艺接合至互连结构212。在该回流工艺过程中，互连结构212上的金属线280与导电连接件260接触，以将表面贴装器件250物理连接并且电连接至互连结构212。
应该注意，在互连结构212内具有两个以上的金属层的情况下，表面贴装器件250能够直接安装至M1和MX之间的任何金属层。
通过去除除了第一钝化层之外的所有钝化层和将表面贴装器件安装在第一金属层上，表面贴装器件的工艺窗口得以放大。这样能够允许较大的表面贴装器件安装在封装件和封装衬底之间。
图3示出了根据一些实施例的半导体封装件800。除了半导体封装件800包括用密封剂290封装的表面贴装器件250的第一封装件700之外，半导体封装件800与上述的半导体封装件600相似。此处不再重复该实施例中与上述实施例相似的具体细节。
在该实施例中，用密封剂290封装表面贴装器件250。例如，可使用压缩模塑将密封剂290模制在表面贴装器件250上。在一些实施例中，密封剂290是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可进行固化步骤以固化模塑材料314，其中，固化可以是热固化、UV固化等。在一些实施例中，密封剂290延伸越过顶部钝化层PN+1的表面。在其他实施例中，密封剂290具有的表面与顶部钝化层PN+1的表面基本共面。
通过用密封剂封装表面贴装器件，防止表面贴装器件受潮并且密封剂可缓冲一些热和物理应力。密封剂可提高具有表面贴装器件的半导体封装件的产量。
本发明的一个实施例是一种半导体封装件，该半导体封装件包括含有一个或多个管芯的第一封装件以及通过第一组连接件接合至第一封装件的第一面的封装衬底。半导体封装件还包括安装至第一封装件的第一面的表面贴装器件，其中，表面贴装器件基本由一个或多个无源器件构成。
本发明的另一个实施例是一种半导体封装件，包括：含有第一管芯的第一封装件，第一管芯具有第一面和第二面，该第二面与该第一面相对；位于第一管芯的第一面上方的互连结构，该互连结构包括N个金属层和M个钝化层；表面贴装器件，安装至互连结构的第一部分内的N个金属层中的一层上，该第一部分的钝化层的数量少于M；以及一组凸块下金属化层(UBM)，连接至第一封装件的互连结构的第N个金属层，该第N个金属层是距离第一管芯的第一面最远的金属层。半导体封装件还包括连接至该组UBM的第一组导电连接件和接合至该第一组导电连接件的封装衬底。
本发明的又一个实施例是一种方法，包括：形成第一封装件(包括在第一管芯的第一面的上方形成互连结构)；使该互连结构的一部分凹进；以及将表面贴装器件安装在该互连结构的凹进部分内。该方法还包括使用第一组导电连接件将第一封装件的互连结构接合至封装衬底。
上面论述了几个实施例的特征，使得本领域的普通技术人员可以更好地理解本发明的各个方面。本领域的普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改用于达到与本发明所介绍的实施例相同的目的和/或实现与其相同有益效果的其他工艺和结构。本领域的普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种改变、替换以及变化。

Claims (10)

1.一种半导体封装件，包括：
第一封装件，包括一个或多个管芯；
封装衬底，通过第一组连接件接合至所述第一封装件的第一面；以及
表面贴装器件，安装至所述第一封装件的第一面，所述表面贴装器件基本由一个或多个无源器件构成。
2.根据权利要求1所述的半导体封装件，其中，所述第一封装件还包括所述第一封装件的第一面上的互连结构，所述表面贴装器件安装在所述互连结构的凹槽内。
3.根据权利要求2所述的半导体封装件，其中，所述凹槽的深度介于约10μm至约30μm之间。
4.根据权利要求2所述的半导体封装件，还包括：位于所述凹槽内且环绕所述表面贴装器件的一部分的密封剂。
5.根据权利要求1所述的半导体封装件，其中，所述表面贴装器件具有两个导电连接件。
6.根据权利要求1所述的半导体封装件，还包括：第二封装件，通过第二组导电连接件接合至所述第一封装件的第二面，所述第二面与所述第一面相对，所述第二封装件包括一个或多个管芯。
7.根据权利要求1所述的半导体封装件，其中，所述第一封装件还包括：
电连接件，从所述第一封装件的第二面延伸至所述第一封装件的第一面，所述第二面与所述第一面相对，所述电连接件与所述第一封装件的一个或多个管芯间隔开；以及
模塑材料，环绕所述第一封装件的一个或多个管芯和所述第一封装件的电连接件。
8.根据权利要求1所述的半导体封装件，其中，所述表面贴装器件中的一个或多个无源器件选自由电容器、电阻器、电感器或它们的组合所组成的组。
9.一种半导体封装件，包括：
第一封装件，包括：
第一管芯，具有第一面和第二面，所述第二面与所述第一面相对；
互连结构，位于所述第一管芯的第一面的上方，所述互连结构包括N个金属层和M个钝化层；
表面贴装器件，安装至所述互连结构的第一部分内的所述N个金属层中的一个，所述第一部分具有的钝化层数量少于M个；和
一组凸块下金属化层(UBM)，连接至所述第一封装件的互连结构的第N个金属层，所述第N个金属层是距离所述第一管芯的第一面最远的金属层；
第一组导电连接件，连接至所述一组UBM；以及
封装衬底，接合至所述第一组导电连接件。
10.一种方法，包括：
形成第一封装件，包括：
在第一管芯的第一面的上方形成互连结构；
使所述互连结构的一部分凹进；和
将表面贴装器件安装在所述互连结构的凹进部分中；以及
使用第一组导电连接件将所述第一封装件的互连结构接合至封装衬底。
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