CN105679681A - 集成电路封装焊盘以及形成方法 - Google Patents

集成电路封装焊盘以及形成方法 Download PDF

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Publication number
CN105679681A
CN105679681A CN201510851861.5A CN201510851861A CN105679681A CN 105679681 A CN105679681 A CN 105679681A CN 201510851861 A CN201510851861 A CN 201510851861A CN 105679681 A CN105679681 A CN 105679681A
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China
Prior art keywords
hole
layer
integrated circuit
dorsal part
ground floor
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CN201510851861.5A
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CN105679681B (zh
Inventor
余振华
陈宪伟
吴集锡
叶德强
苏安治
陈威宇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体器件及其制造方法。该半导体器件包括具有通孔的集成电路，通孔邻近集成电路管芯，其中，在集成电路管芯和通孔之间插入模塑料。通孔具有延伸穿过图案化层的凸出物，并且通孔可以从图案化层的表面偏移。可以通过选择性地去除用于形成通孔的晶种层形成凹槽。本发明实施例涉及集成电路封装焊盘以及形成方法。

Description

集成电路封装焊盘以及形成方法
相关申请的交叉引用
本申请要求于2014年12月3日提交的名称为“IntegratedCircuitPackagePadandMethodsofFormingSame”的美国临时专利申请第62/087，090号的优先权，其全部内容结合于此作为参考。
技术领域
本发明实施例涉及集成电路封装焊盘以及形成方法。
背景技术
半导体器件用于各种电子应用中，诸如个人计算机、手机、数码相机和其他电子设备。通常通过以下步骤来制造半导体器件：在半导体衬底上方相继沉积绝缘或介电层、导电层和半导体材料层；以及使用光刻来图案化该多个材料层，以在该多个材料层上形成电路组件和元件。通常，在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线锯切集成电路来分割单独的管芯。然后，以多芯片模式或以其他封装类型来分别地封装单独的管芯。
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度不断提高，半导体行业已经历了快速的发展。在很大程度上，集成密度的这种提高源自于最小部件尺寸的不断减小(例如，将半导体工艺节点减小至亚20nm节点)，这允许在给定区域内集成更多的组件。由于对小型化的需求，近来已经发展了更高速度和更大带宽以及更低功耗和延迟，所以已经产生一种更小且更富创造性的半导体管芯封装技术的需要。
随着半导体技术的进一步发展，已经出现了堆叠的半导体器件(例如，三维集成电路(3DICs))作为有效替代以进一步减小半导体器件的物理尺寸。在堆叠的半导体器件中，在不同的半导体晶圆上制造诸如逻辑电路、存储器电路、处理器电路等的有源电路。两个或更多的半导体晶圆可以彼此安装或堆叠以进一步降低半导体器件的形状因数。叠层封装件(POP)器件是一种类型的3DIC，其中，封装管芯并且然后将管芯与另一封装过的管芯或管芯封装在一起。
发明内容
根据本发明的一个实施例，提供了一种制造半导体器件的方法，所述方法包括：在载体衬底上方形成第一层；在所述第一层上形成通孔；在所述第一层上方放置集成电路管芯；在所述第一层上方形成模塑料，所述模塑料沿着所述集成电路管芯和所述通孔的侧壁延伸；去除所述载体衬底，暴露所述第一层；以及完全去除所述第一层，因此暴露所述通孔。
根据本发明的另一实施例，还提供了一种制造半导体器件的方法，所述方法包括：在载体衬底上方形成第一层，所述第一层具有开口；在所述第一层上形成通孔，所述通孔具有延伸至所述开口内的通孔凸出物；在所述第一层上方放置集成电路管芯；在所述第一层上方形成模塑料，所述模塑料沿着所述集成电路管芯和所述通孔的侧壁延伸；在所述集成电路管芯和所述通孔上方形成再分布层；去除所述载体衬底，暴露所述第一层；以及使所述第一层凹进使得所述通孔从所述第一层突出。
根据本发明的又另一实施例，还提供了一种半导体器件，包括：集成电路管芯，所述集成电路管芯具有正侧和背侧；模塑料，邻近所述集成电路管芯的侧壁；以及第一层，在所述模塑料上方、具有延伸穿过所述第一层的通孔凸出物的通孔上方延伸。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1至图9是根据一些实施例的形成半导体器件的各个中间步骤的截面图。
图10至图12是根据一些实施例的形成半导体器件的各个中间步骤的截面图。
图13至图20是根据一些实施例的形成半导体器件的各个中间步骤的截面图。
图21至图23是根据一些实施例的形成半导体器件的各个中间步骤的截面图。
图24至图31是根据一些实施例的形成半导体器件的各个中间步骤的截面图。
图32至图40是根据一些实施例的形成半导体器件的各个中间步骤的截面图。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等空间关系术语以描述如图所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外，空间关系术语意欲包括使用或操作过程中的器件的不同的方位。装置可以以其它方式定位(旋转90度或在其他方位)，并且通过在本文中使用的空间关系描述符可同样地作相应地解释。
将结合在具体的环境中的实施例来描述实施例，即，三维(3D)集成扇出(InFO)叠层封装件(PoP)器件。然而，其他实施例也可以应用于其他电连接组件，其他电连接组件包括但不限定于，处理衬底、插入件、衬底等中、装配封装或安装输入组件、板、管芯或其他组件中的叠层封装件装配、芯片与芯片装配、晶圆与晶圆装配、芯片与衬底装配，或其他实施例也可以应用于连接封装或安装任何类型的集成电路或电子部件的组合。
图1至图9示出了根据一些实施例的在形成半导体封装件中的中间步骤的截面图。首先，参照图1，图1示出了具有释放层102的载体衬底100以及在其上形成的背侧介电层104。通常地，载体衬底100在后续的工艺步骤中提供临时的机械和结构支撑。例如，载体衬底102可以包括任何合适的材料，诸如硅基材料(诸如硅晶圆、玻璃或氧化硅)或其他材料(诸如氧化铝、陶瓷材料)、这些材料的任意组合等。在一些实施例中，为了适应进一步的工艺，载体衬底100是平坦的。
释放层120是形成在载体衬底100上方的可选层，可以允许更加容易地去除载体衬底100。如下面更详细的解释，各个层和器件将放置在载体衬底100的上方，之后可以去除载体衬底100。可选的释放层102有助于载体衬底100的去除，减少了对形成在载体衬底100上方的结构的损坏。释放层102可以由基于聚合物的材料形成。在一些实施例中，释放层102是诸如光热转换(LTHC)释放涂层的基于环氧树脂的热释放材料，该材料在被加热时失去其粘性。在其他实施例中，释放层102可以是紫外(UV)胶，当紫外(UV)胶暴露于UV光时失去其粘性。释放层102可以作为液体被分配并且被固化。在其他实施例中，释放层102可以是层压到载体衬底102上的层压薄膜。可以使用其他释放层。
例如，通过旋转涂覆、层压、化学汽相沉积(CVD)等形成的背侧介电层104可以是聚合物(诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等)、氮化物(诸如氮化硅等)、氧化物(诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)或它们的组合等)等。在一些实施例中，背侧介电层104具有约1μm至约10μm的厚度，诸如约7μm。
现在，参考图2，根据一些实施例，图2示出了通孔206的形成。通孔206提供从封装件的一侧到封装件的另一侧的电连接。例如，下面将做出更详细的解释，管芯将被安装至背侧介电层104并且围绕通孔和管芯形成模塑料。随后，诸如另一个管芯、封装件、衬底等的另一个器件，可以附接至管芯和模塑料。通孔206提供另一个器件和封装件的背侧之间的电连接，无需通过安装至背侧介电层104上的管芯传递电信号。
例如，可以通过在背侧介电层104上方形成导电晶种层(未示出)形成导电通孔206。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。晶种层可由铜、钛、镍、金或它们的组合等制成。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。例如，可以使用物理汽相沉积(PVD)、CVD、原子层沉积(ALD)、它们的组合等形成晶种层。晶种层可以包括一个或多个层。
沉积并且图案化掩模(诸如图案化的光刻胶层)以限定通孔206的形状，其中掩模中的开口暴露晶种层。例如，使用化学镀工艺或电化学镀工艺利用导电材料填充开口。镀工艺在图案化光刻胶中可以单向填充开口(例如，从晶种层向上)。单向填充可以允许这种开口的更均匀填充，特别是具有高纵横比的通孔。可选地，可以在图案化的光刻胶中的开口的侧壁上形成晶种层，并且可以多向填充这种开口。随后，如图2所示，在灰化和/或湿削离工艺中去除光刻胶，并且蚀刻晶种层多余的材料，保留背侧介电层104上方的通孔206。通孔206也可以通过引线接合工艺利用金属丝钉放置来实现，诸如铜引线接合工艺。引线接合工艺的使用可以消除对沉积晶种层、沉积并图案化光刻胶以及形成通孔310的电镀的需求。
根据一些实施例，图3示出了将集成电路管芯310附接至背侧介电层104。在一些实施例中，集成电路管芯310可以通过粘合剂312(诸如管芯粘合薄膜(DAF))粘附于背侧介电层104。粘合剂312的厚度在约10μm到约30μm的范围内。集成电路管芯310可以是如图3所示的单个管芯，或在一些实施例中，可以附接两个或两个以上的管芯，并且可以包括适合特定方法的任何管芯。例如，集成电路管芯310可以包括静态随机存取存储器(SRAM)芯片或动态随机存取存储器(DRAM)芯片、处理器、存储芯片、逻辑芯片、模拟芯片、数字芯片、中央处理单元(CPU)、图形处理单元(GPU)或它们的组合等。集成电路管芯310可以附接至适合的位置以用于特定的设计或应用。例如，图3示出了一个实施例，其中，集成电路310安装在中心区域，其中，通孔206是定位在周界周围。在其他实施例中，集成电路管芯310可以从中心偏移。在附接至背侧介电层104之前，可以根据适用的制造工艺处理集成电路管芯310以在集成电路管芯310中形成集成电路。
在一些实施例中，集成电路管芯310安装至背侧介电层104上使得管芯接触件314背向或远离背侧介电层104。管芯接触件314提供至形成在集成电路管芯310上的电路系统的电连接。管芯接触件314可以形成在集成电路管芯310的有源侧上，或者可以形成在背侧上并且包括通孔。管芯接触件314可以进一步包括在集成电路管芯310的第一侧和第二侧之间提供电连接的通孔。在一个实施例中，管芯接触件314的导电材料是铜、钨、铝、银、金、锡、它们的组合等。
根据一些实施例，图4示出了由密封材料416密封集成电路管芯310和通孔206。在一些实施例中，封装工艺是晶圆级模塑工艺。例如，分配密封材料416以填充集成电路管芯310和通孔206之间间隙。密封材料416可以包括诸如模塑料、环氧树脂、聚合物、模制底部填充物等任何合适的材料。用于形成密封材料416的合适的方法可以包括压缩模塑、传递模塑法、液体密封剂模塑等。例如，密封材料416可以以液体形式分布在集成电路管芯310和通孔206之间。随后，执行固化工艺以固化密封材料416。
在一些实施例中，形成密封材料416以覆盖通孔206和/或管芯接触件314。在这些实施例中，可以使用机械研磨、化学机械抛光(CMP)或其他回蚀技术以去除密封材料416多余的部分并且暴露集成电路管芯310的管芯接触件314。平坦化之后，密封材料416的顶面、集成电路管芯310和通孔206基本水平。
图5示出了根据一些实施例的正侧再分布结构518的形成。通常地，正侧再分布结构518包括一个或多个再分布层(RDL)并且提供将要形成的导电图案以允许完整封装的引脚(pin-out)接触图案，其不同于通孔206和管芯接触件314的图案，允许通孔206和集成电路管芯310的布局更加灵活。可以利用RDL以提供至集成电路管芯310和/或至通孔206的外部电连接。RDL可以进一步用于将集成电路管芯310电连接至通孔206，可以电连接至一个或多个其他封装件、封装衬底、组件等或它们的组合。示出的正侧再分布结构518中的金属化层的数量仅用于说明的目的而不是限制。正侧再分布结构518可以包括任意数量的介电层、金属化图案和通孔。例如，图5所示的实施例中，再分布结构518包括具有各自的金属化图案和通孔的三个介电层520a、520b、520c，如下文所述，三个介电层520a、520b、520c统称为正侧介电层520。
在密封材料416和集成电路管芯310上形成第一介电层520a。在一些实施例中，第一介电层520a由聚合物形成，聚合物可以是使用光刻图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。在其他实施例中，第一介电层520a由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等形成。可以通过旋涂、层压、CVD等或它们的组合形成第一介电层520a。然后图案化第一介电层520a形成开口，从而暴露管芯连接件314和通孔206的部分。在实施例中，第一介电层520a由光敏材料形成，可以通过按照所需的图案暴露第一介电层520a来执行图案化以去除多余的材料，从而暴露管芯接接触件314和通孔206的部分。其他方法，诸如使用图案化的掩模和蚀刻，也可以用于图案化第一介电层520a。
第一金属化图案522a形成在第一介电层520a上并且与暴露的管芯接触件314和通孔206电接触。以形成第一金属化图案522a为例，在形成在第一介电层522a上方和第一介电层522a中的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。然后根据期望的再分布图案在晶种层上形成并图案化掩模。在一些实施例中，掩模是通过旋涂等形成的并且暴露于光以用于图案化。掩模的图案对应于第一金属化图案522a。图案化形成穿过掩模的开口以暴露晶种层。在掩模的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成第一金属化图案522a。第二介电层520b形成在第一介电层522a上方以为后续层提供更平坦的表面，并且可以使用类似于用作形成第一介电层520a材料和工艺来形成第二介电层520b。在一些实施例中，第二介电层520b由聚合物、氮化物、氧化物等形成。在一些实施例中，第二介电层520b是通过旋涂工艺形成的PBO。
在介电层520b和第一金属化图案522a上形成第三介电层522c和第二金属化图案522b。第三介电层522c和第二金属化图案522b可以使用如上所述的用于形成第一介电层520a和第一金属化图案522a的类似工艺和类似材料形成。正侧介电层520中的开口形成以互连相邻的金属化层的通孔，诸如互接第一金属化图案522a和通孔206/管芯接触件314，以及互接第一金属化图案522a和第二金属化图案522b。
图5进一步示出了根据一些实施例的在最上面的金属化图案的上方形成钝化层524。钝化层524可以由聚合物形成，聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中，钝化层524由诸如氮化硅、氧化硅、PSG、BSG、BPSG等的氮化物或氧化物形成。可以通过旋涂、层压、CVD等或它们的组合形成钝化层524。然后图案化钝化层524以暴露部分底层金属化层，例如，第二金属化图案522b。可以通过可接受的工艺进行图案化，诸如当介电层是光敏材料时通过将钝化层524暴露于光或者例如通过使用各向异性蚀刻的蚀刻。单层钝化层524是用于说明的目的而示出的，并且在其他实施例中，可以使用多个钝化层。
图5也示出了凸块下金属(UBM)526，在钝化层524上方并且穿过钝化层524形成以及图案化凸块下金属(UBM)526，因此形成了与最上面金属化层(例如，图5所示的实施例中的第二金属化层522b)的电连接。凸块下金属526提供了电连接，可以在凸块下金属526上面放置电连接件(例如，焊球/凸块、导电支柱等)。在实施例中，凸块下金属526包括扩散阻挡层、晶种层或它们的组合。扩散阻挡层可以包括Ti、TiN、Ta、TaN或它们的组合。晶种层可以包括铜或铜合金。然而，其他金属，诸如镍、钯、银、金、铝、他们的组合以及它们的多层也可以包括在内。在实施例中，使用溅射形成凸块下金属526。在其他实施例中，可以使用电镀。
根据一些实施例，在凸块下金属526上方形成连接件528。连接件528可以是焊球、金属支柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块、它们的组合(例如，具有附接的焊球的金属支柱)等。连接件528可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，如实例，连接件528包括共晶材料并且可以包括焊料凸块或焊球。例如，焊料材料可以是例如，含铅和无铅焊料，诸如用于含铅焊料的Pb-Sn组分；包括InSb的无铅焊料；锡、银和铜(SAC)组分；以及具有共同熔点并且在电气应用中形成导电焊料连接件的其它共晶材料。如实例，对于无铅焊料，可以使用不同组分的SAC焊料，诸如SAC105(锡98.5％、银1.0％、铜0.5％)、SAC305和SAC405。诸如焊球的无铅连接件也可以由锡铜(SnCu)化合物形成，而不使用银(Ag)。可选地，无铅焊料连接件可以包括锡和银、Sn-Ag，不使用铜。连接件528可以形成栅格，诸如球栅格阵列(BGA)。在一些实施例中，可以执行回流工艺，在一些实施例中给出局部球形形状的连接件528。可选地，连接件528可以包括其他形状。例如，连接件528也可以包括非球形导电连接件。
在一些实施例中，连接件528包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属支柱(诸如铜支柱)，在连接件528上具有或不具有焊料材料。金属支柱可以无焊料并且具有基本垂直的侧壁或锥形的侧壁。
简化正侧再分布结构518以用于说明的目的。例如，尽管可以使用正侧再分布结构518以提供至任何通孔206和管芯接触件314的外部电连接，以及将相应的通孔206连接至相应的管芯接触接触件314，为了说明的目的，但是示出了仅从通孔206延伸的导线。
根据一些实施例，图6示出了去除载体衬底100和释放层102(参照图5)以暴露背侧介电材料104。在一些实施例中，去接合包括将诸如激光或UV光的光投射到释放层102上，从而使得释放层102在光的热量下分解，并且载体衬底100可以被去除。在另一个实施例中，可以使用热工艺、化学剥离工艺、激光去除、UV处理等或它们的组合。
分离载体衬底100之后，可以使用清洗工艺以去除释放层102的残留物。在使用LTHC薄膜作为释放层102的实施例中，可以使用等离子体清洗工艺去除LTHC残留物。例如，在一些实施例中，等离子体清洗工艺使用Ar、N2、CF4、O2等作为工艺气体。载体衬底100和释放层102的去接合之后，暴露背侧介电层104。
在一些实施例中，可能需要额外的支撑。在这种情况下，在去除载体衬底100之前，第二载体衬底(未示出)可以附接至钝化层524和/或连接件528。例如，可以使用诸如UV粘合剂的粘合剂来粘附第二载体衬底。
根据一些实施例，图7示出了去除背侧介电层104。通常，如果电接触至通孔206和/或集成电路管芯310(诸如翻转集成电路管芯定位或集成电路管芯包括通孔的情况下)，然后去除背侧介电层104的至少部分。已经发现，穿过背侧介电层104的激光钻孔开口可能损坏通孔并且包括许多额外的工艺步骤。根据在此公开的一些实施例，不需要激光钻孔工艺以暴露通孔206，因此减小和/或防止了不必要的损坏。
在一些实施例中，例如，使用Ar、N2、CF4、O2等的干蚀刻工艺去除背侧介电层104。
根据一些实施例，图8示出了背侧连接件830的形成。背侧介电层104去除之后，背侧连接件830可以直接形成在通孔206上。可以使用与正侧连接件528类似的工艺和材料形成背侧连接件830。
根据一些实施例，图9示出了将图8所示结构附接至第一衬底923和第二衬底934。每个第一衬底932和第二衬底934可以是任何衬底，诸如集成电路管芯、封装件、印刷电路板、插入器等。例如，图9所示的实施例中，第一衬底923包括印刷电路板或插入器，以及第二衬底934包括其他封装件。
根据一些实施例，图9也示出了插入第二衬底934和模塑密封材料416之间的模塑底部填充936。在一些实施例中，例如，模塑底部填充是聚合物、环氧树脂等。模塑底部填充保护背侧连接件830免受外部环境的影响并且可以提供额外的支撑。在一些实施例中，模塑底部填充936可以沿着如图9所示的第二衬底934的侧壁延伸。在一些实施例中，模塑底部填充936可以不沿着第二衬底934的侧壁延伸。尽管未示出，围绕正侧连接件，可以在第一衬底932和钝化层524之间形成模塑底部填充。
为了说明的目的，已经简化了在此提供的附图并且可以执行其他工艺。例如，图中示出的结构可以代表更大的类晶圆结构的单个3DIC封装区域。在一些实施例中，载体衬底100可以是晶圆并且集成电路管芯可以是形成在晶圆上的多个管芯区域中一个。第二衬底934可以是附接至单独的管芯区域的多个衬底中的一个并且模塑底部填充936可以形成在管芯区域上方。此后，执行分割工艺以将单独的管芯区域分成如图9所示的独自的3DIC结构。
图10至图12示出了根据一些额外的实施例的在形成半导体封装件中的中间步骤的截面图。图10至图12示出的很多结构可以使用类似于如上参考图1至图9所讨论的工艺和材料形成，其中，相同的参考符号指的是类似的元件，因此，在此将不重复描述这些元件。图10至图12所示的实施例采取如上参考图1至图6讨论的已经执行过的工艺。因此，在此公开的方法包括图1至图6所示的工艺以及随后的图10至图12所示的工艺。
现在参考图10，根据一些实施例，去除背侧介电层104(参照图6)并且使密封材料416凹进。如上面所讨论的，参考图7，去除背侧介电层104使得使密封材料416不凹进。图10示出了使密封材料416凹进的实施例，因此，导致通孔206突出于密封材料416的表面或在密封材料416的表面之上延伸，使得暴露通孔206的侧壁的一部分。
在一些实施例中，例如，使用过蚀刻工艺去除背侧介电层104和使密封材料416凹进。例如，在一些实施例中，以如上参考图7所讨论的具有较长蚀刻时间的类似方式去除背侧介电层104。蚀刻工艺是选择性的，使得通孔206发生很小或没有发生蚀刻，而较长的蚀刻时间允许蚀刻工艺继续蚀刻并且凹进密封材料416。
在一些实施例中，使密封材料416凹进等于或大于2μm的深度D1。通过使密封材料416凹进并且通过这样的距离暴露通孔206的侧壁，在通孔206上方随后形成的背侧连接件830(例如，焊料)可以沿着通孔206的侧壁延伸，增加接触表面面积。在一些实施例中，在焊料和通孔206之间增加的接触面积可以增加可靠性。
现在参考图11，根据一些实施例示出了背侧连接件830的形成。可以使用如上参考图5所述的和正侧连接件528类似的工艺和材料形成背侧连接件。
根据一些实施例，图12示出了将图11所示的结构附接至第一衬底932和第二衬底934。每个第一衬底932和第二衬底934可以是任何衬底，诸如集成电路管芯、封装件、印刷电路板、插入器等。例如，图12所示的实施例中，第一衬底932包括印刷电路板或插入器，以及第二衬底934包括其他封装件。
根据一些实施例，图12也示出了插入在第二衬底934和模塑密封材料416之间的模塑底部填充936。在一些实施例中，例如，模塑底部填充936是聚合物、环氧树脂等。模塑底部填充936保护背侧连接件830免受外部环境的影响并且可以提供额外的支撑。在一些实施例中，模塑底部填充936可以沿着如图12所示的第二衬底934的侧壁延伸。在一些实施例中，模塑底部填充936可以不沿着第二衬底934的侧壁延伸。尽管未示出，围绕正侧连接件，也可以在第一衬底932和钝化层524之间形成模塑底部填充。
通过过蚀刻的密封材料416的凹进也可以使密封材料416的表面变粗糙。密封材料416的粗糙表面可以增加密封材料和模塑底部填充936之间的接合，因此，减小或者防止分层问题。
图13至图20示出了根据一些额外的实施例的在形成半导体封装件中的中间步骤的截面图。图13至图20示出的很多结构可以使用类似于如上参考图1至图12所讨论的工艺和材料形成，其中，相同的参考符号是指类似的元件，因此，在此将不重复描述这些元件。
首先参考图13，图13示出了具有释放层102以及在其上形成的背侧介电层104的载体衬底100。可以使用如上参考图1所述的类似工艺和类似材料形成载体衬底100、释放层102和背侧介电层104。如图13所示，图案化背侧介电层104以在其中形成开口1340。而上面参考图1至图2所讨论的实施例利用具有相对平坦的表面的通孔，如下面更详细的讨论，开口1340将用于形成通孔，通孔具有从通孔的端部延伸的一个或多个凸出物。
在背侧介电材料104由诸如PBO的感光材料形成的实施例中，通过根据凸出物的期望图案暴露背侧介电层104并且对应凸出物的位置显影背侧介电层104以去除部分背侧介电层104来图案化背侧介电层104。在一些实施例中，背侧介电层104具有约1μm至约10μm的厚度，诸如约7μm。如下将更详细的讨论，随后将在背侧介电层104上方形成通孔，其中，开口1340对应通孔凸出物。约7μm的厚度提供了形成通孔凸出物(例如，锥形侧壁)的足够厚度，以及为过蚀刻工艺提供足够的工艺窗口以暴露通孔凸出物的部分侧壁。
图14至图18分别示出了类似于如上参考图2至图6所讨论的后续工艺。如图14所示，通孔206包括通孔凸出物1442，对应图13所示的开口1340。通孔206和通孔凸出物1442可以使用如上讨论的类似工艺和材料形成。例如，可以在背侧介电层104的上方和沿着开口1340的侧壁和底部形成晶种层(未示出)。在晶种层上方形成图案化的掩模(未示出)，其中，图案化的掩模的开口对应通孔206的位置。在开口中形成导电材料，去除图案化的掩模，并且去除晶种层多余的材料，形成如图14所示的具有通孔凸出物1442的通孔206。
图18示出了执行如上参考图2至图6讨论的包括去除载体衬底100和释放层102的工艺之后的结构。在一些实施例中，保留背侧介电层104使得背侧介电层104的表面和通孔凸出物1442相对平坦，允许在相同释放层102上形成通孔206和背侧介电层104的工艺变化。
此后，如图19至图20所示，可以分别执行类似于如上参考图8和图9所述的工艺，以形成将结构附接至其他衬底(例如，第一衬底932和/或第二衬底934)的背侧连接件830，并且形成模塑底部填充936。在一些实施例中，如图20所示，背侧连接件830直接接触通孔凸出物1442。在一些实施例中，可以在第二衬底934上提供背侧连接件830并且然后附接至通孔凸出物1442。
图21至图23示出了根据一些实施例的在形成半导体封装件中的中间步骤的截面图。图21至图23采用如上参考图13至图18所述的先前执行过的工艺，其中，类似的参考符号指的是类似元件。首先，参考图21，图21示出了在执行凹进工艺以使背侧介电层104凹进从而暴露通孔凸出物1442的至少部分侧壁之后的图18的结构。例如，可以使用Ar、N2、CF4、O2等来使用干蚀刻工艺执行凹进工艺。凹进工艺可能导致暴露通孔凸出物1442的侧壁，为随后形成的背侧连接件830增加湿润表面。在一些实施例中，使背侧介电层104凹进使得通孔凸出物1442突出大于约2μm的距离D1。
通过使背侧介电层104凹进以及暴露通孔凸出物1442的侧壁诸如D1的距离，随后在通孔凸出物1442上方形成的背侧连接件830(例如，焊料)可以沿着通孔凸出物1442和/或通孔206的侧壁延伸，增加接触表面面积。在一些实施例中，在焊料与通孔凸出物1442和/或通孔206之间增加的接触面积可以增加可靠性。
此后，如图22和图23所示，可以分别执行类似于如上参考图19和图20所述的工艺，以形成将结构接合至其他衬底(例如，第一衬底932和/或第二衬底934)的背侧连接件830，并且形成模塑底部填充936。在一些实施例中，模塑底部填充936可以不沿着第二衬底934的侧壁延伸。在一些实施例中，如图22所示，背侧连接件830直接位于通孔凸出物1442上。尽管未示出，围绕正侧连接件，也可以在第一衬底932和钝化层524之间形成模塑底部填充。
图24至图29示出了根据一些实施例的在形成半导体封装件中的中间步骤的截面图。下面将更详细的解释，将使用牺牲层以助于形成具有一个或多个通孔凸出物的通孔的工艺，类似于如上参考图21至图23讨论的结构。首先参考图24，使用类似的工艺和类似的材料以形成类似于如上参考图13讨论的结构，在形成背侧介电层104之前，该结构具有在释放层102上方形成的牺牲背侧介电层2450的额外部件，其中类似的参考符号指的是类似的元件。
在一些实施例中，牺牲背侧介电层2450可以是聚合物(诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等)、氮化物(诸如氮化硅等)、氧化物(诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)或它们的组合等)等，以及可以通过例如旋转涂覆、层压、化学汽相沉积(CVD)等形成牺牲背侧介电层2450。在一些实施例中，牺牲背侧介电层2450是已经在表面涂覆并且显影的光刻胶材料(例如PBO)。在一些实施例中，牺牲层2450具有约2μm的厚度。
此后，在牺牲背侧介电层2450上方形成并且图案化背侧介电层104。在一些实施例中，如图24所示，背侧介电层104是已经被涂覆、曝光并且显影以形成开口1340的光刻胶材料(例如PBO)。因为牺牲背侧介电层2450已经固化，所以在背侧介电层104的图案化期间保留牺牲背侧介电层2450。在一些实施例中，背侧介电层104具有约1μm至约10μm的厚度，诸如约7μm。如下将更详细的讨论，随后，在背侧介电层104上方形成通孔，其中，开口1340对应通孔凸出物。约7μm的厚度提供形成通孔凸出物(例如，锥形侧壁)的足够的厚度，同时为过蚀刻工艺提供足够的工艺窗口以暴露通孔凸出物的部分侧壁。
图25至图28分别示出了与如上参考图14至图17讨论的那些工艺类似的工艺，其中，除了存在牺牲背侧介电层2450，类似的参考符号指的是类似的元件。如图29所示，在去除载体衬底100和释放层102之后，可以去除牺牲背侧介电层2450。在一些实施例中，由类似于背侧介电层104的材料形成牺牲背侧介电层2450，并且由类似于如上参考图21讨论的背侧介电层104的方式去除牺牲背侧介电层2450。例如，可以执行使用干蚀刻工艺去除牺牲背侧介电层2450，干蚀刻工艺使用例如，Ar、N2、CF4、O2等。可以控制去除工艺过蚀刻使得背侧介电层104凹进低于通孔凸出物1442的表面，使得暴露通孔1442的部分侧壁。在一些实施例中，使背侧介电层104凹进使得通孔凸出物1442突出等于或大于约2μm的距离D2。通过使背侧介电层104凹进以及暴露通孔凸出物1442的侧壁诸如D2的距离，随后，在通孔凸出物1442上方形成的背侧连接件830(例如，焊料)可以沿着通孔凸出物1442和/或通孔206的侧壁延伸，增加接触表面面积。在一些实施例中，在焊料与通孔凸出物1442和/或通孔206之间增加的接触面积可以增加可靠性。
此后，如图30和图31所示，可以分别执行类似于如上参考图19和图20所述的工艺，以形成将结构接合至其他衬底(例如，第一衬底932和/或第二衬底934)的背侧连接件830，并且形成模塑底部填充936。在一些实施例中，模塑底部填充936可以不沿着第二衬底934的侧壁延伸。尽管未示出，围绕正侧连接件，也可以在第一衬底932和钝化层524之间形成模塑底部填充。在一些实施例中，如图31所示，背侧连接件830直接位于通孔凸出物1442上并且沿着通孔凸出物1442的侧壁延伸。
图32至图40示出了根据一些实施例的在形成半导体封装件中的中间步骤的截面图。如上所述，在去除载体衬底100之后暴露通孔206。在一些实施例中，在形成通孔206之前，在背侧介电层104上方形成背侧再分布结构。因此，图32至图40示出的具有背侧再分布结构的实施例类似于如上参考图24至图31所述的实施例。
首先参考图32，图32示出了类似于图24所示的实施例，其中，类似的参考符号指的是类似的元件。背侧介电层104中的开口1340对应于图24中的通孔凸出物1442，图32中的背侧介电层104中的开口1340对应于最外层的背侧再分布层。在一些实施例中，背侧介电层104具有约1μm至约10μm的厚度，诸如约7μm。这样的厚度为导电层和工艺窗口提供足够的厚度以在后续的步骤中部分地暴露背侧介电层104的侧壁。
图33示出了背侧再分布结构3160，背侧再分布结构3160包括形成在第一背侧介电层3164和第二背侧介电层3166中的第一背侧金属化层3162。可以使用如上参考图5所述的用于形成正侧再分布结构518所使用的类似工艺和材料形成背侧再分布结构3160。
图34至图40分别示出了类似于如上参考图25至图31讨论的工艺，其中，类似的参考符号指的是类似的元件。在去除载体衬底100和释放层102之后，可以去除牺牲背侧介电层2450。在一些实施例中，由类似于第一背侧介电层3164的材料形成牺牲背侧介电层2450，并且由类似于如上参考图29讨论的与背侧介电层104类似的方式去除牺牲背侧介电层2450。例如，可以使用干蚀刻工艺执行去除牺牲背侧介电层2450，例如，干蚀刻工艺使用Ar、N2、CF4、O2等。可以控制去除工艺以过蚀刻使得第一背侧介电层3164凹进低于第一背侧金属化层3162的表面，使得暴露第一背侧金属化层3162的至少部分侧壁。
在一些实施例中，使第一背侧介电层3164凹进等于或大于2μm的深度D3。通过使第一背侧介电层3164凹进以及暴露第一背侧金属化层3162的侧壁诸如D2的距离，随后在第一背侧金属化层3162上方形成的背侧连接件830(例如，焊料)可以沿着第一背侧金属化层3162的侧壁延伸，增加接触表面面积。在一些实施例中，在焊料和第一背侧金属化层3162之间增加的接触面积可以增加可靠性。
此后，如图39和图40所示，可以分别执行类似于如上参考图30和图31所述的工艺，以形成将结构接合至其他衬底(例如，第一衬底932和/或第二衬底934)背侧连接件830，并且形成模塑底部填充936。在一些实施例中，如图40所示，背侧连接件830直接位于第一背侧金属化层3162上并且沿着第一背侧金属化层3162的侧壁延伸。
图39和图40也示出了一个或多个迹线，诸如也可以暴露迹线3970。迹线3970表示形成在第一背侧金属化层3162中并且可以连接一个或多个背侧连接件的迹线(例如，出入页面的迹线)。如图40所示，迹线3970暴露的部分可以被模塑底部填充936覆盖，保护迹线3970免受外部环境的影响。在一些实施例中，模塑底部填充936可以不沿着第二衬底934的侧壁延伸。尽管未示出，围绕正侧连接件，也可以在第一衬底932和钝化层524之间形成模塑底部填充。
在一些实施例中，提供了一种制造半导体器件的方法。该方法包括：在载体衬底上方形成第一层和以及在第一层上方形成通孔。在第一层上方放置集成电路管芯，并且在第一层上方形成模塑料使得模塑料沿着集成电路管芯和通孔的侧壁延伸。在去除载体衬底之后，完全去除第一层。
在一些实施例中，提供了一种制造半导体器件的方法。该方法包括：在载体衬底上方形成第一层，第一层具有开口，并且在第一层上形成通孔，通孔延伸至开口内。在第一层上方放置集成电路管芯，以及在第一层上方形成模塑料，模塑料沿着集成电路管芯和通孔的侧壁延伸。在集成电路管芯和通孔上方形成再分布层。在去除载体衬底之后，暴露并且凹进第一层使得通孔从第一层突出。
在一些实施例中，提供了一种半导体器件。半导体器件包括具有正侧和背侧的集成电路管芯。模塑料邻近集成电路管芯的侧壁。第一层在模塑料、通孔上方延伸，通孔具有延伸穿过第一层的通孔凸出物。
根据本发明的一个实施例，提供了一种制造半导体器件的方法，所述方法包括：在载体衬底上方形成第一层；在所述第一层上形成通孔；在所述第一层上方放置集成电路管芯；在所述第一层上方形成模塑料，所述模塑料沿着所述集成电路管芯和所述通孔的侧壁延伸；去除所述载体衬底，暴露所述第一层；以及完全去除所述第一层，因此暴露所述通孔。
在上述方法中，进一步包括，使所述模塑料凹进使得所述通孔从所述模塑料的表面突出第一距离。
在上述方法中，所述第一距离等于或大于2μm。
在上述方法中，进一步包括，在去除所述载体衬底之前，在所述集成电路管芯和所述通孔上方形成再分布层。
在上述方法中，进一步包括，在形成所述通孔之前，在所述第一层上方形成第二层。
在上述方法中，所述通孔包括通孔凸出物，所述通孔凸出物延伸穿过所述第二层。
在上述方法中，进一步包括，使所述第二层凹进使得所述通孔凸出物从所述第二层的表面突出。
在上述方法中，所述通孔凸出物从所述第二层的所述表面突出等于或大于2μm的距离。
根据本发明的另一实施例，还提供了一种制造半导体器件的方法，所述方法包括：在载体衬底上方形成第一层，所述第一层具有开口；在所述第一层上形成通孔，所述通孔具有延伸至所述开口内的通孔凸出物；在所述第一层上方放置集成电路管芯；在所述第一层上方形成模塑料，所述模塑料沿着所述集成电路管芯和所述通孔的侧壁延伸；在所述集成电路管芯和所述通孔上方形成再分布层；去除所述载体衬底，暴露所述第一层；以及使所述第一层凹进使得所述通孔从所述第一层突出。
在上述方法中，进一步包括，在去除所述载体衬底之前，在所述集成电路管芯和所述通孔上方形成再分布层。
在上述方法中，进一步包括形成牺牲层，在所述牺牲层上形成所述第一层。
在上述方法中，进一步包括完全去除所述牺牲层。
在上述方法中，所述通孔从所述第一层突出等于或大于2μm的距离。
在上述方法中，所述通孔凸出物的宽度小于所述通孔的延伸穿过所述模塑料的宽度。
在上述方法中，形成所述第一层包括形成多个介电层以及在相邻的所述介电层之间形成金属化层。
在上述方法中，所述凹进暴露从接合焊盘沿着所述第一层延伸的迹线。
根据本发明的又另一实施例，还提供了一种半导体器件，包括：集成电路管芯，所述集成电路管芯具有正侧和背侧；模塑料，邻近所述集成电路管芯的侧壁；以及第一层，在所述模塑料上方、具有延伸穿过所述第一层的通孔凸出物的通孔上方延伸。
在上述半导体器件中，所述通孔凸出物具有小于所述通孔的延伸穿过所述模塑料的宽度的宽度。
在上述半导体器件中，所述通孔凸出物从所述第一层突出。
在上述半导体器件中，所述通孔凸出物从所述第一层突出等于或大于2μm的距离。
以上论述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域的技术人员应该理解，他们可以容易地使用本发明作为用于设计或修改用于执行与本发明相同或类似的目的和/或实现相同或类似优点的其它工艺和结构的基础。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，所述方法包括：
在载体衬底上方形成第一层；
在所述第一层上形成通孔；
在所述第一层上方放置集成电路管芯；
在所述第一层上方形成模塑料，所述模塑料沿着所述集成电路管芯和所述通孔的侧壁延伸；
去除所述载体衬底，暴露所述第一层；以及
完全去除所述第一层，因此暴露所述通孔。
2.根据权利要求1所述的方法，进一步包括，使所述模塑料凹进使得所述通孔从所述模塑料的表面突出第一距离。
3.根据权利要求2所述的方法，其中，所述第一距离等于或大于2μm。
4.根据权利要求1所述的方法，进一步包括，在去除所述载体衬底之前，在所述集成电路管芯和所述通孔上方形成再分布层。
5.根据权利要求1所述的方法，进一步包括，在形成所述通孔之前，在所述第一层上方形成第二层。
6.根据权利要求5所述的方法，其中，所述通孔包括通孔凸出物，所述通孔凸出物延伸穿过所述第二层。
7.根据权利要求6所述的方法，进一步包括，使所述第二层凹进使得所述通孔凸出物从所述第二层的表面突出。
8.根据权利要求7所述的方法，其中，所述通孔凸出物从所述第二层的所述表面突出等于或大于2μm的距离。
9.一种制造半导体器件的方法，所述方法包括：
在载体衬底上方形成第一层，所述第一层具有开口；
在所述第一层上形成通孔，所述通孔具有延伸至所述开口内的通孔凸出物；
在所述第一层上方放置集成电路管芯；
在所述第一层上方形成模塑料，所述模塑料沿着所述集成电路管芯和所述通孔的侧壁延伸；
在所述集成电路管芯和所述通孔上方形成再分布层；
去除所述载体衬底，暴露所述第一层；以及
使所述第一层凹进使得所述通孔从所述第一层突出。
10.一种半导体器件，包括：
集成电路管芯，所述集成电路管芯具有正侧和背侧；
模塑料，邻近所述集成电路管芯的侧壁；以及
第一层，在所述模塑料上方、具有延伸穿过所述第一层的通孔凸出物的通孔上方延伸。
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