CN105679741A - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN105679741A
CN105679741A CN201510656984.3A CN201510656984A CN105679741A CN 105679741 A CN105679741 A CN 105679741A CN 201510656984 A CN201510656984 A CN 201510656984A CN 105679741 A CN105679741 A CN 105679741A
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China
Prior art keywords
layer
hole
opening
crystal seed
carrier substrates
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CN201510656984.3A
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CN105679741B (zh
Inventor
余振华
刘重希
林志伟
郑明达
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了一种半导体器件和用于形成半导体器件的方法。半导体器件包括：具有邻近集成电路管芯的通孔的集成电路，其中，模塑料置于集成电路管芯和通孔之间。通孔具有延伸穿过图案化层的突出件，并且通孔可以从图案化层的表面偏移。通过选择性地去除晶种层可以形成凹槽，其中，晶种层用于形成通孔。本发明涉及半导体封装件及其形成方法。

Description

半导体封装件及其形成方法
相关申请的交叉引用
本申请要求于2014年12月3日提交的题目为“SemiconductorPackagesandMethodsofFormingtheSame”的美国临时专利申请第62/087,167号的优先权和益处，其全部内容通过引用结合于此，作为参考。
技术领域
本发明涉及半导体封装件及其形成方法。
背景技术
半导体器件用于各种电子应用中，诸如个人计算机、手机、数码相机、以及其他电子设备。通常通过在半导体衬底上方依次沉积绝缘层或介电层、导电层和半导体材料层并且使用光刻以图案化各个材料层以在其上形成电路组件和元件来制造半导体器件。通常在单个半导体晶圆上制造几十个或数百个集成电路。通过沿着划线锯切集成电路来分割单独的管芯。然后将单独的管芯以多芯片模式或以其他封装类型分别地封装。
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度不断提高，半导体产业经历了快速的发展。在大多数情况下，这种集成密度的提高源自最小部件尺寸的不断减小(例如，将半导体工艺节点向着亚20nm节点缩减)，这使得更多的组件集成至给定的区域内。随着近来对微型化、更高速度、更大带宽以及更低功耗和延迟的要求的提高，对半导体管芯的更小和更具创造性的封装技术的需要也不断增加。
随着半导体技术的进一步发展，堆叠的半导体器件，例如，三维集成电路(3DIC)已经作为用于进一步降低半导体器件的物理尺寸的有效替代而出现。在堆叠的半导体器件中，在不同的半导体晶圆上制造诸如逻辑电路、存储器电路、处理器电路等的有源电路。两个以上的半导体晶圆可以安装或堆叠在彼此的顶部上以进一步减小半导体器件的形式因数。叠层封装(POP)器件是3DIC的一种类型，其中，封装管芯并且然后将其与另一个或一些封装的管芯封装在一起。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种制造半导体器件的方法，所述方法包括：在载体衬底上方形成第一层；在所述第一层中形成第一开口；在所述第一层上方形成通孔，所述通孔延伸至所述第一开口内；在所述第一层上方放置集成电路；在所述第一层上方形成模塑料，所述模塑料沿着所述集成电路和所述通孔的侧壁延伸；在所述集成电路和所述通孔上形成重分布层；以及去除所述载体衬底。
在上述方法中，还包括：在所述第一开口中形成一个或多个晶种层。
在上述方法中，还包括：在去除所述载体衬底之后，去除所述一个或多个晶种层的至少一个。
在上述方法中，去除所述一个或多个晶种层的至少一个形成了凹槽。
在上述方法中，所述第一开口呈负锥形。
在上述方法中，所述第一开口呈正锥形。
在上述方法中，还包括：在所述重分布层上放置第一焊球和在所述通孔上放置第二焊球。
在上述方法中，还包括：在所述载体衬底上方形成所述第一层之前，在所述载体衬底上方形成牺牲层，其中，所述第一层形成在所述牺牲层上方。
根据本发明的另一方面，还提供了一种制造半导体器件的方法，所述方法包括：在载体衬底上形成第一层；在所述第一层中形成开口；沿着所述开口的侧壁和底部形成一个或多个晶种层；在所述晶种层上形成通孔，所述通孔延伸至所述开口内；在所述第一层上放置集成电路；在所述第一层上形成模塑料，所述模塑料置于所述集成电路和所述通孔之间；以及去除所述载体衬底。
在上述方法中，还包括：在所述载体衬底上方形成所述第一层之前，在所述载体衬底上方形成牺牲层，其中，所述第一层形成在所述牺牲层上方。
在上述方法中，还包括：在去除所述载体衬底之后，去除至少一个晶种层，所述去除形成了凹槽。
在上述方法中，所述凹槽的深度为约0.01μm至约1μm。
在上述方法中，所述凹槽呈负锥形，所述负锥形的负锥角为约5度至约85度。
在上述方法中，所述凹槽呈正锥形，所述正锥形的正锥角为约5度至约85度。
在上述方法中，还包括：在去除所述载体衬底之后，去除至少一个晶种层，所述去除形成了凹槽。
在上述方法中，所述凹槽的深度为约0.01μm至约5μm。
在上述方法中，还包括：在所述通孔上形成焊料接点，所述焊料接点延伸至所述凹槽内。
根据本发明的又一方面，还提供了一种半导体器件，包括：第一层，具有开口；集成电路，位于所述第一层上；密封剂，位于邻近所述集成电路的所述第一层上；以及通孔，延伸穿过所述密封剂，所述通孔延伸至所述开口内，延伸穿过所述密封剂的所述通孔的宽度大于延伸至所述开口内的所述通孔的宽度。
在上述半导体器件中，还包括：一个或多个晶种层，沿着所述开口的侧壁延伸，其中，所述一个或多个晶种层的至少一个不在所述开口中的所述通孔的底面上方延伸。
在上述半导体器件中，所述开口具有锥形侧壁。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有按比例绘制。实际上，为了清楚讨论，各个部件的尺寸可以任意增大或减小。
图1至图16是根据一些实施例的形成半导体器件的各个中间步骤的截面图。
图17A至图17C示出了根据一些实施例的用于通孔的开口轮廓的各个截面图。
图18至图31是根据一些实施例的形成半导体器件的各个中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
将结合具体上下文中的实施例来描述实施例，即，三维(3D)集成扇出(InFO)叠层封装(PoP)器件。然而，其他实施例也可以应用于其他电连接的组件，包括但不限于，叠层封装组件、管芯至管芯组件、晶圆至晶圆组件、管芯至衬底组件、装配封装中、处理衬底中、中介层、衬底等或安装输入组件、板、管芯或其他组件或用于连接封装或安装任何类型的集成电路或电组件的组合。
图1至图16示出了根据一些实施例的形成半导体器件的中间步骤的截面图。图1是载体衬底40的截面图。例如，载体衬底40包括硅基材料，诸如硅晶圆、玻璃或氧化硅，或者诸如氧化铝、陶瓷材料的其他材料、这些材料的任何组合等。在一些实施例中，载体衬底40是平坦的以便适应进一步的处理。在一些实施例中，载体衬底40可以是晶圆，多个封装件结构形成在该晶圆上。载体衬底40可以是为载体衬底40上方的层提供机械支撑(在制造工艺的中间操作期间)的任何合适的衬底。
图2是根据一些实施例的位于载体衬底40上的释放层42的截面图。释放层42可以由聚合物基材料形成，释放层42和载体衬底40可以从将在随后的步骤中形成的上面的结构去除。在一些实施例中，释放层42是环氧基热释放材料，当环氧基热释放材料被加热时而失去其粘合性能，环氧基热释放材料诸如光热转换(LTHC)释放涂层。在其他实施例中，释放层42可以是紫外(UV)胶，当紫外(UV)胶暴露于UV光时，而失去其粘合性能。释放层42可以作为液体分配和固化，其可以是层压至载体衬底40上的层压膜等。
图3是根据一些实施例的位于释放层42上的第一图案化层44的截面图。如将在下面更详细地讨论的，第一图案化层44被图案化为具有开口，在随后的工艺中形成的通孔将在该开口中延伸。第一图案化层44可以是聚合物(诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等)、氮化物(诸如氮化硅等)、氧化物(诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)或它们的组合等)，等并且可以，例如，通过旋涂、层压、化学汽相沉积(CVD)等形成。在一些实施例中，第一图案化层44是光刻胶材料并且通过图案化的掩模将光刻胶材料暴露于光而图案化，从而在光刻胶材料中创建第一开口47。
图4是根据一些实施例的随后在第一图案化层44和部分的释放层42上方形成的通孔的晶种层46的截面图。可以在第一图案层44上方以及第一开口47中形成晶种层46，第一开口47形成在第一图案化层44中。在一些实施例中，晶种层46是金属层，其可以是单层或包括多个由不同的材料形成的子层的复合层。晶种层46可以由铜、钛、镍、金或它们的组合等制成。在一些实施例中，该晶种层46包括钛层和位于钛层上方的铜层。例如，可以使用物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)、它们的组合等形成晶种层46。晶种层46可以包括一层或多层。
如将在下面更详细地讨论的，将利用晶种层46以形成通孔，在形成通孔之后，可以去除晶种层46的部分以形成凹槽。晶种层46的厚度，或者如果利用复合晶种层，则一层或多层复合晶种层可以用于控制从第一图案化层44的底面至通孔50(见图6)的深度。因此，可以选择晶种层46的厚度和材料以帮助控制凹槽。例如，在一些实施例中，晶种层46可以包括钛层和上面的铜层。在该实施例中，可以选择性地去除钛层，从而生成凹槽并且暴露出铜层。在一些实施例中，第一晶种层(例如，钛层)具有约0.01μm至约5μm的厚度，并且第二晶种层(例如，铜层)具有约0.01μm至约5μm的厚度。在其他实施例中，可以利用其他材料。
图5是根据一些实施例的第二图案化层48的截面图，第二图案化层48位于晶种层46上方并且具有第二开口49以暴露出第一开口47的至少部分。可以通过诸如旋涂工艺的湿工艺，或者通过干工艺或者施加干膜来形成第二图案化层48，并且第二图案化层48可以暴露于光以用于图案化。图案化形成穿过第二图案化层48的第二开口49以暴露出晶种层46的部分和第一开口47，并且第二开口49的宽度可以宽于第一开口47的宽度。在一些实施例中，第二图案化层48包括光刻胶层，并且使用光刻技术被图案化。在其他实施例中，可以将诸如氧化硅或氮化硅的其他材料用作第二图案化层48。
图6是根据一些实施例的导电材料填充第二图案化层48的第一开口47(见图3)和第二开口49(见图5)以形成通孔50的截面图，其中，第一开口47(见图3)和第二开口49(见图5)位于晶种层46的暴露部分上。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝或它们的组合等，并且可以具有包括多层的复合结构。如图6所示，通孔50包括具有第一宽度w1的主体部分和具有由于通孔50延伸穿过第一图案化层44的第二宽度w2的狭窄突出件。通孔50包括具有介于第一宽度w1和第二宽度w2之间的宽度w3的凸耳或凹槽。通孔50的第一宽度w1可以在从约20μm至约500μm的范围内，第二宽度w2可以在从约20μm至约500μm的范围内，并且第三宽度w3可以在从约0μm至约100μm的范围内。通孔50的主体部分的第一高度h1可以在从约20μm至约1000μm的范围内，并且通孔50的狭窄突出件的第二高度h2可以在从约0.01μm至约50μm的范围内。
图7是根据一些实施例的在去除第二图案化层48(见图6)之后的通孔50的截面图。在一些实施例中，其中，第二图案化层48包括光刻胶材料，可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除第二图案化层48，并且也可以通过丙酮、异丙醇和去离子水等冲洗来去除第二图案化层48。一旦去除第二图案化层48，则暴露出晶种层46的未被通孔50覆盖的部分。
图8根据一些实施例示出了去除暴露的晶种层46的去除。例如，可以通过使用诸如通过湿或干蚀刻的可接受的蚀刻工艺来去除暴露的晶种层46，从而暴露出第一图案化层44的至少部分。
图9根据一些实施例示出了将集成电路管芯52附接至第一图案化层44。在一些实施例中，集成电路管芯52可以通过诸如管芯附接膜(DAF)的粘合剂54附接至第一图案化层44。粘合剂54的厚度可以在从约0.01μm至约100μm的范围内。集成电路管芯52可以是如图9所示的单个管芯，或者在一些实施例中，可以附接两个以上的管芯，并且其可以包括适用于特定方法的任何管芯。例如，集成电路管芯52可以包括静态随机存取存储器(SRAM)芯片或动态随机存取存储器(DRAM)芯片、处理器、存储器芯片、逻辑芯片、模拟芯片、数字芯片、中央处理单元(CPU)、图形处理单元(GPU)或它们的组合等。集成电路管芯52可以附接至合适的位置以用于特定的设计或应用。例如，图9示出了其中集成电路管芯52安装在中心区域中的实施例，其中，通孔50设置在外围周围。在其他实施例中，集成电路管芯52可以从中心偏移。在附接至第一图案化层44之前，可以根据适用的制造工艺处理集成电路管芯52以在集成电路管芯52中形成集成电路。
在一些实施例中，该集成电路管芯52安装至第一图案化层44，从而使得管芯连接件56面向为远离于第一图案化层44或位于第一图案化层44的远端。该管芯连接件56提供至形成在集成电路管芯52上的电路的电连接。管芯连接件56可以形成在集成电路管芯52的有源侧上或可以形成在背侧上并且包括通孔。管芯连接件56可以进一步包括在集成电路管芯52的第一侧和第二侧之间提供电连接的通孔。在实施例中，管芯连接件56的导电材料是铜、钨、铝、银、金、锡、它们的组合等。
图10根据一些实施例示出了通过密封剂58来密封集成电路管芯52和通孔50。将密封剂58放置在集成电路管芯52之间的间隙中以及通孔50周围。例如，使用压缩模制可以将密封剂58模制在集成电路管芯52和通孔50上。在一些实施例中，密封剂58是由模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合制成的。可以实施固化步骤以固化和凝固密封剂58，其中，固化可以是热固化、UV固化等或它们的组合。可以使用诸如层压、压缩模制等的其他密封工艺。
在一些实施例中，模制材料完全覆盖集成电路管芯52的上表面。在这些实施例中，可以对模制材料58实施诸如研磨的平坦化步骤以暴露出集成电路管芯52和管芯连接件56。在一些实施例中，管芯连接件56的表面和通孔50的表面与模制材料58的表面相平。通孔50可以称为模制通孔(TMV)、封装件通孔(TPV)和/或InFO(集成的扇出)通孔(TIV)。
图11根据一些实施例示出了重分布结构60的形成。重分布结构60可以包括任何数量的介电层、金属化图案和通孔。例如，图11示出了其中重分布结构60包括具有相应的金属化图案和通孔的三个介电层62、64、66的实施例，这将在下文进行论述，但是其他实施例可以具有更多或更少的介电层。
第一介电层62形成在密封剂58和管芯连接件56上。在一些实施例中，第一介电层62是由聚合物形成的，该聚合物可以是诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料，并且可以使用光刻来图案化该光敏材料。在其他实施例中，第一介电层62是由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等形成的。可以通过旋涂、层压、化学汽相沉积(CVD)等或它们的组合形成第一介电层62。然后图案化第一介电层62以形成开口，从而暴露出管芯连接件56和通孔50的部分。可以通过可接受的工艺来实施图案化，诸如当介电层是光敏材料时通过将第一介电层62暴露于光或者通过蚀刻，例如，使用图案化的掩模和各向异性蚀刻。
在第一介电层62上形成具有通孔72的第一金属化图案70。作为用于形成第一金属化图案70和通孔72的实例，在第一介电层62上方以及在开口中形成晶种层(未示出)，其中，开口形成于第一介电层62中。在一些实施例中，该晶种层是金属层，该金属层可以是单层或复合层，复合层包括由不同材料形成的多个子层。在一些实施例中，该晶种层包括钛层和位于钛层上方的铜层。例如，可以使用物理汽相沉积(PVD)等形成晶种层。然后根据所需的重分布图案，在晶种层上形成并且图案化掩模。在一些实施例中，该掩模是通过旋涂等形成的光刻胶并且暴露于光以用于图案化。掩模的图案对应于具有通孔72的第一金属化图案70。图案化形成穿过掩模的开口，以暴露出该晶种层。在掩模的开口中以及在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。然后，去除光刻胶和晶种层的其上没有形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺来去除光刻胶。一旦去除光刻胶，诸如通过使用湿或干蚀刻的可接受的蚀刻工艺，去除晶种层的暴露部分。晶种层和导电材料的剩余部分形成第一金属化图案70和通孔72。在第一介电层62上方形成第二介电层64以为随后的层提供更平坦的表面。在一些实施例中，由聚合物、氮化物、氧化物等形成第二介电层64。在一些实施例中，该第二介电层64是通过旋涂工艺形成的PBO。
在第二介电层64和第一金属化图案70上形成第三介电层66、第二金属化图案68和通孔74。使用与上文论述的用于形成第一介电层62、第一金属化图案70和通孔72的类似的材料和类似的工艺可以形成第三介电层66、第二金属化图案68和通孔74。通孔74互连金属化图案68和70。在第三介电层66上以及第二金属化图案68周围形成第四介电层67。在一些实施例中，第四介电层67是由聚合物形成的，该聚合物可以是可以使用光刻掩模图案化的光敏材料，诸如PBO、聚酰亚胺、BCB等。在其他实施例中，第四介电层67是由诸如氮化硅、氧化硅、PSG、BSG、BPSG等的氮化物或氧化物形成的。可以通过旋涂、层压、CVD等或它们的组合形成第四介电层67。然后，图案化第四介电层67以创建第三开口71。可以通过可接受的工艺来实施图案化，诸如当介电层是光敏材料时通过将第四介电层67暴露于光或者通过蚀刻，例如，使用各向异性蚀刻。
重分布层60可以称为集成电路管芯52上的正侧重分布层。该正侧重分布层60可以用于提供至集成电路管芯52的外部电连接和/或用于将集成电路管芯52电连接至通孔50，该正侧重分布层60电连接至一个或多个其他封装件、封装衬底、组件等或它们的组合。在重分布层60中所示出的金属化层的数量仅仅是用于示出的目的并且不在于限制。可以存在与图11中示出的不同的任意数量的介电层和金属化图案。
图12根据一些实施例示出了在第三开口71(见图11)中的凸块下金属化(UBM)层75的形成。UBM75可以包括多个层，诸如钛层、接下来的铜层以及第三Ni层。在一些实施例中，UBM75可以包括钛(Ti)层、钽(Ta)层和氮化钽(TaN)层。可以通过电镀或化学镀方法图案化UBM焊盘。
图13示出了在UBM75上方的一组导电连接件76的形成，并且导电连接件76电连接至重分布层60。导电连接件76可以是焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍化学镀钯浸金技术(ENEPIG)形成的凸块、它们的组合(例如，具有附接的焊球的金属柱)等。导电连接件76可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在其中导电连接件76是焊料凸块的实施例中，首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等的这些常用的方法来形成焊料层，从而形成导电连接件76。一旦已经在该结构上形成焊料层，则可以实施回流以将该材料成型为期望的凸块形状。在另一实施例中，导电连接件76是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本上垂直的侧壁。
图14根据一些实施例示出了去除载体衬底40和释放层42以暴露出第一图案化层44，以及去除位于通孔50上的晶种层46的一层或多层。在一些实施例中，去接合包括将诸如激光或UV光的光投射在释放层42(见图13)上，从而使得释放层在光的热量下分解并且可以去除载体衬底40。可以实施清洗和/或研磨工艺以去除释放层的残留部分。在另一实施例中，可以使用热处理、化学剥离工艺、激光去除、UV处理等或它们的组合。在载体衬底40和释放层42去接合之后，暴露出一层或多层晶种层46。通过诸如湿或干蚀刻的可接受的蚀刻工艺来去除一层或多层晶种层46。在去除暴露的晶种层之后，然后暴露出通孔50。在一些实施例中，一层或多层晶种层46可以保持在通孔50上方。晶种层46的去除的层的厚度将控制凹槽深度，其中，凹槽深度介于第一图案化层44的在密封剂58远端的表面和晶种层46和/或通孔50的暴露表面之间。下面将参考图17A至图17C来更详细地论述该凹槽。
图15示出了一组导电连接件78在通孔50上方的形成，并且该组导电连接件78电连接到通孔50。导电连接件78可以是焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件78可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合等。在其中导电连接件76是焊料凸块的实施例中，首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等的这些常用的方法来形成焊料层，从而形成导电连接件78。一旦已经在该结构上形成焊料层，则可以实施回流以将该材料成型为期望的凸块形状。在另一实施例中，导电连接件78是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本上垂直的侧壁。导电连接件78的直径可以在从约20μm至约500μm的范围内。
图16根据一些实施例示出了用粘合材料82的额外的粘合支撑将导电连接件78电连接至衬底80。衬底80可以是任何衬底，诸如集成电路管芯、封装件、印刷电路板、中介层等。在一些实施例中，粘合材料82可以是环氧树脂或胶水，并且可以将粘合材料82应用于导电连接件78。在一些实施例中，导电连接件78可以直接附接至通孔50。光或UV光可以用于固化晶圆80和导电连接件78之间的粘合材料82。
在一些实施例中，也可以在导电连接件78和通孔50之间使用UBM结构。UBM结构可以类似于UBM75。
图17A至图17C根据各个实施例示出了如图14所示的凹槽79的各种配置。多层晶种层的使用允许利用晶种层来控制凹槽的深度79。例如，在诸如图17A至图17C示出的实施例中，利用具有第一晶种层83(诸如钛层)和第二晶种层84(诸如铜层)的多层晶种层46。在诸如这些的实施例中，通过依靠第一晶种层83和第二晶种层84的材料之间的蚀刻选择性从而使得第二晶种层84用作用于去除第一晶种层83的蚀刻停止层，第一晶种层83的厚度限定凹槽79的深度。在一些实施例中，第一晶种层83具有厚度并且凹槽79的深度R为约0.01μm至约5μm。在其他实施例中，可以从通孔50的端部去除第一晶种层83和第二晶种层84，从而使得完全去除晶种层46并且暴露出通孔50。
图17A至图17C进一步示出了开口47(见图3)的各个侧壁轮廓。例如，图17A示出了其中通孔50的突出件具有延伸穿过第一图案化层44的基本垂直侧壁的实施例。图17B示出了其中通孔50的突出件具有延伸穿过第一图案化层44的正锥形的实施例，从而使得突出件的宽度随着突出件从通孔50的中心主体向外远离延伸而增加。在实施例中，突出件的侧壁的正锥角(α)为约5度至约85度，正锥形的角度(α)可以在从约500mJ/cm2至约1000mJ/cm2的剂量内调整，并且在光刻工艺期间的聚焦深度为从约5μm至约10μm。
图17C示出了其中通孔50的突出件具有延伸穿过第一图案化层44的负锥形的实施例，从而使得突出件的宽度随着突出件从通孔50的中心主体向外远离延伸而减小。在实施例中，突出件的侧壁具有约5度至约85度的负锥角(β)，负锥形的角度(β)可以在从约100mJ/cm2至约500mJ/cm2的剂量内调整，并且在光刻工艺期间的聚焦深度为从约5μm至约20μm。在特定设计中可以调整通孔50的突出件的锥形以降低应力。
诸如本文中的那些公开的实施例允许制造至通孔50的接触件而无需使用可能会引起更多破坏或提供更少控制的工艺。例如，与穿过介电层的激光钻孔开口以提供至通孔的电接触相反，诸如那些本文中的实施例依靠良好控制的选择性蚀刻工艺，利用第一图案化层44和晶种层结构中的开口以形成至通孔50的凹槽。诸如激光钻孔的技术可以导致对轮廓和临界尺寸的破坏以及提供更少的控制。
图18至图31示出了根据一些实施例的制造封装件结构的各个中间阶段的截面图。在图18至图31中示出的实施例可以利用如以上参考图1至图16和图17A至图17C的论述的许多类似结构和工艺，其中，相同的参考标号用于代表相同的元件，可以使用类似的工艺由类似的材料形成相同的元件。然而，可以利用其它材料和工艺。现参照图18，示出了在释放层42和载体衬底40上形成的牺牲层94，其中，如以上参考图1和图2的描述，一些实施例可以利用载体衬底40和释放层42。如将在下文中论述的，将在载体衬底40上形成结构以及然后，随后去除载体衬底40。牺牲层94在随后的去除载体衬底40和释放层42(例如，见图29)期间提供保护层以保护随后形成的聚合物层44(见图19)。在去除工艺之后，聚合物层44仍然平坦。
在一些实施例中，牺牲层94可以是聚合物层或金属层。例如，聚合物层可以是六甲基二硅氮烷(HMDS)层等，以及例如，金属层可以是钛(Ti)层等。可以通过旋涂来沉积聚合物层，并且可以通过化学汽相沉积(CVD)、物理汽相沉积(PVD)、溅射等来沉积金属层。在一些实施例中，HMDS层的厚度在从约0.01μm至约5μm的范围内。在其他实施例中，牺牲层94是，例如，通过溅射、CVD、PVD等形成的Ti层。Ti层的厚度是在从约0.01μm至约5μm的范围内。
图19至图30示出了后续的各个中间步骤的截面图，分别类似于在图3至图14中示出的那些步骤。可以使用类似的工艺和材料并且本文中不再重复，其中，相同的参考标号代表相同的元件。
现在参考图31，根据一些实施例，示出了去除牺牲层94(见图30)和一层或多层晶种层46。例如，可以通过使用诸如湿或干蚀刻的可接受的蚀刻工艺来去除牺牲层94和一层或多层晶种层46，从而暴露出第一图案化层44和通孔50的至少部分。如以上参考图17A至图17C所论述的，牺牲层94的去除和一层或多层晶种层46的去除暴露出通孔50并且创建了凹槽79。通孔50可以进一步电连接至另一半导体结构。例如，可以通过等离子体灰化、以丙酮冲洗、异丙醇冲洗等去除HMDS层。可以通过湿蚀刻或干蚀刻去除Ti层。之后，可以实施后续处理。例如，可以实施诸如以上参考图15和图16论述的处理以形成导电连接件78(见图15)和使用导电连接件78和粘合材料料82(见图16)以连接衬底80。可以使用与图15和图16类似的工艺和材料并且本文中不再重复。
在一些实施例中，提供了一种制造半导体器件的方法。该方法包括在载体衬底上方形成第一层和在第一层中形成第一开口。在第一层上方形成通孔，从而使得通孔延伸至第一开口内。在第一层上方放置集成电路，并且在第一层上方形成模塑料，模塑料沿着集成电路和通孔的侧壁延伸。可以在集成电路和通孔上形成重分布层。去除载体衬底。
在另一个实施例中，提供了一种制造半导体器件的方法。该方法包括在载体衬底上形成第一层和在第一层中形成开口。沿着开口的侧壁和底部形成一个或多个晶种层，在晶种层上方形成通孔，从而通孔延伸至开口内。在第一层上放置集成电路，和在第一层上形成模塑料，模塑料置于集成电路和通孔之间。可以去除载体衬底。
在另一实施例中，提供了一种半导体器件。该半导体器件包括：第一层，具有开口；集成电路，位于第一层上；密封剂，设置在邻近集成电路的第一层上；密封剂具有延伸穿过其中的通孔，通孔延伸至开口内。通孔的延伸穿过密封剂的部分的宽度大于通孔的延伸至开口内的部分。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，所述方法包括：
在载体衬底上方形成第一层；
在所述第一层中形成第一开口；
在所述第一层上方形成通孔，所述通孔延伸至所述第一开口内；
在所述第一层上方放置集成电路；
在所述第一层上方形成模塑料，所述模塑料沿着所述集成电路和所述通孔的侧壁延伸；
在所述集成电路和所述通孔上形成重分布层；以及
去除所述载体衬底。
2.根据权利要求1所述的方法，还包括：在所述第一开口中形成一个或多个晶种层。
3.根据权利要求2所述的方法，还包括：在去除所述载体衬底之后，去除所述一个或多个晶种层的至少一个。
4.根据权利要求2所述的方法，其中，去除所述一个或多个晶种层的至少一个形成了凹槽。
5.根据权利要求4所述的方法，其中，所述第一开口呈负锥形。
6.根据权利要求4所述的方法，其中，所述第一开口呈正锥形。
7.根据权利要求1所述的方法，还包括：在所述重分布层上放置第一焊球和在所述通孔上放置第二焊球。
8.根据权利要求1所述的方法，还包括：在所述载体衬底上方形成所述第一层之前，在所述载体衬底上方形成牺牲层，其中，所述第一层形成在所述牺牲层上方。
9.一种制造半导体器件的方法，所述方法包括：
在载体衬底上形成第一层；
在所述第一层中形成开口；
沿着所述开口的侧壁和底部形成一个或多个晶种层；
在所述晶种层上形成通孔，所述通孔延伸至所述开口内；
在所述第一层上放置集成电路；
在所述第一层上形成模塑料，所述模塑料置于所述集成电路和所述通孔之间；以及
去除所述载体衬底。
10.一种半导体器件，包括：
第一层，具有开口；
集成电路，位于所述第一层上；
密封剂，位于邻近所述集成电路的所述第一层上；以及
通孔，延伸穿过所述密封剂，所述通孔延伸至所述开口内，延伸穿过所述密封剂的所述通孔的宽度大于延伸至所述开口内的所述通孔的宽度。
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US20190311988A1 (en) 2019-10-10
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US20210233854A1 (en) 2021-07-29
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