TWI663699B - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

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TWI663699B
TWI663699B TW106114156A TW106114156A TWI663699B TW I663699 B TWI663699 B TW I663699B TW 106114156 A TW106114156 A TW 106114156A TW 106114156 A TW106114156 A TW 106114156A TW I663699 B TWI663699 B TW I663699B
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Taiwan
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dummy
perforation
dielectric layer
top cover
metal
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TW106114156A
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TW201830639A (zh
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余振華
陳憲偉
李孟燦
林宗澍
吳偉誠
邱建嘉
王景德
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台灣積體電路製造股份有限公司
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Abstract

一種半導體封裝包括第一介電層、元件晶粒、主動穿孔及虛設穿孔、密封材料、第二介電層、主動金屬頂蓋、虛設金屬頂蓋及第一重佈線線路。元件晶粒位於第一介電層之上。密封材料密封元件晶粒、主動穿孔、及虛設穿孔。第二介電層位於元件晶粒、主動穿孔、及虛設穿孔之上。主動金屬頂蓋位於第二介電層之上，並且電性耦合至主動穿孔。主動金屬頂蓋交疊主動穿孔。虛設金屬頂蓋位於第二介電層之上。虛設金屬頂蓋交疊虛設穿孔。虛設金屬頂蓋被間隙分隔成第一部分及第二部分。重佈線線路穿過虛設金屬頂蓋的第一部分與第二部分之間的間隙。

Description

半導體封裝及其形成方法
本發明實施例是有關於一種半導體封裝，且特別是有關於一種半導體封裝及其形成方法。
隨著半導體技術的演進，半導體晶片/晶粒正日漸變小。與此同時，需要在半導體晶粒中整合更多的功能。因此，半導體晶粒需要將越來越多的輸入/輸出（input/output，I/O）墊包裝於更小的區域中，且輸入/輸出墊的密度隨時間而急劇增加。因此，半導體晶粒的封裝變得更加困難，此對封裝的良率造成不利影響。
傳統封裝技術可劃分成兩個類別。在第一類別中，在鋸切晶圓上的晶粒之前封裝所述晶粒。此種封裝技術具有某些有利特徵，例如具有更大的產量及更低的成本。此外，需要更少的底部填充物或模塑化合物。然而，此種封裝技術亦具有缺點。由於晶粒的大小正日漸變小，因此相應封裝可僅為扇入型封裝（fan-in type package），在所述扇入型封裝中每一晶粒的輸入/輸出墊被限制於位於相應晶粒的表面正上方的區域。由於晶粒的面積有限，因此輸入/輸出墊的數目因所述輸入/輸出墊的節距（pitch）的限度而受限。若欲減小墊的節距，則可能出現焊料橋（solder bridge）。另外，根據固定的球之大小要求，焊料球必須具有特定大小，此進而會限制可在晶粒的表面上包裝的焊料球的數目。
在封裝的另一類別中，是在封裝晶圓之前自所述晶圓鋸切出晶粒。此封裝技術的有利特徵是可形成扇出型封裝（fan-out package），此意指晶粒上的輸入/輸出墊可被重佈線至較所述晶粒大的區域，且因此在晶粒的表面上所包裝的輸入/輸出墊的數目可增大。此種封裝技術的另一有利特徵是可封裝“已知合格晶粒（known-good-die）”並捨棄缺陷晶粒，且因此不會在缺陷晶粒上浪費成本及精力。
在扇出型封裝中，將元件晶粒密封於模塑化合物中，所述模塑化合物接著被平坦化以暴露出元件晶粒。接著形成重佈線線路以連接至元件晶粒。扇出型封裝亦可包括穿透過模塑化合物的穿孔（through via）。
本發明實施例提供一種半導體封裝，包括第一介電層、元件晶粒、主動穿孔及虛設穿孔、密封材料、第二介電層、主動金屬頂蓋、虛設金屬頂蓋以及第一重佈線線路。元件晶粒位於第一介電層之上並貼合至第一介電層。密封材料密封元件晶粒、主動穿孔、及虛設穿孔。第二介電層位於元件晶粒、主動穿孔、及虛設穿孔之上並接觸元件晶粒、主動穿孔、及虛設穿孔。主動金屬頂蓋位於第二介電層之上並接觸第二介電層，並且電性耦合至主動穿孔，其中主動金屬頂蓋交疊主動穿孔。虛設金屬頂蓋位於第二介電層之上並接觸第二介電層，其中虛設金屬頂蓋交疊虛設穿孔，且虛設金屬頂蓋被第一間隙分隔成第一部分及第二部分。第一重佈線線路穿過所述第一間隙。
本發明實施例提供一種半導體封裝，包括元件晶粒、虛設穿孔、密封材料、第一介電層、第一虛設金屬頂蓋以及第一重佈線線路。密封材料密封元件晶粒及虛設穿孔。第一介電層位於元件晶粒、虛設穿孔、及密封材料之上並接觸元件晶粒、虛設穿孔、及密封材料。第一虛設金屬頂蓋位於第一介電層之上並接觸第一介電層，其中第一虛設金屬頂蓋交疊虛設穿孔且延伸超過虛設穿孔的邊緣。第一重佈線線路與第一虛設金屬頂蓋位於同一水平高度，其中第一重佈線線路將第一虛設金屬頂蓋分隔成第一部分及第二部分。
本發明實施例提供一種半導體封裝的形成方法包括：將元件晶粒貼合至第一介電層；在第一介電層之上形成主動穿孔及虛設穿孔；將元件晶粒、主動穿孔、及虛設穿孔密封于密封材料中；在密封材料之上形成第二介電層；以及在共用製程中沈積主動金屬頂蓋、重佈線線路、及虛設金屬頂蓋。主動金屬頂蓋及虛設金屬頂蓋分別交疊主動穿孔及虛設穿孔。虛設金屬頂蓋被重佈線線路分隔成第一部分及第二部分。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本發明實施例為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本發明各種實施例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
根據各種示例性實施例提供一種封裝及其形成方法。根據某些實施例說明形成所述封裝的中間階段。對某些實施例的某些變型進行論述。在各個圖中及說明性實施例通篇中，相同的元件符號用於表示相同的部件。
圖1至圖14說明根據某些實施例的封裝的形成過程中的各中間階段的剖視圖。圖1至圖14中所示的步驟亦於圖22中所示的製程流程200中進行示意性地說明。
圖1說明載體20及塗布於載體20上的離型層22。載體20可為玻璃載體、陶瓷載體等。載體20可具有圓的俯視圖形狀，且可具有矽晶圓的大小。舉例而言，載體20可具有8英吋的直徑、12英吋的直徑等。離型層22可由光熱轉換（Light To Heat Conversion，LTHC）塗布材料形成，其可與載體20一起自將在後續步驟中形成的上覆結構被移除。根據本發明的某些實施例，離型層22是由環氧樹脂系熱釋放材料形成。可將離型層22塗布至載體20上。
在離型層22之上形成介電層28。介電層28的底表面可接觸離型層22的頂表面。根據本發明的某些實施例，介電層28是由聚合物形成，所述聚合物可為例如聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene，BCB）等感光性材料。根據替代實施例，介電層28是由無機介電材料形成，所述無機介電材料可為例如氮化矽等氮化物、例如氧化矽等氧化物、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）、或類似材料。
圖2至圖4說明金屬柱體32A及32B的形成，金屬柱體32A及32B被統稱為金屬柱體32。相應步驟作為步驟202說明於圖22中所示製程流程中。在本說明通篇中，金屬柱體32或被稱作穿孔32，乃因金屬柱體32穿透過隨後分配的密封材料。
參照圖2，例如藉由物理氣相沈積（Physical Vapor Deposition，PVD）而形成金屬種子層29。金屬種子層29可包含銅，或根據某些實施例可包含鈦層及位於所述鈦層之上的銅層。在金屬種子層29之上形成光阻30。接著使用微影罩幕（圖中未示出）在光阻30上執行曝光（light-exposure）。在後續的顯影之後，在光阻30中形成開口31。經由開口31而暴露出金屬種子層29的某些部分。
接下來，如圖3中所示，藉由在開口31中鍍敷金屬材料而形成穿孔32（包括32A及32B）。所鍍敷金屬材料可為銅或銅合金。在後續步驟中，移除光阻30，且因此暴露出金屬種子層29的位於光阻30之下的部分。接著在蝕刻步驟中移除所暴露出的金屬種子層29之部分。在圖4中說明所得的穿孔32。在本說明通篇中，將金屬種子層29的其餘部分視作穿孔32的部分，故不再對其予以單獨說明。穿孔32包括功能性（主動）穿孔32A及虛設穿孔32B，二者的功能將在隨後的段落中進行論述。
圖5說明元件晶粒36的植放/貼合。相應步驟作為步驟204說明於圖22中所示的製程流程中。藉由晶粒貼合膜（Die-Attach Film，DAF）38而將元件晶粒36貼合至介電層28，晶粒貼合膜38為黏合劑膜。元件晶粒36可包括後表面（面朝下的表面）與晶粒貼合膜38實體接觸的半導體基底。元件晶粒36可包括位於半導體基底的前表面（面朝上的表面）處的積體電路元件（例如主動元件（包括例如電晶體（圖中未示出）））。元件晶粒36可為邏輯晶粒，例如中央處理單元（Central Processing Unit，CPU）晶粒、圖形處理單元（Graphic Processing Unit，GPU）晶粒、行動應用晶粒等。
根據某些示例性實施例，預形成金屬柱42（例如銅柱）來作為元件晶粒36的部分，其中將金屬柱42電性耦合至積體電路元件，例如元件晶粒36中的電晶體（圖中未示出）。根據本發明的某些實施例，聚合物填充相鄰金屬柱42之間的間隙以形成頂部介電層44。頂部介電層44亦可包括覆蓋並保護金屬柱42的一部分。根據本發明的某些實施例，聚合物層44可由聚苯並噁唑或聚醯亞胺形成。
接下來，如圖6中所示，藉由密封材料48來密封元件晶粒36及金屬柱體32。相應步驟作為步驟206說明於圖22中所示製程流程中。密封材料48填充相鄰穿孔32之間的間隙及穿孔32與元件晶粒36之間的間隙。密封材料48可包括模塑化合物、模制底部填充物、環氧樹脂、及/或樹脂。密封材料48的頂表面高於金屬柱42的頂端。模塑化合物可包含基材（base material）及位於所述基材中的填料顆粒（圖中未示出），所述基材可為聚合物、樹脂、環氧樹脂等。填料顆粒可為SiO2 、Al2 O3 、矽土等的介電顆粒，且可具有球體形狀。
在後續步驟中，如圖7中所示，執行平坦化（例如化學機械研磨（Chemical Mechanical Polish，CMP）步驟或機械磨削（mechanical grinding）步驟）以使密封材料48薄化，直至暴露出穿孔32及金屬柱42。相應步驟亦作為步驟206說明於圖22中所示製程流程中。基於所述平坦化步驟，穿孔32的頂端與金屬柱42的頂表面實質上齊平（共面），且與密封材料48的頂表面實質上共面。
圖8及圖9說明第一層前側重佈線線路及相應介電層的形成。參照圖8，形成介電層50。相應步驟作為步驟208說明於圖22中所示製程流程中。根據本發明的某些實施例，介電層50是由例如聚苯並噁唑、聚醯亞胺等聚合物形成。根據替代性實施例，介電層50是由氮化矽、氧化矽等形成。接著例如藉由微影製程（photo lithography process）來形成開口52。經由開口52而暴露出主動穿孔32A及金屬柱42。根據本發明的某些實施例，經由開口52而暴露出虛設穿孔32B。根據本發明的替代性實施例，開口52沒有被形成為暴露出某些或所有虛設穿孔32B，且因此某些或所有虛設穿孔32B在開口52形成之後仍被介電層50完全覆蓋。
接下來，參照圖9，在介電層50之上形成金屬特徵56（包括56A、56B、及56C）。導電特徵56包括位於介電層50之上的（主動）金屬頂蓋56A、虛設金屬頂蓋56B、及重佈線線路（Redistribution Line，RDL）56C，其中特徵56A、56B、及56C位於同一金屬層中且處於同一水平高度。相應步驟作為步驟210說明於圖22中所示製程流程中。在介電層50中形成穿孔54A以將金屬柱42及主動穿孔32A連接至上覆的金屬頂蓋56A及重佈線線路56C。重佈線線路56C包括位於介電層50之上的金屬跡線（金屬線路）。根據本發明的某些實施例，在鍍敷製程中形成金屬特徵56及穿孔54（包括54A及54B），所述鍍敷製程包括沈積種子層（圖中未示出）、在所述種子層之上形成光阻（圖中未示出）並將所述光阻圖案化、及在所述種子層之上鍍敷例如銅或鋁等金屬材料。種子層及所鍍敷材料可由相同材料或不同材料形成。接著移除經圖案化的光阻，隨後對種子層的先前被所述經圖案化的光阻覆蓋的部分進行蝕刻。
金屬頂蓋56A交疊對應的主動穿孔32A，且虛設金屬頂蓋56B交疊對應的虛設穿孔32B。金屬頂蓋56A及虛設金屬頂蓋56B較穿孔32大，以使得由相應的位於之下的穿孔32A及32B所造成的應力得以屏蔽。根據某些其中形成開口52（圖8）以暴露出虛設穿孔32B的實施例中，在介電層50中形成虛設穿孔54B，且虛設穿孔54B將某些或所有虛設金屬頂蓋56B實體地且電性地連接至虛設穿孔32B。根據替代性實施例，沒有開口52（圖8）被形成為暴露出虛設穿孔32B，且虛設金屬頂蓋56B藉由介電層50而與位於之下的虛設穿孔32B間隔開。因此，使用虛線示出虛設穿孔54B以表示可形成或可不形成虛設穿孔54B，且可形成某些虛設穿孔54B的同時，不形成其他虛設穿孔54B。
亦如圖9中所示，將虛設金屬頂蓋56B分隔成兩個（或更多個）部分，其中重佈線線路56C穿過虛設金屬頂蓋56B的經分隔部分之間的間隙/空間。金屬頂蓋56A及虛設金屬頂蓋56B可如圖17至圖21中所示具有圓的俯視圖形狀，以使得由其施加至周圍介電結構的應力最小化。根據替代性實施例，金屬頂蓋56A及虛設金屬頂蓋56B可具有例如六邊形形狀、八邊形形狀等其他多邊形形狀。可將重佈線線路56C連接至金屬頂蓋56A、穿孔54A、金屬柱42、及其他線路導電結構。重佈線線路56C用於傳導電壓、訊號、電力等。
參照圖10，根據本發明的某些實施例，在圖9中所示結構之上形成介電層60，隨後在介電層60中形成開口。因此經由所述開口而暴露出金屬頂蓋56A及重佈線線路56C的某些部分。可使用選自用於形成介電層50的相同的候選材料的材料來形成介電層60，所述候選材料可包括聚苯並噁唑、聚醯亞胺、或苯並環丁烯。接著形成包括58A且可包括58B的金屬特徵（重佈線線路）58。重佈線線路58A延伸至介電層60中的開口中以接觸金屬頂蓋56A及/或重佈線線路56C。相應步驟作為步驟212說明於圖22中所示製程流程中。
根據本發明的某些實施例，將重佈線線路58中的某些重佈線線路（標記為58B，其亦被稱作金屬橋）形成為互連虛設金屬頂蓋56B的經分隔部分。如此一來，同一虛設金屬頂蓋56B的經分隔部分與相應上覆金屬橋58B組合起來形成積體金屬特徵。因此，金屬橋58B可提高虛設金屬頂蓋56B的積體度，且因此改善虛設金屬頂蓋56B的應力屏蔽效應（stress shielding effect）。
根據本發明的替代性實施例，不形成某些或所有金屬橋58B。因此，同一虛設金屬頂蓋56B的經分隔部分彼此電性斷開，且沒有金屬特徵將其互連。因此使用虛線來說明金屬橋58B以指示可形成或可不形成某些或所有金屬橋58B。當虛設金屬頂蓋56B不具有上覆的連接金屬橋時，藉由介電層60來完全覆蓋虛設金屬頂蓋56B的經分隔部分中的每一者的整個頂表面。此外，可藉由介電層50及60來完全封閉虛設金屬頂蓋56B的經分隔部分中的一或多者。
圖11說明介電層62及重佈線線路64的形成。介電層62可由選自用於形成介電層50及60的同一組候選材料的材料形成。重佈線線路64亦可由金屬或金屬合金形成，所述金屬或金屬合金包括鋁、銅、鎢、及/或其合金。應理解，儘管在所示示例性實施例中，形成有三層重佈線線路（56、58、及64），然而重佈線線路的數目可具有任何數目的層，例如一個層或多於兩個層。
圖12說明根據某些示例性實施例的介電層66、球下金屬（Under-Bump Metallurgy，UBM）68、及電性連接件70的形成。相應步驟作為步驟214說明於圖22中所示製程流程中。介電層66可由選自用於形成介電層50及60的同一組候選材料的材料形成。舉例而言，可使用聚苯並噁唑、聚醯亞胺、或苯並環丁烯來形成介電層66。在介電層66中形成開口以暴露出作為重佈線線路64的部分的位於之下的金屬墊。根據本發明的某一實施例，將球下金屬68形成為延伸至介電層66中的開口中以接觸重佈線線路64。球下金屬68可由鎳、銅、鈦、或其多層形成。
接著形成電性連接件70。所述形成電性連接件70可包括在球下金屬68的暴露出的部分上放置焊料球，且接著對所述焊料球進行回焊。根據本發明的替代性實施例，所述形成電性連接件70包括執行鍍敷步驟以在球下金屬68之上形成焊料層，且接著對所述焊料層進行回焊。電性連接件70亦可包括亦可藉由鍍敷來形成的金屬柱、或金屬柱及焊料頂蓋。在本說明通篇中，將包括介電層28的結構與上覆的結構組合起來稱作封裝100，封裝100是包括多個元件晶粒36的複合晶圓（且在下文中亦被稱作複合晶圓100）。
接下來，例如藉由在離型層22上投射紫外（ultra violet，UV）光或雷射光束（laser beam）以使得離型層22在所述紫外光或雷射光束的熱量下分解而將封裝100自載體20剝離。因此，封裝100得以自載體20剝離。在圖13中示出所得封裝100。根據本發明的某些實施例，在所得封裝100中，介電層28存留而作為封裝100的底部部份並保護穿孔32。接著執行雷射鑽孔（laser drill）以移除介電層28的某些部分以形成開口72，以暴露出主動穿孔32A及虛設穿孔32B。接下來，執行單體化（晶粒-鋸切）製程以將複合晶圓100分隔成單獨的封裝100’。相應步驟作為步驟218說明於圖22中所示製程流程中。
圖14說明將封裝400結合至封裝100’，進而形成疊層封裝（Package-on-Package，PoP）結構/封裝300。相應步驟作為步驟220說明於圖22中所示製程流程中。藉由焊料區74來執行所述結合，焊料區74會将穿孔32A及32B接合至位於之下的封裝400中的金屬墊406。根據本發明的某些實施例，封裝400包括封裝基底404及一（或多個）元件晶粒402，元件晶粒402可為例如靜態隨機存取記憶體（Static Random Access Memory，SRAM）晶粒、動態隨機存取記憶體（Dynamic Random Access Memory，DRAM）晶粒等記憶體晶粒。
根據本發明的替代性實施例，不再在介電層28中形成開口72（圖13）並接著將封裝400直接結合至封裝100’，而是在元件晶粒36的後側上形成後側重佈線線路。為了形成後側重佈線線路，首先在圖12中所示結構上執行載體切換（carrier switch），其中在剝離載體20之前藉由黏合劑膜82而將電性連接件70黏附至載體80（圖15）。
接下來，自複合晶圓100剝離載體20（圖12），並顯露出介電層28。接著形成金屬特徵26（包括金屬頂蓋26A、虛設金屬頂蓋26B、及重佈線線路26C）及穿孔25/25B。所述形成可相似於導電特徵56及穿孔54的形成，且因此不再對其予以贅述。
接著形成圖15中所示的介電層24及金屬特徵86A、86B、84A、及84B。相應步驟作為步驟216說明於圖22中所示製程流程中。介電層24可由選自用於形成介電層50及60的同一組候選材料的材料形成。金屬特徵86A/84A（其包括金屬跡線86A及穿孔84A）亦可由金屬或金屬合金形成，所述金屬或金屬合金包括鋁、銅、鎢、及/或其合金。使用虛線來說明某些穿孔84B1以表示可形成或可不形成該些穿孔，且可將焊料區（圖16）74電性連接至虛設金屬頂蓋26B中某些（而非所有）經分隔片段，或者經由穿孔84B1而連接至虛設金屬頂蓋56B中的所有經分隔片段。可形成（或可不形成）介電層85。接著自載體80剝離複合晶圓100，並執行單體化/晶粒鋸切以將複合晶圓100分隔成單獨的封裝100’。接著將所得封裝100’結合至封裝400，以得到在圖16中所示的封裝300。
根據圖14及圖16中所示某些實施例，虛設穿孔32B是電性浮動的。舉例而言，在虛設穿孔32B的底側上，封裝400中的金屬墊406可為虛設墊，且不電性連接至任何位於之下的金屬線路及元件晶粒402。若在虛設穿孔32B的頂側上不形成穿孔54B，則藉由介電層50來覆蓋虛設穿孔32B的整個頂表面。可將虛設金屬頂蓋56B完全封閉於介電層50及60中（當不形成穿孔54B及金屬橋58B時），或可與金屬橋58B一起形成積體金屬特徵，可將此積體特徵完全封閉於介電層50、60、及62中（當不形成穿孔54B時）。所述積體特徵是電性浮動的。若將穿孔54B形成為連接至虛設穿孔32B，則金屬橋58B中的相應一者、穿孔54B中的相應一者、及虛設穿孔32B中的相應一者可形成互連金屬特徵，所述互連金屬特徵可為電性浮動的。
亦可將虛設穿孔32B電性接地或連接至一（或多個）非接地電壓，且可由元件晶粒402提供所述電性接地或非接地電壓。根據某些實施例，穿孔32B仍為虛設的，乃因其被配置成不容許電流流過。可達成此結果的原因是電性路徑可在不與任何上覆金屬特徵電性連接的金屬橋58B處終止。當沒有形成金屬橋58B時，電性路徑亦可在虛設金屬頂蓋56B處終止。當沒有形成穿孔54B時，電性路徑亦可在虛設穿孔32B的頂端處終止。
根據本發明的某些實施例，不形成區域78（圖16）中所示的其中包括穿孔84B、金屬跡線/墊86B、及焊料區70的導電特徵。因此，區域88中的所有金屬特徵組合起來而在介電材料24、28、48、50、60、及62中完全絕緣且為電性浮動的。作為另一選擇，不形成穿孔25B，且因此特徵32B、54B、56B、及/或58B在介電材料中完全絕緣。
根據本發明的替代性實施例，可形成有多個穿孔84B，所述多個穿孔84B中的每一者均連接至同一虛設金屬頂蓋26B的經分隔片段中的一者，且所述多個穿孔84B可電性連接至同一焊料區74。當沒有形成穿孔84B時，根據該些實施例的虛設金屬頂蓋26B亦可在介電層24及28中完全絕緣。
圖17說明圖14及圖16中所示封裝100’的一部分的俯視圖，其中說明元件晶粒36、主動穿孔32A、及虛設穿孔32B，且未示出其他特徵。應理解，穿孔32的所示佈局僅為實例，且穿孔32A及32B的實際數目及實際位置是基於封裝100’的翹曲情況（warpage situation）而確定，且被選擇成減少封裝100’的翹曲。可自圖17中含有線A-A的平面獲得圖14及圖16中所示封裝100’的剖視圖。
圖18說明根據某些實施例的主動金屬頂蓋56A及虛設金屬頂蓋56B的俯視圖。虛設金屬頂蓋56B可被分隔成兩個部分56B1及56B2以容許重佈線線路56C穿過排列於所述兩個部分之間的間隙/空間。因此，儘管虛設金屬頂蓋56B為大的且佔用相當大的面積，然而虛設金屬頂蓋56B所使用的間隙可仍被用於對重佈線線路56C進行佈線。圖18左側上的虛設金屬頂蓋56B示出重佈線線路56C穿過虛設金屬頂蓋56B中間的實例。因此，沒有穿孔54B（參照圖14及圖16）被形成為連接至相應虛設金屬頂蓋56B。圖18中間的虛設金屬頂蓋56B示出重佈線線路56C穿過遠離虛設金屬頂蓋56B中間的位置的實例。因此，可將或可不將穿孔54B形成為連接至相應虛設金屬頂蓋56B。圖18右側上的金屬頂蓋56表示主動金屬頂蓋56A。作為另一選擇，圖18右側上的金屬頂蓋56表示可形成於重佈線線路稀疏區（RDL-sparse region）中的未經分隔的虛設金屬頂蓋56B。
圖19說明其中多於一個重佈線線路56C穿過一個虛設金屬頂蓋56B的某些實施例。左側虛設金屬頂蓋56B被分隔成三個部分，在所述三個部分中具有兩個間隙，所述間隙中的每一者穿過有一個重佈線線路56C。右側虛設金屬頂蓋56B被分隔成兩個部分，兩個（或更多個）重佈線線路56C穿過同一間隙。
圖20及圖21說明其中重佈線線路56C不平直的某些實施例。重佈線線路56C可包括形成介於約30度與約150度之間的範圍內的角度α的兩個或更多個區段。在圖18至圖21中所示實例中，使用虛線來說明金屬橋58B以指示視需要來形成金屬橋58B。
本文中提供某些示例性尺寸。應理解，該些尺寸為實例。參照圖19、圖20、及圖21（以及具有相似尺寸的圖18），重佈線線路56C的寬度A以及間距B及C可小於約30微米（μm）。虛設金屬頂蓋56B的直徑D（或長度或者寬度）可介於約140微米與約230微米之間的範圍內。虛設穿孔32B的直徑E（或長度或者寬度）可介於約100微米與約190微米之間的範圍內。虛設穿孔54B的直徑F（長度或寬度）可介於約10微米與約60微米之間的範圍內。
重新參照圖16，在元件晶粒36的後側上形成虛設金屬頂蓋26B，重佈線線路26C穿過虛設金屬頂蓋26B。虛設金屬頂蓋26B及重佈線線路26C的佈局以及相應尺寸可與圖19至圖21中所示者實質上相同，且本文中不再對其予以贅述。
本發明的實施例具有某些有利特徵。形成虛設穿孔以提供額外的錨固力以用於結合至封裝400，以及減少封裝的翹曲。然而，虛設穿孔會對重佈線線路層產生應力。為了屏蔽由虛設穿孔造成的應力，在所述虛設穿孔的正上方或正下方形成大的虛設金屬頂蓋。虛設穿孔佔用大的晶片區域，且對重佈線線路的佈線造成不利影響。因此，根據本發明的實施例，將虛設金屬頂蓋分隔成更小的部分，且藉由所述更小的部分之間的間隙來對重佈線線路進行佈線。
根據本發明的某些實施例，一種半導體封裝包括：第一介電層；元件晶粒，位於所述第一介電層之上並貼合至所述第一介電層；主動穿孔及虛設穿孔；以及密封材料，密封所述元件晶粒、所述主動穿孔、及所述虛設穿孔。所述封裝更包括第二介電層，所述第二介電層位於所述元件晶粒、所述主動穿孔、及所述虛設穿孔之上並接觸所述元件晶粒、所述主動穿孔、及所述虛設穿孔。主動金屬頂蓋位於所述第二介電層之上並接觸所述第二介電層，並且電性耦合至所述主動穿孔。所述主動金屬頂蓋交疊所述主動穿孔。虛設金屬頂蓋位於所述第二介電層之上並接觸所述第二介電層。所述虛設金屬頂蓋交疊所述虛設穿孔。所述虛設金屬頂蓋被間隙分隔成第一部分及第二部分。重佈線線路穿過所述虛設金屬頂蓋的所述第一部分與所述第二部分之間的所述間隙。在本發明的一些實施例中，所述的半導體封裝更包括穿過第一間隙的第二重佈線線路。
根據本發明的某些實施例，一種半導體封裝包括：元件晶粒；虛設穿孔；密封材料，密封所述元件晶粒及所述虛設穿孔；以及第一介電層，位於所述元件晶粒、所述虛設穿孔、及所述密封材料之上並接觸所述元件晶粒、所述虛設穿孔、及所述密封材料。虛設金屬頂蓋位於所述第一介電層之上並接觸所述第一介電層，其中所述虛設金屬頂蓋交疊所述虛設穿孔且延伸超過所述虛設穿孔的邊緣。重佈線線路與所述虛設金屬頂蓋位於同一水平高度。所述重佈線線路將所述虛設金屬頂蓋分隔成第一部分及第二部分。
在本發明的一些實施例中，所述第一虛設金屬頂蓋的所述第一部分與所述第二部分彼此電性解耦合。在本發明的一些實施例中，所述的半導體封裝更包括位於第一虛設金屬頂蓋之上的金屬橋，其中金屬橋互連第一虛設金屬頂蓋的第一部分與第二部分。在本發明的一些實施例中，所述的半導體封裝更包括位於第一介電層中的穿孔，其中穿孔將第一虛設金屬頂蓋的第一部分連接至虛設穿孔，且第一虛設金屬頂蓋的第二部分是電性浮動的。在本發明的一些實施例中，所述的半導體封裝更包括第二介電層、第二虛設金屬頂蓋以及第二重佈線線路，其中第二介電層位於虛設穿孔及密封材料之下並接觸虛設穿孔及密封材料；第二虛設金屬頂蓋，位於第二介電層之下並接觸第二介電層，其中虛設穿孔交疊第二虛設金屬頂蓋的一部分；第二重佈線線路與第二虛設金屬頂蓋位於同一水平高度，其中第二重佈線線路將第二虛設金屬頂蓋分隔成在實體上彼此間隔開的第三部分與第四部分。在本發明的一些實施例中，所述第二虛設金屬頂蓋的第一部分及第二部分中的每一者完全封閉於介電材料中。
根據本發明的某些實施例，一種半導體封裝的形成方法包括：將元件晶粒貼合至第一介電層；在所述第一介電層之上形成主動穿孔及虛設穿孔；將所述元件晶粒、所述主動穿孔、及所述虛設穿孔密封于密封材料中；在所述密封材料之上形成第二介電層；以及在共用製程中沈積主動金屬頂蓋、重佈線線路、及虛設金屬頂蓋。所述主動金屬頂蓋及所述虛設金屬頂蓋分別交疊所述主動穿孔及所述虛設穿孔。所述虛設金屬頂蓋被所述重佈線線路分隔成第一部分及第二部分。
在本發明的一些實施例中，所述虛設金屬頂蓋的第一部分及第二部分分別與重佈線線路間隔開第一間隙及第二間隙，且所述形成方法更包括在第一間隙及第二間隙中形成第三介電層。在本發明的一些實施例中，所述形成方法更包括形成延伸至第三介電層中的多個導電特徵，其中虛設金屬頂蓋的第一部分及第二部分是電性浮動的。在本發明的一些實施例中，所述形成方法更包括形成延伸至第三介電層中的多個導電特徵，其中多個導電特徵中的金屬橋互連虛設金屬頂蓋的第一部分與第二部分，且金屬橋是電性浮動的。在本發明的一些實施例中，所述形成方法更包括在共用製程中形成將虛設金屬頂蓋的第一部分連接至虛設穿孔的穿孔，其中穿孔處於第二介電層中，且第二介電層中沒有穿孔連接至虛設金屬頂蓋的第二部分。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明實施例的各個態樣。熟習此項技術者應知，其可容易地使用本發明實施例作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明實施例的精神及範圍，而且他們可在不背離本發明實施例的精神及範圍的條件下對其作出各種改變、代替、及變更。
20、80‧‧‧載體
22‧‧‧離型層
24、28、50、60、62‧‧‧介電層/介電材料
25/25B‧‧‧穿孔
26A‧‧‧金屬頂蓋
26B‧‧‧虛設金屬頂蓋
26C‧‧‧重佈線線路
29‧‧‧金屬種子層
30‧‧‧光阻
31、52、72‧‧‧開口
32A‧‧‧金屬柱體/功能性（主動）穿孔/主動穿孔/穿孔
32B‧‧‧金屬柱體/穿孔/虛設穿孔/虛設穿孔/特徵
36‧‧‧元件晶粒
38‧‧‧晶粒貼合膜
42‧‧‧金屬柱
44‧‧‧頂部介電層/聚合物層
48‧‧‧密封材料/介電材料
54A、84B1‧‧‧穿孔
54B‧‧‧穿孔/虛設穿孔/特徵/虛設穿孔
56‧‧‧金屬特徵/導電特徵/重佈線線路/金屬頂蓋
56A‧‧‧金屬特徵/（主動）金屬頂蓋/特徵
56B‧‧‧金屬特徵/虛設金屬頂蓋/特徵
56B1、56B2‧‧‧部分
56C‧‧‧金屬特徵/重佈線線路/特徵
58A‧‧‧金屬特徵/重佈線線路
58B‧‧‧金屬特徵/重佈線線路/金屬橋/特徵
64‧‧‧重佈線線路
66、85‧‧‧介電層
68‧‧‧球下金屬
70‧‧‧電性連接件/焊料區
74‧‧‧焊料區
78、88‧‧‧區域
82‧‧‧黏合劑膜
84A、84B‧‧‧金屬特徵/穿孔
86A‧‧‧金屬特徵/金屬跡線
86B‧‧‧金屬特徵/金屬跡線/墊
100‧‧‧封裝/複合晶圓
100’‧‧‧封裝
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218、220‧‧‧步驟
300‧‧‧疊層封裝結構/封裝
400‧‧‧封裝
402‧‧‧元件晶粒
404‧‧‧封裝基底
406‧‧‧金屬墊
A-A‧‧‧線
A‧‧‧寬度
B、C‧‧‧間距
D、E、F‧‧‧直徑
α‧‧‧角度
結合附圖閱讀以下詳細說明，會最佳地理解本發明實施例的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1至圖14是說明根據某些實施例的包括前側重佈線線路的封裝的形成過程中的各中間階段的剖視圖。 圖15及圖16是根據某些實施例的包括前側重佈線線路及後側重佈線線路的封裝的形成過程中的各中間階段的剖視圖。 圖17是根據某些實施例的封裝的俯視圖。 圖18至圖21是根據某些實施例的虛設金屬頂蓋的俯視圖。 圖22說明根據某些實施例的形成封裝的製程流程。

Claims (10)

  1. 一種半導體封裝，包括： 第一介電層； 元件晶粒，位於所述第一介電層之上並貼合至所述第一介電層； 主動穿孔及虛設穿孔； 密封材料，密封所述元件晶粒、所述主動穿孔、及所述虛設穿孔； 第二介電層，位於所述元件晶粒、所述主動穿孔、及所述虛設穿孔之上並接觸所述元件晶粒、所述主動穿孔、及所述虛設穿孔； 主動金屬頂蓋，位於所述第二介電層之上並接觸所述第二介電層，並且電性耦合至所述主動穿孔，其中所述主動金屬頂蓋交疊所述主動穿孔； 虛設金屬頂蓋，位於所述第二介電層之上並接觸所述第二介電層，其中所述虛設金屬頂蓋交疊所述虛設穿孔，且所述虛設金屬頂蓋被第一間隙分隔成第一部分及第二部分；以及 第一重佈線線路，穿過所述第一間隙。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述虛設穿孔的所述第一部分及所述第二部分配合形成實質上圓形形狀、六邊形形狀、或八邊形形狀。
  3. 如申請專利範圍第1項所述的半導體封裝，其中所述虛設穿孔的所述第一部分及所述第二部分中的至少一者是電性浮動的。
  4. 如申請專利範圍第3項所述的半導體封裝，更包括位於所述第二介電層中的穿孔，其中所述穿孔連接所述虛設金屬頂蓋的所述第一部分，且所述虛設穿孔與所述虛設金屬頂蓋的所述第一部分組合起來是電性浮動的。
  5. 如申請專利範圍第3項所述的半導體封裝，更包括位於所述第二介電層中的穿孔，其中所述穿孔連接所述虛設金屬頂蓋的所述第一部分，且所述虛設穿孔與所述虛設金屬頂蓋的所述第一部分組合起來連接至電壓，且所述虛設穿孔與所述虛設金屬頂蓋的所述第一部分被配置成不容許電流流過。
  6. 如申請專利範圍第1項所述的半導體封裝，更包括互連所述虛設金屬頂蓋的所述第一部分與所述第二部分的金屬橋。
  7. 如申請專利範圍第6項所述的半導體封裝，其中所述金屬橋以及所述虛設金屬頂蓋的所述第一部分及所述第二部分組合起來是電性浮動的。
  8. 如申請專利範圍第1項所述的半導體封裝，其中所述虛設金屬頂蓋被第二間隙分隔出第三部分，所述第二間隙位於所述虛設金屬頂蓋的所述第二部分與所述第三部分之間，且所述封裝更包括位於所述第二間隙中的第二重佈線線路。
  9. 一種半導體封裝，包括： 元件晶粒； 虛設穿孔； 密封材料，密封所述元件晶粒及所述虛設穿孔； 第一介電層，位於所述元件晶粒、所述虛設穿孔、及所述密封材料之上並接觸所述元件晶粒、所述虛設穿孔、及所述密封材料； 第一虛設金屬頂蓋，位於所述第一介電層之上並接觸所述第一介電層，其中所述第一虛設金屬頂蓋交疊所述虛設穿孔且延伸超過所述虛設穿孔的邊緣；以及 第一重佈線線路，與所述第一虛設金屬頂蓋位於同一水平高度，其中所述第一重佈線線路將所述第一虛設金屬頂蓋分隔成第一部分及第二部分。
  10. 一種半導體封裝的形成方法，包括： 將元件晶粒貼合至第一介電層； 在所述第一介電層之上形成主動穿孔及虛設穿孔； 將所述元件晶粒、所述主動穿孔、及所述虛設穿孔密封于密封材料中； 在所述密封材料之上形成第二介電層；以及 在共用製程中沈積主動金屬頂蓋、重佈線線路、及虛設金屬頂蓋，其中所述主動金屬頂蓋及所述虛設金屬頂蓋分別交疊所述主動穿孔及所述虛設穿孔，且所述虛設金屬頂蓋被所述重佈線線路分隔成第一部分及第二部分。
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