TWI550787B - 晶粒中的環狀結構 - Google Patents

晶粒中的環狀結構 Download PDF

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Publication number
TWI550787B
TWI550787B TW103138144A TW103138144A TWI550787B TW I550787 B TWI550787 B TW I550787B TW 103138144 A TW103138144 A TW 103138144A TW 103138144 A TW103138144 A TW 103138144A TW I550787 B TWI550787 B TW I550787B
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Taiwan
Prior art keywords
metal
ring
layer
pad
metal ring
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TW103138144A
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English (en)
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TW201545286A (zh
Inventor
陳英儒
陳潔
陳憲偉
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台灣積體電路製造股份有限公司
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Publication of TW201545286A publication Critical patent/TW201545286A/zh
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Description

晶粒中的環狀結構
本案係有關於半導體元件之封裝結構。
現代電路的製程典型需要數個步驟。首先，在半導體晶圓上形成積體電路，該半導體晶圓含有多個相同的半導體晶片，其各自包括積體電路。而後，從該晶圓切割下該半導體晶片，並且將其封裝。封裝製程有兩個主要目的：保護精緻的半導體晶片，並且將內部積體電路連接至外部接腳(pin)。
隨著對於更多功能之需求增加，因而發展層疊封裝(package-on-package，PoP)技術，接合二或多個封裝以擴展封裝的整合能力。由於高度整合，元件之間的連接路徑縮短而改良所得PoP封裝的電子效能。使用PoP技術，使得封裝設計更具彈性並且較簡單。亦縮短上市時間。
本案之一實施例描述一種結構，其包括：晶粒。晶粒，其包括：一金屬墊；第一金屬墊；鈍化層，其係位於該第一金屬墊上方；聚合物層，其係位於該鈍化層上方；金屬柱，其係位於該第一金屬墊上方並且電性耦合至該第一金屬墊；以及金屬環，其係與該金屬柱齊 平，其中該聚合物層包括與該金屬柱及該金屬環齊平的第一部分。
在一實施例中，該結構進一步包括與該第一金屬墊齊平的第二金屬墊，其中該第二金屬墊形成附加金屬環，其係相鄰於該晶粒的邊緣。
在一實施例中，其中該金屬環延伸至該鈍化層中，該金屬環的底部表面係接觸該第二金屬墊的頂部表面。
在一實施例中，其中該金屬環包括底部表面，該底部表面係與該鈍化層的頂部表面接觸，該金屬環完全與該第二金屬墊隔離。
在一實施例中，其中該金屬環係電性浮接。
在一實施例中，該結構進一步包括與該金屬環重疊的密封環，其中該密封環延伸至複數個金屬間介電(Inter-Metal Dielectric，IMD)層中。
在一實施例中，該結構進一步包括：塑形材料，其塑形該晶粒；複數個連通柱(through-via)，其穿透該塑形材料；介電層，其具有與該塑形材料接觸的表面；以及重佈線，其係位於該介電層中，並且電性耦合至該金屬柱與該複數個連通孔，其中該金屬環包括與該介電層之該表面其坪的表面，以及其中該金屬環的該表面之整體係與該介電層接觸。
在一實施例中，其中該聚合物層進一步包括分別與該金屬柱及該金屬環重疊的第二部分以及第三部分。
本案之一實施例描述一種結構，其包括：晶粒；塑形材料，其係環繞該晶粒，其中該塑形材料的頂部表面係與該金屬柱的第一頂部表面及該金屬環的第二頂部表面齊平；介電層，其係位於該塑形材料上方並且與該塑形材料接觸；以及重佈線，其係位於該介電層中並且電性耦合至該金屬柱，其中該介電層覆蓋該金屬環的整體。其中晶粒包括：第一金屬墊；第二金屬墊，其係與該第一金屬墊齊平，其中該 第二金屬墊形成包圍該第一金屬墊的環；鈍化層，其係位於該第一金屬墊與該第二金屬墊的上方，該鈍化層包括對準該第一金屬墊之中心部分的開口；聚合物層，其係位於該鈍化層的上方；金屬柱，其係位於該第一金屬墊的上方並且電性耦合至該第一金屬墊；金屬環，其係與該金屬柱齊平，該金屬環包圍該金屬柱，其中該金屬環與該第二金屬墊重疊；以及密封環，其係位於該金屬環下方並且與該金屬環重疊。
在一實施例中，其中該介電層中無傳導特徵與該金屬環接觸。
在一實施例中，其中該金屬環係與該第二金屬墊接觸。
在一實施例中，其中該金屬環包括部分位於該鈍化層中，該金屬環的該部分之底部表面係與該第二金屬墊接觸。
在一實施例中，其中該金屬環包括底部表面，該底部表面係與該鈍化層的頂部表面接觸，該金屬環係藉由該鈍化層而與該第二金屬墊完全隔離。
在一實施例中，其中該金屬環係在該介電材料中完全絕緣，該金屬環的所有表面係與該介電材料接觸。
本案之一實施例描述一種方法，其包括：形成晶粒；在塑形材料中塑形該晶粒；以及研磨該塑形材料，以暴露該金屬柱的第一頂部表面以及該金屬環的第二頂部表面。該晶粒包括：金屬柱；金屬環，其係與該金屬柱齊平；以及聚合物層，其包括與該金屬柱及該金屬環齊平的第一部分，該聚合物層包圍該金屬柱與該金屬環。
在一實施例中，該方法包括：形成介電層，該介電層係位於該金屬柱、該金屬環以及該塑形材料上方，並且與該金屬柱、該金屬環以及該塑形材料接觸；以及在該介電層中，形成重佈線，其中該重佈線其中之一係連接至該金屬柱，以及在形成該重佈線之後，該金屬環之該第二頂部表面的整體係與該介電層的底部表面接觸。
在一實施例中，其中在該重佈線形成之後，該介電層中無金屬特徵與該金屬環接觸。
在一實施例中，該方法進一步包括在該塑形材料中形成連通柱，其中在該研磨該塑形材料之後，暴露該連通柱。
在一實施例中，其中形成該金屬環以重疊該晶粒中的密封環。
在一實施例中，其中該金屬環的底部表面係與該密封環接觸。
前文已頗為廣泛地概述本發明之特徵及技術優勢以便可更好地理解隨後的本發明之詳細描述。本發明之額外特徵及優勢將在下文中加以描述，且形成本發明之申請專利範圍的主題。熟習此項技術者應瞭解，所揭示之概念及特定實施例可易於用作修改或設計其他結構或程序以用於進行本發明之同樣目的之基礎。熟習此項技術者亦應認識到，此等等效構造並不脫離如隨附申請專利範圍中所闡明之本發明之精神及範疇。
8‧‧‧晶粒附接膜(DAF)
10‧‧‧半導體基板
12‧‧‧電晶體
14‧‧‧層間介電(ILD)
16‧‧‧互連結構
18‧‧‧介電層
20‧‧‧金屬線
22‧‧‧通路
26‧‧‧通路
28‧‧‧鈍化層
30、30A、30B‧‧‧金屬墊
32‧‧‧鈍化層
36‧‧‧聚合物層
40‧‧‧金屬柱
40A‧‧‧金屬柱
40B‧‧‧金屬環
40’‧‧‧頂部表面
43‧‧‧鋸刀
42‧‧‧密封環
48‧‧‧載體
44‧‧‧接觸栓
52‧‧‧緩衝層
50‧‧‧黏著層
54‧‧‧光阻
53‧‧‧晶種層
58‧‧‧連通柱
56‧‧‧開口
60A‧‧‧頂部表面
58A’‧‧‧頂部表面
62‧‧‧介電層
60‧‧‧塑形材料
66‧‧‧介電層
64‧‧‧重佈線
69‧‧‧介電層
68‧‧‧重佈線
72‧‧‧電連接器
70‧‧‧下金屬層
78‧‧‧載體
74、74’‧‧‧封裝
82‧‧‧介電層
80‧‧‧黏著層
86‧‧‧介電層
84‧‧‧重佈線
90‧‧‧開口
88‧‧‧膠帶
100’‧‧‧晶粒
100‧‧‧晶圓
202‧‧‧封裝基板
200‧‧‧封裝元件
204‧‧‧晶粒
由以下詳細說明與附隨圖式得以最佳了解本申請案揭示內容之各方面。注意，根據產業之標準實施方式，各種特徵並非依比例繪示。實際上，為了清楚討論，可任意增大或縮小各種特徵的尺寸。
圖1係根據一些實施方式說明晶圓的橫切面圖式。
圖2至16係根據一些實施方式說明在形成封裝的中間階段之橫切面圖式。
圖17係根據一些實施方式說明晶圓的一部分之俯視圖。
上文已經概略地敍述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應可瞭解，下文揭示之概念與特定實施例可作為基礎而相當輕易地予以修改或設計其它結構或製程而實現與本揭露相同之目的。本 揭露所屬技術領域中具有通常知識者亦應可瞭解，這類等效的建構並無法脫離後附之申請專利範圍所提出之本揭露的精神和範圍。
以下揭示內容提供許多不同的實施方式或範例，用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下，以簡化本申請案之揭示內容。當然，這些僅為範例，並非用於限制本申請案。例如，以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施方式，亦可包含在該第一與第二特徵之間形成其他特徵的實施方式，因而該第一與第二特徵可並非直接接觸。此外，本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的，而非支配不同實施方式與/或所討論架構之間的關係。
再者，本申請案可使用空間對應語詞，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明，以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外，裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向)，並且可相應解釋本申請案使用的空間對應描述。
根據不同的範例實施方式，提供晶粒以及形成包含該晶粒的封裝方法。本申請案說明形成該封裝的中間階段。本申請案討論實施方式的變異。在不同圖式與所說明的實施方式中，相同的元件符號係代表相同的元件。
圖1至16係根據一些實施方式說明形成封裝的中間階段之橫切面圖式。參閱圖1，提供晶圓100，其包含複數個晶粒100’。晶圓100進一步包含半導體基板10，其可為大塊矽(bulk silicon)基板或是絕緣體上矽(silicon-on-insulator)基板。或者，亦可使用含有III族、IV族與V 族元素的其他半導體材料，其可包含矽鍺、矽碳，以及/或可使用III-V化合物半導體材料。在半導體基板10中以及/或在半導體基板10上，形成積體電路裝置，例如電晶體12。晶圓100可進一步包含半導體基板10上方的層間介電(inter-layer dielectric，ILD)14以及互連結構16。互連結構16包含金屬線20與通路22，其係形成在介電層18中。此後，在相同位準(level)的金屬線統稱為金屬層。據此，互連結構16可包含複數個金屬層，其係透過通路22而互連。金屬線20與通路22可由銅或銅合金形成，但其亦可由其他金屬形成。在一些實施方式中，介電層18包括低k介電材料。例如，該低k介電材料的介電常數(k值)可小於約3.0或約2.5。
該金屬層包含底部金屬層(亦稱為金屬層1，或是M1)至頂部金屬層(Mtop)。在一些實施方式中，該Mtop層係最頂部的金屬層，並且係由低k介電材料形成。
根據本申請案揭示內容的一些實施方式，在頂部金屬層Mtop與個別介電層18的上方，形成鈍化層28。鈍化層28的k值大於3.8，並且係使用非低k介電材料形成鈍化層28。在一些實施方式中，鈍化層28係複合層，其包括氧化矽層(未繪示)以及位於該氧化矽層上方的氮化矽層(未繪示)。亦可由例如未摻雜的矽酸鹽玻璃(USG)、氧氮化矽以及/或類似物之其他非多孔介電材料而形成鈍化層28。
金屬墊30(包含30A與30B)形成於鈍化層28中的部分，並且可透過通路26、金屬線20以及通路22而電性耦合至電晶體12。金屬墊30可為鋁墊或是鋁-銅墊，因而亦可稱為鋁墊，但是亦可使用其他金屬材料。例如，金屬墊30的鋁(原子)百分比係約99.5百分比至約99.9百分比之間，以及銅百分比係約0.1百分比至約0.5百分比之間。在圖1中，通路26係作為Mtop層中的金屬線20連接至上方的金屬墊30。
在其他實施方式中，金屬墊30可與頂部金屬層中的金屬線(墊)20 物理接觸且無通路位於其間。
亦如圖1所示，在鈍化層上方，形成鈍化層32。鈍化層32的材料可與鈍化層28的材料相同。鈍化層28與32可由相同介電材料形成，或是由不同的介電材料形成。在一些實施方式中，鈍化層32包含氧化矽層以及在該氧化矽層上方的氮化矽層。而後，將鈍化層32圖案化，使得鈍化層32的部分覆蓋金屬墊30的邊緣部分，以及金屬墊30的中心部分透過鈍化層32的開口而暴露。在一些實施方式中，鈍化層32亦可包含與金屬墊30齊平的部分。
在金屬墊30的上方，形成金屬柱40。金屬柱40的形成可包含進行物理蒸氣沉積(PVD)，以沉積晶種層，形成且圖案化遮罩層(未繪示)，至少一些金屬墊30不被該遮罩層遮蓋，以及而後進行電鍍步驟以形成金屬柱40。接著，蝕刻該遮罩層以及受到該遮罩層覆蓋的部分晶種層。金屬柱40可包括銅或其他金屬或是包含銅、鋁、鎢、鎳、鈷的金屬合金，以及/或類似物。
形成聚合物層36作為晶圓100的頂部特徵。聚合物層36可為介電層，但是其亦可由非聚合物形成，例如可由無機材料形成。該形成製程可包含旋塗，而後為硬化製程。該硬化製程使得聚合物層36固體化。在一些實施方式中，聚合物層36係由聚苯噁唑(polybenzoxazole，PBO)形成。在其他實施方式中，聚合物層36係由其他聚合物形成，例如苯并環丁烯(benzocyclobutene，BCB)、聚醯亞胺或類似物。聚合物層36的材料可為光敏性，但是亦可使用非光敏性材料。
金屬柱40包含金屬柱40A與金屬環40B。金屬柱40A係作為晶粒100’中的特徵與接合至晶粒100’的特徵之間的電性連接。金屬環40B係為由金屬製作之環狀結構，其係接近個別晶粒100’之邊緣。圖17係說明圖1之結構的俯視圖，其中金屬環40B具有四側，各自與對應晶 粒100’的邊緣相鄰。個別金屬環40B包圍金屬柱40A。在一些實施方式中，如圖1所示，聚合物層36係延伸至金屬柱40的頂部。
參閱圖1，根據一些實施方式，金屬環40B與個別密封環42重疊。密封環42包含介電層18中的複數個金屬環，其中該金屬環包含形成環的複數個金屬線20以及形成環的複數個通路22。金屬線20的環與通路22的環相連接，以形成延伸穿過所有介電層18的整合環。在一些實施方式中，密封環42亦包含由接觸栓(contact plug)44，其延伸至半導體基板10的頂部表面。此外，金屬墊30B亦可形成環，金屬墊30B形成的該金屬環連接至介電層18中的環，以形成整合的且連續的金屬環，其自聚合物層36持續延伸至層間介電14，或是可能延伸至半導體基板10。
密封環42亦可包含四側，各自與個別晶粒100’的邊緣相鄰，如圖17所示。再者，金屬環40B的四側可與密封環42的對應側重疊。
亦如圖1所示，進行晶粒切割步驟(由鋸刀43所示)，將晶圓100切割為複數個晶粒100’，各自包含金屬柱40A、金屬環40B以及密封環42。晶粒附接膜(die-attach film，DAF)8係附接至晶圓100的底部表面，因而亦可附接至各晶粒100’的底部。
圖2至16係根據一些範例實施方式說明在封裝中晶粒100’的中間階段之橫切面圖式。參閱圖2，提供載體48，以及黏著層50係位於載體48上。載體48可為空白玻璃載體、空白陶瓷載體或類似物。黏著層50可由黏著劑形成，該黏著劑例如紫外線(UV)膠、光熱轉換(LTHC)膠或類似物，但是可使用其他形式的黏著劑。在一些實施方式中，黏著層50在光熱下具有分解功能，因而將載體從形成於其上的結構釋放分離。
在一些實施方式中，在黏著層50上方，形成緩衝層52。或者，在黏著層50上方不形成緩衝層52。根據本申請案揭示內容的一些實施 方式，緩衝層52係介電層，其可為聚合物層。例如，該聚合物可為聚醯亞胺、PBO、BCB、焊料阻抗膜(SR)、或類似物。緩衝層52係具有均勻後度的平面層，其厚度可大於約2微米，並且可為約2微米至約40微米之間。緩衝層52的頂部表面與底部表面亦為平面。在其他實施.方式中，不形成緩衝層52。
例如，在緩衝層52上方，透過物理蒸氣沉積(PVD)或是金屬箔壓層而形成晶種層53。晶種層53可包括銅、鋁、鈦或是其多層。在一些實施方式中，晶種層53包括鈦層(未繪示)以及在該鈦層上方的銅層(未繪示)。在其他實施方式中，晶種層53包含單一銅層。
根據一些實施方式，在晶種層53上方，施用光阻54，並且將其圖案化。因此，在光阻54中形成開口56，透過開口56暴露部分的晶種層53。
如圖3所示，透過電鍍，在開口56中形成連通柱(through-via)58，該電鍍可為電鍍或是無電鍍。連通柱58係鍍在晶種層53暴露的部分上。連通柱58可包含銅、鋁、鎢、鎳或其合金。連通柱58的俯視形狀包含但不限於長方形、正方形、圓形及類似者。連通柱58的高度係由後續置放的晶粒100’(圖5)的厚度而決定，在不同的實施方式中，連通柱58的高度係大於或等於晶粒100’的厚度。
在電鍍連通柱58之後，移除光阻54，所得到的結構如圖4所示。此外，暴露受到光阻54覆蓋的部分晶種層53(圖20)。而後，進行蝕刻步驟，移除該暴露部分的晶種層53，其中該蝕刻可為非等向性或是等向性蝕刻。另一方面，仍未蝕刻與連通柱58重疊之部分的晶種層53。在本申請案的揭示內容中，剩下的晶種層53的下方部分係指連通柱58的底部部分。雖然所示之晶種層53與連通柱58的上方部分具有可區分的界面，但是當晶種層53與個別的下方連通柱58係以相似或相同材料形成時，晶種層53可與連通柱58合併而無可區分的界面於其間。據 此，晶種層53不再繪示於後續的圖式中。在其他實施方式中，晶種層53與下方電鍍部分的連通柱58之間存在可區分的界面。
圖5係說明在緩衝層52上方置放晶粒100’。晶粒100’可透過晶粒附接膜8而貼附至緩衝層52。雖然圖5係說明放置單一晶粒100’，但可在緩衝層52上方放置複數個晶粒100’，其中該複數個放置的晶粒100’可被放置為複數個列與欄。
參閱圖6，在晶粒100’與連通柱58上，將塑形材料60塑形。塑形材料60填充晶粒100’與連通柱58之間的間隙，並且可與緩衝層52接觸。塑形材料60可包含塑形化合物、塑形底膠(underfill)、還氧化合物或是樹脂。在該塑形製程之後，塑形材料60的頂部表面係高於金屬柱40與連通柱58的頂端。塑形材料60係為液體，而後受到硬化。
接著，進行平面化步驟，例如化學機械拋光(CMP)步驟或是研磨步驟，用以將塑形材料60薄化，直到暴露連通柱58。在一些實施方式中，如圖7所示，藉由平面化作用移除在金屬柱40頂部上之部分的聚合物層36。研磨的結果造成金屬柱40暴露。該研磨造成連通柱58的頂部表面58A’實質上與金屬柱40的頂部表面40’齊平(共平面)，並且實質上與塑形材料60的頂部表面60A齊平。
參閱圖8，介電層62形成於塑形材料60、連通柱58以及金屬柱40上方，並且與塑形材料60、連通柱58以及金屬柱40接觸。根據本申請案揭示內容的一些實施方式，介電層62係由聚合物形成，該聚合物例如PBO、聚醯亞胺或類似物。在其他實施方式中，介電層62係由無機介電材料形成，例如氮化矽、氧化矽、氮氧化矽、或類似物。
接著，參閱圖9，形成重佈線(redistribution line,RDL)64，以連接至金屬柱40與連通柱58。重佈線64亦可與金屬柱40與連通柱58互連。雖未繪示，但是重佈線64可包含位於下方且連接至重佈線64的金屬軌跡(金屬線)與通路。在這些實施方式中，在介電層62中形成該通 路，並且在介電層62上方形成該金屬軌跡(metal trace)。在一些實施方式中，在電鍍製程中形成重佈線64，其中每一個重佈線64包含晶種層(未繪示)以及位於該晶種層上方的電鍍金屬材料。該晶種層與該電鍍金屬材料可由相同材料或不同材料形成。
如圖9所示，金屬柱40A與連通柱58係電性連接至重佈線64並且可實際上接觸重佈線64。另一方面，金屬環40B可不連接至任何一個重佈線64。因此，根據本申請案揭示內容的實施方式，金屬環40B的頂部表面整體係與介電層62的底部表面接觸，並且不與任何金屬特徵接觸。
參閱圖10，根據不同的實施方式，在圖9所示的結構上方，形成一個或複數個介電層66，以及在介電層66中形成重佈線68。在一些實施方式中，每一層重佈線68的形成係包含形成覆蓋(blanket)晶種層、形成且圖案化在該覆蓋晶種層上方的遮罩層、進行電鍍以形成重佈線68、移除該遮罩層，以及進行蝕刻步驟以移除未被重佈線68覆蓋之該覆蓋晶種層。重佈線68可包括金屬或是包含鋁、銅、鎢之金屬合金、及/或其合金。
圖10係說明一重佈線68。在其他實施方式中，依照個別封裝的佈線需求(routing requirement)，可有更多的重佈線68。在這些實施方式中的介電層66可包括聚合物，例如PBO、聚醯亞胺、BCB或類似物。或者，介電層66可包含非有機介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽或類似物。
圖11係根據一些範例實施方式說明介電層69、下金屬層(under bump metallization,UBM)70與電連接器72的形成。形成介電層69的材料可選自於用於形成介電層62與66的候選材料。電連接器72的形成可包含在下金屬層70的暴露部分上放置焊球，而後回銲(reflow)該焊球。在其他實施方式中，電連接器72的形成包含進行電鍍步驟，以於 重佈線68上方形成焊接區(solder region)，而後回銲該焊接區。電連接器72亦可包含金屬柱，或是金屬柱與焊接蓋(solder cap)，其亦可透過電鍍而形成。在本申請案揭示內容中，包含晶粒100’、連通柱58、塑形材料60、上方重佈線64與68以及介電層62與66的組合裝置係稱為封裝74，其可為包含複數個晶粒100’的複合晶圓。
接著，例如，藉由投射UV光或是雷射於黏著層50上，而將封裝74自載體48脫離。亦自封裝74移除殘留的黏著層50與緩衝層52(若有緩衝層52)。所得到的結果係如圖12所示。封裝74係進一步透過黏著層80而附貼至載體78，其中電連接器72可面對接觸黏著層80。而後形成介電層82與重佈線84。根據本申請案揭示內容的一些實施方式，所繪示的重佈線84係代表單一重佈線層。在其他實施方式中，所繪示的重佈線84係代表多於一重佈線層，其中形成通路用以將不同重佈線層中的不同金屬軌跡互連。介電層82亦可由聚合物形成，例如PBO、BCB、聚醯亞胺、或無機材料，例如氧化矽、氮化矽、氮氧化矽或類似物。
如圖12所示，在重佈線84與介電層82上方，形成介電層86。可由PBO或其他有機或無機材料形成介電層86。在一些實施方式中，如圖13所示，在介電層86上方，形成/層壓膠帶88。而後，在介電層86與膠帶88中，形成開口90，因而暴露頂部重佈線84中的金屬墊。
在後續步驟中，封裝74係接合至封裝元件200，所得到的結構如圖14所示。根據一些實施方式，封裝元件200係包含記憶體晶粒(例如靜態隨機存取記憶體(SRAM)晶粒或是動態隨機存取記憶體(DRAM)晶粒)於其中的封裝。再者，封裝元件200可包含封裝基板202，晶粒204係接合在該封裝基板202上。
圖14係說明在塑形材料60中塑形的一晶粒100’。在製造製程中，可藉由塑形材料60同時塑形複數個晶粒100’。在本申請案揭示內容 中，封裝74包含複數個封裝74’，其各自包含一晶粒100’以及周圍的連通柱58。據此，各個封裝74’可接合至與封裝元件200相同的複數個封裝元件之一。在該接合之後，進行切割步驟，將封裝74切割為複數個封裝，其各自包含一個封裝74’以及對應的封裝元件200。
在圖14所示的實施方式中，金屬環40B的底部表面係接觸金屬墊30B的頂部表面，該金屬墊30B亦形成環。在這些實施方式中，金屬環40B與對應的密封環42可為電性浮接或是接地。
根據其他實施方式，如圖15所示，金屬環40B的底部表面係與鈍化層32的頂部表面接觸，並且藉由鈍化層32而與金屬墊30B的頂部表面相隔。因此，金屬環40B在介電基質材料中完全絕緣，介電層62、鈍化層32與聚合物層36完全將金屬環40B包圍於其中。再者，在這些實施方式中，金屬環40B係電性浮接。
圖14與15係說明有兩個密封環(標示為42A與42B)以及兩個金屬環40B1與40B2，密封環42A包圍密封環42B。金屬環40B1進一步包圍金屬環40B2。根據其他實施方式，如圖16所示，係單一密封環42與單一金屬環40B。圖17係說明晶圓100與晶粒100’的俯視圖。根據一些實施方式，金屬環40B的寬度A係約15微米至約70微米之間。金屬環40B的寬度A可大於、等於或小於金屬墊30的寬度E。金屬柱40A的寬度或直徑C可為約50微米至約100微米之間。然而，可理解本申請案揭示內容中的值係僅為範例，並且可更改為不同的值。金屬環40B1與40B2之間的距離D可大於約20微米。圖17係說明在一些實施方式中，金屬環42比個別的下方金屬環40B寬，B表示包圍欄(enclosure)，其可大於2微米。在其他實施方式中，密封環42可比個別的上方金屬環40B窄。
本申請案揭示內容的實施方式具有一些有利的特徵。如果在將晶圓切割為複數個晶粒的步驟中，不在頂部聚合物層中形成該金屬 環，如圖1所示，則切割刀施加的機械力可造成頂部聚合物層與下方介電層之間的脫層(delamination)，該下方介電層例如鈍化層。藉由形成該金屬環，增加該晶圓的機械強度，並且降低發生脫層的可能性。再者，該金屬環的形成更進一步增進該晶粒對於濕度滲入的抵抗性。
根據本申請案揭示內容的一些實施方式，晶粒包含金屬墊、在該金屬墊上方的鈍化層，以及在該鈍化層上方的聚合物層。金屬柱係位於該金屬墊上方，並且電性耦合至該金屬墊。金屬環係與該金屬墊齊平，該金屬環具有複數側接近該晶粒的邊緣。該聚合物層包含與該金屬柱及該金屬環齊平的部分。
根據本申請案揭示內容的其他實施方式，結構包含晶粒。該晶粒包含第一金屬墊，以及與該第一金屬墊齊平的第二金屬墊，其中該第二金屬墊形成包圍該第一金屬墊的環。該晶粒進一步包含在該第一金屬墊與該第二金屬墊上方的鈍化層，該鈍化層具有對準該第一金屬墊之中心部分的開口。聚合物層係位於該鈍化物層上方。金屬柱係位於該第一金屬墊上方，並且電性耦合至該第一金屬墊。金屬環係與該金屬柱齊平，並且該金屬環包圍該金屬柱。該金屬環與該第二金屬墊重疊。密封環係位於該金屬環下方，並且與該金屬環重疊。塑形材料環繞該晶粒，其中該塑形材料的頂部表面係與該金屬柱的第一頂部表面及該金屬環的第二頂部表面齊平。介電層係位於該塑形材料上方，並且與該塑形材料接觸。在該介電層中形成重佈線，該重佈線電性耦合至該金屬柱，其中該介電層覆蓋該金屬環的整體。
根據本申請案揭示內容的其他實施方式，方法包含形成晶粒，該晶粒包含金屬柱、與該金屬柱齊平的金屬環，以及聚合物層，其中該金屬環具有接近該晶粒之邊緣的四側，以及該聚合物層包含與該金屬柱及該金屬環齊平的部分。該聚合物層包圍該金屬柱與該金屬環。該方法進一步包含在塑形材料中塑形該晶粒，以及研磨該塑形材料， 以暴露該金屬柱的第一頂部表面與該金屬環的第二頂部表面。
前述內容概述一些實施方式的特徵，因而熟知此技藝之人士可更加理解本申請案揭示內容之各方面。熟知此技藝之人士應理解可輕易使用本申請案揭示內容作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施方式具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本申請案揭示內容的精神與範圍，以及熟知此技藝之人士可進行各種變化、取代與替換，而不脫離本申請案揭示內容之精神與範圍。
8‧‧‧晶粒附接膜(DAF)
10‧‧‧半導體基板
12‧‧‧電晶體
14‧‧‧層間介電(ILD)
16‧‧‧互連結構
18‧‧‧介電層
20‧‧‧金屬線
22‧‧‧通路
26‧‧‧通路
28‧‧‧鈍化層
30、30A、30B‧‧‧金屬墊
32‧‧‧鈍化層
36‧‧‧聚合物層
40‧‧‧金屬柱
40A‧‧‧金屬柱
40B‧‧‧金屬環
42‧‧‧密封環
43‧‧‧鋸刀
44‧‧‧接觸栓
100‧‧‧晶圓
100’‧‧‧晶粒

Claims (10)

  1. 一種晶粒之結構，其包括：晶粒，其包括：第一金屬墊；鈍化層，其係位於該第一金屬墊上方；聚合物層，其係位於該鈍化層上方；金屬柱，其係位於該第一金屬墊上方並且電性耦合至該第一金屬墊；以及金屬環，其頂部表面係與該金屬柱之頂部表面齊平，其中該聚合物層包括與該金屬柱及該金屬環齊平的第一部分。
  2. 如請求項1所述之結構，進一步包括與該第一金屬墊齊平的第二金屬墊，其中該第二金屬墊形成附加金屬環，其係相鄰於該晶粒的邊緣。
  3. 如請求項2所述之結構，其中該金屬環延伸至該鈍化層中，該金屬環的底部表面係接觸該第二金屬墊的頂部表面。
  4. 如請求項2所述之結構，其中該金屬環包括底部表面，該底部表面係與該鈍化層的頂部表面接觸，該金屬環完全與該第二金屬墊隔離。
  5. 如請求項1所述之結構，進一步包括與該金屬環重疊的密封環，其中該密封環延伸至複數個金屬間介電(Inter-Metal Dielectric，IMD)層中。
  6. 如請求項1所述之結構，進一步包括：塑形材料，其塑形該晶粒；複數個連通柱(through-via)，其穿透該塑形材料；介電層，其具有與該塑形材料接觸的表面；以及 重佈線，其係位於該介電層中，並且電性耦合至該金屬柱與該複數個連通孔，其中該金屬環包括與該介電層之該表面其坪的表面，以及其中該金屬環的該表面之整體係與該介電層接觸。
  7. 如請求項1所述之結構，其中該聚合物層進一步包括分別與該金屬柱及該金屬環重疊的第二部分以及第三部分。
  8. 一種晶粒之結構，其包括：晶粒，其包括：第一金屬墊；第二金屬墊，其係與該第一金屬墊齊平，其中該第二金屬墊形成包圍該第一金屬墊的環；鈍化層，其係位於該第一金屬墊與該第二金屬墊的上方，該鈍化層包括對準該第一金屬墊之中心部分的開口；聚合物層，其係位於該鈍化層的上方；金屬柱，其係位於該第一金屬墊的上方並且電性耦合至該第一金屬墊；金屬環，其係與該金屬柱齊平，該金屬環包圍該金屬柱，其中該金屬環與該第二金屬墊重疊；以及密封環，其係位於該金屬環下方並且與該金屬環重疊；塑形材料，其係環繞該晶粒，其中該塑形材料的頂部表面係與該金屬柱的第一頂部表面及該金屬環的第二頂部表面齊平；介電層，其係位於該塑形材料上方並且與該塑形材料接觸；以及重佈線，其係位於該介電層中並且電性耦合至該金屬柱，其中該介電層覆蓋該金屬環的整體。
  9. 一種晶粒結構之形成方法，其包括：形成晶粒，該晶粒包括：金屬柱；金屬環，其係與該金屬柱齊平；以及聚合物層，其包括與該金屬柱及該金屬環齊平的第一部分，該聚合物層包圍該金屬柱與該金屬環；在塑形材料中塑形該晶粒；以及研磨該塑形材料，以暴露該金屬柱的第一頂部表面以及該金屬環的第二頂部表面。
  10. 如請求項9所述之方法，其包括：形成介電層，該介電層係位於該金屬柱、該金屬環以及該塑形材料上方，並且與該金屬柱、該金屬環以及該塑形材料接觸；以及在該介電層中，形成重佈線，其中該重佈線其中之一係連接至該金屬柱，以及在形成該重佈線之後，該金屬環之該第二頂部表面的整體係與該介電層的底部表面接觸。
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Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6031059B2 (ja) * 2014-03-31 2016-11-24 信越化学工業株式会社 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US9520385B1 (en) * 2015-06-29 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming same
US9691723B2 (en) * 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
JP6862087B2 (ja) * 2015-12-11 2021-04-21 株式会社アムコー・テクノロジー・ジャパン 配線基板、配線基板を有する半導体パッケージ、およびその製造方法
TWI578483B (zh) * 2016-01-11 2017-04-11 美光科技公司 包含不同尺寸的封裝穿孔的封裝上封裝構件
US9837367B1 (en) 2016-10-19 2017-12-05 International Business Machines Corporation Fabrication of solder balls with injection molded solder
DE102017127920A1 (de) 2017-01-26 2018-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Erhöhte Durchkontaktierung für Anschlüsse auf unterschiedlichen Ebenen
US10297494B2 (en) * 2017-01-26 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Raised via for terminal connections on different planes
JP6903375B2 (ja) * 2017-04-19 2021-07-14 株式会社ディスコ デバイスチップの製造方法
CN107393900B (zh) * 2017-08-08 2019-07-26 中国电子科技集团公司第五十八研究所 极多层布线的埋置型tsv转接板结构
US10420211B2 (en) * 2017-08-09 2019-09-17 Advanced Semiconductor Engineering, Inc. Semiconductor package device
US10510691B2 (en) * 2017-08-14 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10074618B1 (en) * 2017-08-14 2018-09-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
KR101973445B1 (ko) * 2017-11-07 2019-04-29 삼성전기주식회사 팬-아웃 센서 패키지 및 카메라 모듈
KR101912292B1 (ko) * 2017-12-15 2018-10-29 삼성전기 주식회사 팬-아웃 반도체 패키지 및 이를 포함하는 패키지 온 패키지
US10622302B2 (en) 2018-02-14 2020-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Via for semiconductor device connection and methods of forming the same
US10872862B2 (en) * 2018-03-29 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having bridge structure for connection between semiconductor dies and method of fabricating the same
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate
DE102018126130B4 (de) 2018-06-08 2023-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und -verfahren
US11158775B2 (en) 2018-06-08 2021-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11114407B2 (en) * 2018-06-15 2021-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package and manufacturing method thereof
US10992100B2 (en) 2018-07-06 2021-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11088037B2 (en) * 2018-08-29 2021-08-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device having probe pads and seal ring
US11075173B2 (en) * 2018-10-31 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming same
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
US11373962B2 (en) 2020-08-14 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Advanced seal ring structure and method of making the same
KR20220027338A (ko) 2020-08-26 2022-03-08 삼성전자주식회사 반도체 장치
US11728229B2 (en) 2021-03-25 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy patterns in redundant region of double seal ring

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201001647A (en) * 2008-04-22 2010-01-01 Micron Technology Inc Die stacking with an annular via having a recessed socket
JP2011031036A (ja) * 2009-07-07 2011-02-17 Katsutoshi Kuki 自力服薬援助器具

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770971B2 (en) * 2002-06-14 2004-08-03 Casio Computer Co., Ltd. Semiconductor device and method of fabricating the same
JP4502173B2 (ja) 2003-02-03 2010-07-14 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
US6879019B2 (en) * 2003-06-24 2005-04-12 Intel Corporation Guard ring of a combination wafer or singulated die
US7453128B2 (en) 2003-11-10 2008-11-18 Panasonic Corporation Semiconductor device and method for fabricating the same
JP4055717B2 (ja) * 2004-01-27 2008-03-05 カシオ計算機株式会社 半導体装置およびその製造方法
JP2006173232A (ja) * 2004-12-14 2006-06-29 Casio Comput Co Ltd 半導体装置およびその製造方法
JP4395775B2 (ja) * 2005-10-05 2010-01-13 ソニー株式会社 半導体装置及びその製造方法
JP4851794B2 (ja) * 2006-01-10 2012-01-11 カシオ計算機株式会社 半導体装置
US8836146B2 (en) * 2006-03-02 2014-09-16 Qualcomm Incorporated Chip package and method for fabricating the same
JP5065695B2 (ja) 2007-02-01 2012-11-07 ルネサスエレクトロニクス株式会社 半導体装置
US8237160B2 (en) * 2007-05-10 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Probe pad on a corner stress relief region in a semiconductor chip
US8384199B2 (en) * 2007-06-25 2013-02-26 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US8587124B2 (en) * 2007-09-21 2013-11-19 Teramikros, Inc. Semiconductor device having low dielectric insulating film and manufacturing method of the same
DE102008025202B4 (de) * 2008-05-27 2014-11-06 Epcos Ag Hermetisch geschlossenes Gehäuse für elektronische Bauelemente und Herstellungsverfahren
US7906836B2 (en) 2008-11-14 2011-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreader structures in scribe lines
US8168529B2 (en) 2009-01-26 2012-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Forming seal ring in an integrated circuit die
JPWO2010086952A1 (ja) 2009-01-30 2012-07-26 パナソニック株式会社 半導体装置及びその製造方法
US8193555B2 (en) 2009-02-11 2012-06-05 Megica Corporation Image and light sensor chip packages
US7943423B2 (en) 2009-03-10 2011-05-17 Infineon Technologies Ag Reconfigured wafer alignment
EP2414801B1 (en) 2009-03-30 2021-05-26 QUALCOMM Incorporated Chip package with stacked processor and memory chips
US8338934B2 (en) * 2010-03-18 2012-12-25 Marvell World Trade Ltd. Embedded die with protective interposer
US8343810B2 (en) * 2010-08-16 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
KR101411741B1 (ko) 2011-11-11 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
US9607921B2 (en) * 2012-01-12 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package interconnect structure
US9099485B2 (en) * 2012-03-13 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of guard rings for wafer-level-packaging
US8796829B2 (en) 2012-09-21 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal dissipation through seal rings in 3DIC structure
US9031518B2 (en) 2012-12-17 2015-05-12 Qualcomm Incorporated Concurrent hybrid matching network
US8884400B2 (en) * 2012-12-27 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor in Post-Passivation structures and methods of forming the same
US20140183744A1 (en) * 2012-12-28 2014-07-03 Texas Instruments Incorporated Package substrate with bondable traces having different lead finishes
US8970001B2 (en) * 2012-12-28 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Guard ring design for maintaining signal integrity
US9129944B2 (en) * 2013-01-18 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US9082870B2 (en) * 2013-03-13 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of packaging semiconductor devices
US8987918B2 (en) * 2013-03-14 2015-03-24 Intel Corporation Interconnect structures with polymer core
US9425121B2 (en) * 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
US9728517B2 (en) * 2013-12-17 2017-08-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9583460B2 (en) * 2014-02-14 2017-02-28 Qualcomm Incorporated Integrated device comprising stacked dies on redistribution layers
US9666522B2 (en) * 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US9922896B1 (en) * 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201001647A (en) * 2008-04-22 2010-01-01 Micron Technology Inc Die stacking with an annular via having a recessed socket
JP2011031036A (ja) * 2009-07-07 2011-02-17 Katsutoshi Kuki 自力服薬援助器具

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CN105321913A (zh) 2016-02-10
US20150348916A1 (en) 2015-12-03
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US10262952B2 (en) 2019-04-16
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