TWI584435B - 封裝及其製造方法 - Google Patents

封裝及其製造方法 Download PDF

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Publication number
TWI584435B
TWI584435B TW104135984A TW104135984A TWI584435B TW I584435 B TWI584435 B TW I584435B TW 104135984 A TW104135984 A TW 104135984A TW 104135984 A TW104135984 A TW 104135984A TW I584435 B TWI584435 B TW I584435B
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Taiwan
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top surface
metal
molding material
device die
package
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TW104135984A
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TW201640636A (zh
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陳憲偉
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台灣積體電路製造股份有限公司
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Description

封裝及其製造方法
本揭露係關於用於晶粒探測的結構及相關探測方法。
隨著半導體技術的演進，半導體晶片/晶粒變得越來越小。同時，半導體晶粒上需要整合的越來越多的功能。因此，半導體晶粒需要在較小的面積上封裝越來越多數目的I/O墊，並且I/O墊的密度隨著時間快速增加。因此，半導體晶粒的封裝變得越加困難，進而不利地影響封裝產量。
習知的封裝技術可分為兩類。在第一類中，晶圓上的晶粒在切割之前先被封裝。此封裝技術具有一些優點特徵，例如較大的生產量與較低成本。再者，需要較少的底膠填充或是模塑料。然而，此封裝技術亦有缺點。由於晶粒的尺寸越來越小，因而個別的封裝可僅為扇入型封裝(fan-in type package)，其中各晶粒的I/O墊被直接侷限在個別晶粒之表面上方的區域。由於晶粒面積有限，I/O墊的數目因I/O墊間隔的限制而受到侷限。如果墊的間隔增加，可能會產生焊橋(solder bridge)。此外，在固定的球尺寸需求之下，焊球必具有某種尺寸，其因而限制了在晶粒表面上可封裝的焊球數目。
在另一類封裝中，晶粒在封裝之前被切割。此封裝技術的優點特徵在於可形成扇出封裝(fan-out package)，其係指晶粒上的I/O墊可分布至比晶粒更大的面積，因而可增加晶粒表面上封裝的 I/O墊數目。此封裝技術的另一優點特徵係封裝「已知的良好晶粒」，並且丟棄有缺陷的晶粒，因而不會浪費成本與氣力在有缺陷的晶粒上。
本揭露的一些實施例係提供一種封裝，其包括裝置晶粒，其包括金屬柱，其係位於該裝置晶粒的頂部表面；以及焊料區，其係位於該金屬柱的側壁上；塑封材料，其包圍該裝置晶粒，其中該塑封材料的頂部表面係與該裝置晶粒的頂部表面實質齊平；介電層，其係與該塑封材料與該狀晶粒重疊，該介電層的底表面係接觸該裝置晶粒的頂部表面與該塑封材料的頂部表面；以及重佈線(RDL)，其延伸至該介電層中，以電耦合該金屬柱。
本揭露的一些實施例係提供一種封裝，其包括裝置晶粒，其包括基板；金屬柱，其係位在該裝置晶粒的表面；焊料區，其具有部分位於該金屬柱的側壁上並且電耦合至該金屬柱的該側壁；以及聚合物層，其包圍該金屬柱，其中該金屬柱與該焊料區至少其中之一具有與該聚合物層的頂部表面實質齊平之頂部表面，以及該聚合物層與該基板係共同終止；塑封材料，其包圍該裝置晶粒，該塑封材料的邊緣係接觸該聚合物層的邊緣；貫穿通路，其穿過該塑封材料；介電材料，其係位在該裝置晶粒與該塑封材料上方；第一複數個重佈線，其係在該塑封材料上方，其中該第一複數個重佈線的第一個具有通路部分，其穿過該介電層以接觸該金屬柱與該焊料區該至少其中之一的該頂部表面；以及第二複數個重佈線，其係在該塑封材料的下方，其中該第一複數個重佈線的第二個係經由該貫穿通路而電耦合至該第二複數個重佈線之一。
本揭露的一些實施例係提供一種方法，其包括在裝置晶粒的金屬柱之頂部表面與側壁上，形成焊料區；藉由將探針接觸該 焊料區而探測該裝置晶粒；在該探測之後，將該裝置晶粒塑封於塑封材料中；將該裝置晶粒與該塑封材料平面化，其中該焊料區的頂部表面係與該塑封材料的頂部表面齊平，以及移除該金屬柱上方之至少部分的該焊料區；形成介電層於該裝置晶粒與該塑封材料上方並且接觸該裝置晶粒與該塑封材；以及形成重佈線，其包括穿過該介電層的通路部分，其中該通路部分各自接觸該焊料區與該金屬柱至少其中之一。
20‧‧‧晶圓
22‧‧‧半導體晶片
30‧‧‧半導體基板
30A‧‧‧表面
32‧‧‧積體電路
33‧‧‧層間介電
34‧‧‧互連結構
38‧‧‧介電層
35‧‧‧金屬線
36‧‧‧通路
42‧‧‧鈍化層
40‧‧‧金屬墊
46‧‧‧聚合物層
48‧‧‧凸塊下金屬層
54‧‧‧焊帽(solder cap)
50‧‧‧金屬柱
52‧‧‧金屬層
54‧‧‧焊接區
56‧‧‧探針
58‧‧‧聚合物層
59‧‧‧探測卡
60‧‧‧載體
62‧‧‧脫膜層
64‧‧‧介電層
66‧‧‧RDL
68‧‧‧介電層
70‧‧‧開口
72‧‧‧貫穿通路
74‧‧‧晶粒附貼膜
76‧‧‧塑封材料
78‧‧‧介電層
102‧‧‧封裝
200‧‧‧封裝
98‧‧‧焊料區
202‧‧‧裝置晶粒
80‧‧‧重佈線
82‧‧‧介電層
84‧‧‧開口
86‧‧‧RDL
88‧‧‧介電層
90‧‧‧開口
92‧‧‧UBM
94‧‧‧電連接器
100‧‧‧封裝
204‧‧‧封裝基板
由以下詳細說明與附隨圖式得以最佳了解本揭露之各方面。注意，根據產業之標準實施方式，各種特徵並非依比例繪示。實際上，為了清楚討論，可任意增大或縮小各種特徵的尺寸。
圖1至圖3係根據一些實施例說明形成裝置晶粒之中間階段的剖面圖。
圖4至圖18係根據一些實施例說明封裝裝置晶粒之中間階段的剖面圖與透視圖。
圖19至圖21係根據一些實施例說明封裝的剖面圖。
圖22係說明圖1至圖18所示之封裝製程的流程圖。
以下揭示內容提供許多不同的實施例或範例，用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下，以簡化本申請案之揭示內容。當然，這些僅為範例，並非用於限制本申請案。例如，以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施例，亦可包含在該第一與第二特徵之間形成其他特徵的實施例，因而該第一與第二特徵並非直接接觸。此外，本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的，而非支配不同實施例與/或所討論架構之間的 關係。
再者，本申請案可使用空間對應語詞，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明，以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外，裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向)，並且可相應解釋本申請案使用的空間對應描述。
根據不同的例示實施例，提供封裝及其形成方法。說明形成封裝的中間階段。討論實施例的變化。在不同的圖式與說明實施例中，相同的元件符號係用以表示相同的元件。
圖1至圖18係根據一些實施例說明形成集成的扇出(InFO)結構之剖面圖。圖22中所示的流程300亦說明圖1至圖18所示的步驟。在後續討論中，參閱圖22中的製程步驟，討論圖1至圖8中所示的製程步驟。
圖1係根據例示實施例說明晶圓20的剖面圖。晶圓20包含複數個半導體晶片22於其中。晶圓20進一步包含半導體基板30，其延伸至半導體晶片22中。半導體基板30可為大塊矽基板或是絕緣體上矽基板。或者，半導體基板30可包含其他半導體材料，其包含III族、IV族與V族元素。在半導體基板30的表面30A形成積體電路32。積體電路32可包含互補金屬氧化物半導體(CMOS)電晶體於其中。
裝置晶粒22可進一步包含半導體基板30上方的層間介電(ILD)33以及ILD 33上方的互連結構34。互連結構34係包含介電層38，以及形成在介電層38中的金屬線35與通路36。根據本揭露的一些實施例，介電層38係由低k介電材料形成。例如，該低k介電材料的介電常數(k值)可小於約2.8或小於約2.5。金屬線35與通路36可由銅、銅合金或含有傳導材料之其他金屬形成。可使用單鑲嵌與/或雙鑲嵌製 程，形成金屬線35與通路36。
金屬墊40係形成在互連結構34上方，並且可經由互連結構34中的金屬線35與通路36而電耦合至電路32。金屬墊40可為鋁墊或是鋁-銅墊，或可包含其他金屬。根據本揭露的一些實施例，在金屬墊40下方且與其接觸的金屬特徵係金屬線。在其他實施例中，在金屬墊40下方且與其接觸的金屬特徵係金屬通路。
形成鈍化層42，以覆蓋金屬墊40的邊緣部。每一金屬墊40的中心部係透過鈍化層42中的開口而暴露。鈍化層42可由非孔洞材料形成。根據本揭露的一些實施例，鈍化層42係複合層，其包括氧化矽層(未繪示)以及在該氧化矽層上方的氮化矽層(未繪示)。在其他實施例中，鈍化物層42係包括未摻雜的矽酸鹽玻璃(USG)、氮氧化矽與/或類似物。雖然繪示一鈍化層42，但可有超過一鈍化層。
聚合物層46形成於鈍化層42上方，並且覆蓋鈍化層42。聚合物層46可包括聚合物，例如環氧化合物、聚亞醯胺、苯并環丁烯(BCB)、聚苯并噁唑(PBO)與類似物。將聚合物層46圖案化以形成開口，金屬墊40係經由該開口而暴露。
凸塊下金屬層(UBM)48係形成於金屬墊40上方。UBM 48係包括在聚合物層46上方的第一部分，以及延伸至聚合物層46中的開口與鈍化層42之第二部分，以電耦合至金屬墊40。根據本揭露的一些實施例，每一UBM 48係包含鈦層與銅或銅合金所形成的晶種層。
根據一些實施例，金屬柱50係形成於個別的UBM 48上方，並且與個別的UBM 48一起終止(co-terminus)。例如，每一個金屬柱50的邊緣係對準相應的個別UBM 48之邊緣。因此，金屬柱50的側向尺寸亦等於UBM 48的個別側向尺寸。UBM 48可實體接觸個別的上方之金屬柱50。在一些例示實施例中，金屬柱50係由非焊接材料形 成，其在熔化焊料的回焊製程中不會熔化。例如，金屬柱50可由銅或銅合金形成。
焊帽(solder cap)54係形成於金屬柱50的頂部表面上，其中焊帽54可由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金或類似物形成，並且可為無鉛焊帽或是含鉛焊帽。個別步驟係如圖22中的製程流程之步驟302所示。在一些例示實施例中，整個金屬柱50係由同質金屬材料形成，具有接觸金屬柱50的焊帽54。在其他實施例中，可形成其他金屬層52，作為接觸金屬柱50之頂部表面與側表面的共形層。使用虛線標記的金屬層52係指可形成或不形成該金屬層52。各金屬層52可完全包圍個別金屬柱，並且可包含重疊於個別金屬柱50的頂部。金屬層52可由鈦、鎳、鈀、金或其合金而形成。金屬層52係作為擴散阻障層。
在一些例示實施例中，UBM 48與金屬柱50的形成係包含進行物理氣相沉積(PVD)製程，以形成毯狀UBM層(未繪示，其中UBM 48係UBM層的剩餘部分)，以及形成且圖案化毯狀UBM層上方的遮罩層(未繪示)。遮罩層可為光阻塗覆或乾燥膜。而後，在遮罩層的開口中形成金屬柱50與焊帽54，毯狀UBM層係通過該開口而暴露。而後，藉由鍍而形成金屬柱50與焊帽54。在形成金屬柱50與焊帽54之後，移除遮罩層。移除圖案化遮罩層覆蓋的UBM層之部分，留下未移除的金屬柱50與焊帽54。
可進行回焊，因而焊帽54具有圓的頂部表面。在以下內容中，回焊的焊帽54係指焊料區54。焊帽54中的焊料係包含仍與金屬柱50重疊的一些部分，以及下向流而接觸金屬柱50之側壁的一些其他部分，如圖2所示。焊料區54可未覆蓋金屬柱50的側壁之底部。
接著，在焊料區54上進行探測步驟，以測試裝置晶粒22的電性。個別步驟係如圖22所示的製程流程之步驟304所示。置放 探針56與焊料區54接觸而進行探測。探針56係探測卡59的部分，探測卡56係電連接至測試設備(未繪示)。經由探測，發現缺陷裝置晶粒22，並且決定良好的晶粒。有利的是焊料區54比下方的金屬柱50更軟。因此，探針56與焊料區54之間的接觸係比探針56與金屬柱50之間的接觸更佳。因此，相較於未形成焊料區54，此探測更值得信賴。
在探測之後，形成聚合物層59以覆蓋晶圓20的頂部表面，如圖3所示。個別步驟係如圖22所示之製程步驟中的步驟306所示。因此，金屬柱50與焊料區54係包埋在聚合物層58中，其中聚合物層58的頂部表面係高於焊料區54的頂端。形成聚合物層58的材料可選自與聚合物層46相同的候選材料(例如PBO)。而後，在晶圓20上進行晶粒切割，並且將半導體晶片22彼此分離，如圖3所示。個別步驟係如圖22所示之製程流程的步驟308所示。在以下內容中，分離的半導體晶片22係指裝置晶粒22。
圖4至圖18係說明裝置晶粒22的封裝，以形成InFO結構，因而上方的電連接器(例如焊料區)可分布至大於裝置晶粒22的區域。圖4係說明載體60與形成於載體60上方的脫膜層62。載體60可為玻璃載體、陶瓷載體或類似物。載體60可具有圓的俯視形狀，以及一般的矽晶圓尺寸。例如，載體60可具有8吋直徑、12吋直徑或類似者。脫膜層62可由聚合物基底材料(光熱轉換(LTHC))材料形成，可沿著載體60從後續步驟中將形成的上方結構移除脫膜層62。在一些實施例中，脫膜層62係以環氧化合物基底的熱脫膜材料形成。在其他實施例中，脫膜層62係由紫外線(UV)膠形成。脫膜層62可為液體並且被硬化。在其他實施例中，脫膜層62係壓層膜，並且係被壓層於載體60上。脫膜層62的頂部表面係平的，並且具有高度的共平面性。
介電層64係形成於脫膜層62上。在一些實施例中，介電層64係由聚合物形成，其亦可為光敏材料，例如聚苯并噁唑 (PBO)、聚亞醯胺、苯并環丁烯(BCB)、或類似物，可使用光微影蝕刻製程而輕易將其圖案化。在其他實施例中，介電層64係由例如氮化矽之氮化物、例如氧化矽之氧化物、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)、或類似物而形成。
參閱圖5，重佈線(RDL)66係形成在介電層64上方。由於當完成封裝時，RDL係位在裝置晶粒22(圖18)的背面上，因而RDL 66亦係指背面RDL。RDL 66的形成可包含在介電層64上方形成晶種層(未繪示)，在晶種層上方形成圖案化的遮罩(未繪示)，例如光阻，而後在暴露的晶種層上進行鍍金屬。而後，移除圖案化的遮罩以及圖案化的遮罩所覆蓋的晶種層之部分，留下RDL 66，如圖5所示。根據一些實施例，晶種層包括鈦層以及位在鈦層上方的銅層。例如，可使用PVD形成晶種層。例如，可使用無電鍍進行該鍍製程。
參閱圖6，在RDL 66上方形成介電層68。圖4至圖6所示的步驟亦如圖22中的製程流程之步驟310所示。介電層68的底表面係接觸RDL 66的頂部表面與介電層64。根據本揭露的一些實施例，介電層68係由聚合物形成，其可為光敏材料，例如PBO、聚亞醯胺、BCB或類似物。在其他實施例中，介電層68係由例如氮化矽之氮化物、例如氧化矽之氧化物、PSG、BSG、BPSG或類似物而形成。而後，將介電層68圖案化以於其中形成開口70。因此，RDL 66係經由介電層68中的開口暴露。
參閱圖7，形成金屬支柱72。在說明內容中，由於金屬支柱72穿透後續形成的模塑料，因而金屬支柱72亦係指貫穿通路72。個別步驟係如圖22所示之製程流程的步驟312所示。根據本揭露的一些實施例，以鍍製程形成貫穿通路72。貫穿通路72的鍍製程可包含在層68上方形成毯狀晶種層(未繪示)，並且延伸至開口70中(圖6)，形成且圖案化光阻(未繪示)，以及在晶種層的部分上鍍貫穿通路72， 該晶種層的部分係經由光阻中的開口暴露。而後，移除光阻以及光阻覆蓋之晶種層的部分。貫穿通路72的材料可包含銅、鋁或類似物。貫穿通路72的形狀為桿狀。貫穿通路72的俯視形狀可為圓形、矩形、方形、六邊形或類似者。
圖8係說明在圖7所示之結構上置放裝置晶粒22的透視圖，其中裝置晶粒22係配置為列與欄。個別步驟係如圖22所示之製程流程的步驟314所示。置放探測過程中發現的良好晶粒22，並且丟棄缺陷晶粒22。貫穿通路72未繪示於圖8中，但仍存在於該架構中。
圖9係說明圖8所示之結構的部分剖面圖。在圖9中，僅說明單一裝置晶粒22及其周圍的貫穿通路72。然而，注意，圖9至圖17所示之製程步驟係在晶圓層級進行，以及於載體60上的所有裝置晶粒22上進行。參閱圖9，裝置晶粒22係經由晶粒附貼膜(DAF)74而附貼至介電層68，該晶粒附貼膜可為黏著膜。
接著，參閱圖10，在裝置晶粒22上將塑封材料76成形。個別步驟係如圖22所示之製程流程的步驟316所示。塑封材料76填充相鄰貫穿通路72之間的間隙以及貫穿通路72與裝置晶粒22之間的間隙。塑封材料76可包含模塑料、成形底膠填充、環氧化合物或是樹脂。塑封材料76的頂部表面係高於金屬柱50與貫穿通路72的頂端。
接著，如圖11所示，進行平坦化作用，例如化學機械拋光(CMP)步驟或是研磨步驟，以薄化塑封材料76，直到暴露貫穿通路72與金屬柱50。個別步驟係如圖22所示之製程流程的步驟318所示。由於研磨，貫穿通路72的頂端係與金屬柱50的頂部表面齊平(共平面)，並且與塑封材料76的頂部表面共平面。在例示實施例中，進行平坦化作用，直到暴露金屬柱50。因此，移除與金屬柱50重疊之焊料區54的部分。在平坦化作用之後，保留金屬柱50之側壁上的焊料區54的部分。在圖11所示之結構的俯視圖中，剩餘的焊料區54可形成或 不形成包圍個別金屬柱50的整個環形物。
保留在金屬柱50之側壁上的焊料區54的部分之高度H1係受到各種因子影響，例如回焊期間、回焊溫度、金屬柱50的材料、焊料的量等。在一些例示實施例中，H1/H2比例範圍可在約0.2與約0.5之間，其中H2係金屬柱50的高度。
圖12至圖17係說明正面RDL與焊料區的形成。參閱圖12，形成介電層78。個別步驟係如圖22所示之製程流程的步驟320所示。在一些實施例中，介電層78係由聚合物形成，例如PBO、聚亞醯胺或類似物。在其他實施例中，介電層78係由氮化矽、氧化矽或類似物形成。在介電層78中形成開口79，以暴露貫穿通路72與金屬柱50。可由光微影蝕刻製程，進行開口79的形成。
接著，參閱圖13，形成重佈線(RDL)80以連接至金屬柱50與貫穿通路72。RDL 80亦可與金屬柱50與貫穿通路72互連。RDL 80係包含在介電層78上方的金屬導線(金屬線)以及延伸至開口79中(圖12)的通路，用以電連接至貫穿通路72與金屬柱50。為求簡單說明，不說明連接至最左側與最右側金屬柱50的金屬線，然而其亦形成於其中。在一些實施例中，在鍍製程中形成RDL 80，其中各RDL 80包含晶種層(未繪示)以及在晶種層上方的被鍍金屬材料。晶種層與被鍍材料可由相同材料或不同材料形成。RDL 80可包括金屬或金屬合金，其包括鋁、銅、鎢以及其合金。RDL 80係由非焊材料形成。RDL 80的通路部分可實體接觸金屬柱50的頂部表面。再者，RDL 80的通路部分可實體接觸焊料區54的頂部表面(例如，如果發生錯位)，或與焊料區54實體分離(並且電耦合至焊料區54)。
參閱圖14，在RDL 80與介電層78上方，形成介電層82。可使用聚合物形成介電層82，該聚合物可選自於與介電層78相同的材料。例如，介電層82可包括PBO、聚亞醯胺、BCB或類似物。或 者，介電層82可包含非有機介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽或類似物。在介電層82中亦形成開口84，以暴露RDL 80。可經由光微影蝕刻製程，進行開口84的形成。
圖15係說明RDL 86的形成，其係電連接至RDL 80。RDL 86的形成可採用與形成RDL 80類似的方法與材料。由於RDL 86與80係位於裝置晶粒22的正面上，因而RDL 86與80亦稱為正面RDL。
如圖16所示，形成另一介電層88，其可為聚合物層，用以覆蓋RDL 86與介電層82。介電層88可選自用於形成介電層78與82的相同候選聚合物。而後，在介電層88中形成開口90，以暴露RDL 86的金屬墊部分。
圖17係根據一些例示實施例說明凸塊下金屬(UBM)92與電連接器94。UBM 92的形成可包含沉積與圖案化。電連接器94的形成可包含將焊球置放在UBM 92的暴露部分上，以及回焊該焊球。在其他實施例中，電連接器94的形成係包含進行鍍步驟，以於RDL 86上方形成焊料區，而後回焊該焊料區。電連接器94亦可包含金屬柱或金屬柱與焊帽，其亦可經由鍍製程而形成。在說明內容中，包含裝置晶粒22、貫穿通路72、塑封材料76以及對應的RDL與介電層的組合結構可稱為封裝100，其可為具有圓俯視形狀的複合晶圓。
接著，將封裝100自載體60去接合。個別步驟係如圖22所示之製程流程的步驟322所示。亦將脫模層62自封裝100清除。藉由在脫模層62上投射例如UV光或雷射之光用以分解脫模層62而進行去接合。
在去接合過程中，可將膠帶(未繪示)貼附在介電層68與電連接器94上。在後續步驟中，自封裝100移除載體60與脫模層62。進行晶粒切割步驟，將封裝100切割為複數個封裝，各自包含裝 置晶粒22與貫穿通路72。所得的封裝之一係如圖18的封裝102所示。
圖18係說明接合封裝102與另一封裝200。個別步驟係如圖22所示之製程流程的步驟324所示。根據本揭露的一些實施例，經由焊料區98進行接合，該焊料區98將RDL 66的金屬墊部結合至封裝200中的金屬墊。在一些實施例中，封裝200包含裝置晶粒202，其可為記憶體晶粒，例如靜態隨即存取記憶體(SRAM)晶粒、動態隨機存取記憶體(DRAM)晶粒、或類似物。在一些例示實施例中，記憶體晶粒亦可接合至封裝基板204。
圖19至圖21係根據本揭露的其他實施例說明所形成之封裝的剖面圖。除非特別指名，否則這些實施例中的元件之材料與形成方法係與圖1至圖18所示之實施例中的元件符號所代表之元件實質相同。因此，在圖1至圖18所示之實施例的討論中可得到關於圖19至21所示之元件的形成製程與材料的詳細內容。
圖19的封裝係與圖18的封裝類似，差別在於焊料區54具有保留重疊在金屬柱50的部分。這是自圖11所示平坦化步驟中形成，在完全移除重疊金屬柱50的焊接區54之部分前，停止該平坦化。因此，在圖19之所得結構中，焊接區54將RDL 80的通路部分與下方金屬柱50實體彼此分離，並且將RDL 80電連接至個別金屬柱50。焊料區54的頂部表面係與貫穿通路72、塑封材料76與聚合物層58之頂部表面共平面。
圖20係根據其他實施例說明封裝的剖面圖。圖20所示的結構係類似於圖19的結構，差別在於RDL的通路部分穿透焊料區54，以接觸金屬柱50的頂部表面。個別焊料區54可包圍RDL的通路部分80。個別形成製程係包含蝕刻步驟，當介電層78被圖案化時，用以蝕刻穿透焊料區54。
圖21係根據其他實施例說明封裝的剖面圖。圖20所示 的結構係類似於圖18的結構，差別在於擴散阻障層52形成於金屬柱50的側壁上並且分離金屬柱50與焊料區54。
本揭露的實施例具有一些有利特徵。藉由在金屬柱上形成焊料區，而後經由焊料區探測個別裝置晶粒，因而改良探測的可信賴度。
根據本揭露的一些實施例，封裝包含裝置晶粒，其包含該裝置晶粒的頂部表面上的金屬柱以及在金屬柱側壁上的焊料區。塑封材料包圍裝置晶粒，其中塑封材料的頂部表面係與裝置晶粒的頂部表面實質齊平。介電層重疊塑封材料與裝置晶粒，介電層的底表面係接觸裝置晶粒的頂部表面與塑封材料的頂部表面。RDL延伸至介電層中，以電耦合至金屬柱。
根據本揭露的其他實施例，封裝係包含裝置晶粒，其包含基板、在裝置晶粒之表面處的金屬柱、焊料區，其具有部分位在金屬柱的側壁上並且電耦合至金屬柱，以及包圍金屬柱的聚合物層。金屬柱與焊料區至少其一之頂部表面係與聚合物層的頂部表面實質齊平，以及聚合物層與基板係共同終止(co-terminus)。該封裝進一步包含包圍裝置晶粒的塑封材料，塑封材料的邊緣係接觸聚合物層的邊緣，以及穿過塑封材料的貫穿通路。介電層係在裝置晶粒與塑封材料上方。第一複數個重佈線位於塑封材料上，其中該第一複數個重佈線的第一個重佈線具有穿過介電層的通路部分，以接觸金屬柱與焊料區至少其一的頂部表面。第二複數個重佈線係位於塑封材料上，其中該第一複數個重佈線的第二個重佈線係經由貫穿通路而電耦合至該第二複數個重佈線其中之一。
根據本揭露的其他實施例，方法包含在裝置晶粒的金屬柱之頂部表面與側壁上形成焊料區，以及藉由將探針接觸焊料區而探測該裝置晶粒。在探測之後，裝置晶粒被塑封在塑封材料中。將裝 置晶粒與塑封材料平坦化，其中焊料區的頂部表面係與塑封材料的頂部表面齊平，並且移除金屬柱上方至少部分的焊料區。介電層形成於裝置晶粒與塑封材料上方，並且接觸裝置晶粒與塑封材料。形成重佈線，其包含穿過介電層的通路部分，其中每一通路部分係接觸焊料區與金屬柱至少其一。
前述內容概述一些實施方式的特徵，因而熟知此技藝之人士可更加理解本申請案揭示內容之各方面。熟知此技藝之人士應理解可輕易使用本申請案揭示內容作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施方式具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本申請案揭示內容的精神與範圍，以及熟知此技藝之人士可進行各種變化、取代與替換，而不脫離本申請案揭示內容之精神與範圍。
22‧‧‧半導體晶片
50‧‧‧金屬柱
54‧‧‧焊接區
58‧‧‧聚合物層
64‧‧‧介電層
66‧‧‧RDL
68‧‧‧介電層
72‧‧‧貫穿通路
76‧‧‧塑封材料
78‧‧‧介電層
200‧‧‧封裝
204‧‧‧封裝基板
98‧‧‧焊料區
202‧‧‧裝置晶粒
80‧‧‧重佈線
82‧‧‧介電層
86‧‧‧RDL
88‧‧‧介電層
92‧‧‧UBM
94‧‧‧電連接器

Claims (10)

  1. 一種封裝，其包括：裝置晶粒，其包括：金屬柱，其係位於該裝置晶粒的頂部表面；以及焊料區，其係位於該金屬柱的側壁上；塑封材料，其包圍該裝置晶粒，其中該塑封材料的頂部表面係與該裝置晶粒的頂部表面實質齊平；介電層，其係與該塑封材料與該狀晶粒重疊，該介電層的底表面係接觸該裝置晶粒的頂部表面與該塑封材料的頂部表面；以及重佈線(RDL)，其延伸至該介電層中，以電耦合該金屬柱。
  2. 如請求項1所述之封裝，進一步包括貫穿通路，其穿過該塑封材料，其中該貫穿通路的頂部表面係與該裝置晶粒的頂部表面實質共平面。
  3. 如請求項1所述之封裝，其中該RDL的底表面係接觸該金屬柱的頂部表面，以及該焊料區的頂部表面係與該金屬柱的該頂部表面共平面。
  4. 如請求項1所述之封裝，其中該RDL的底表面係接觸該焊料區的頂部表面，以及該焊料區係包括重疊該金屬柱的部分。
  5. 一種封裝，其包括：裝置晶粒，其包括：基板；金屬柱，其係位在該裝置晶粒的表面；焊料區，其具有部分位於該金屬柱的側壁上並且電耦合至該金屬柱的該側壁；以及聚合物層，其包圍該金屬柱，其中該金屬柱與該焊料區至少 其中之一具有與該聚合物層的頂部表面實質齊平之頂部表面，以及該聚合物層與該基板係共同終止；塑封材料，其包圍該裝置晶粒，該塑封材料的邊緣係接觸該聚合物層的邊緣；貫穿通路，其穿過該塑封材料；介電材料，其係位在該裝置晶粒與該塑封材料上方；第一複數個重佈線，其係在該塑封材料上方，其中該第一複數個重佈線的第一個具有通路部分，其穿過該介電層以接觸該金屬柱與該焊料區該至少其中之一的該頂部表面；以及第二複數個重佈線，其係在該塑封材料的下方，其中該第一複數個重佈線的第二個係經由該貫穿通路而電耦合至該第二複數個重佈線之一。
  6. 如請求項5所述之封裝，其中該第一複數個重佈線的該第二個係包括另一通路部分，其係穿過該介電層以接觸該貫穿通路。
  7. 如請求項5所述之封裝，其中該第一複數個重佈線的該第一個的該通路部分係實體接觸該金屬柱的該頂部表面。
  8. 一種封裝的製造方法，其包括：在裝置晶粒的金屬柱之頂部表面與側壁上，形成焊料區；藉由將探針接觸該焊料區而探測該裝置晶粒；在該探測之後，將該裝置晶粒塑封於塑封材料中；將該裝置晶粒與該塑封材料平坦化，其中該焊料區的頂部表面係與該塑封材料的頂部表面齊平，以及移除該金屬柱上方之至少部分的該焊料區；形成介電層於該裝置晶粒與該塑封材料上方並且接觸該裝置晶粒與該塑封材；以及形成重佈線，其包括穿過該介電層的通路部分，其中該通路部 分各自接觸該焊料區與該金屬柱至少其中之一。
  9. 如請求項8所述之方法，其中藉由該平坦化移除該金屬柱的頂部表面上方之該焊料區的所有部分，以及該重佈線的該通路部分係實體接觸該金屬柱的該頂部表面。
  10. 如請求項8所述之方法，其中在該平坦化之後，留下部分的該焊料區重疊該金屬柱，以及該重佈線的該通路部分係實體接觸該焊料區之剩餘部分的頂部表面。
TW104135984A 2015-03-16 2015-11-02 封裝及其製造方法 TWI584435B (zh)

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DE102015106723A1 (de) 2016-09-22
CN105990291A (zh) 2016-10-05
CN105990291B (zh) 2018-11-27
US9911667B2 (en) 2018-03-06
US20160276235A1 (en) 2016-09-22
TW201640636A (zh) 2016-11-16
KR20160111298A (ko) 2016-09-26
DE102015106723B4 (de) 2019-06-06
KR101738240B1 (ko) 2017-05-19
US20170186655A1 (en) 2017-06-29
US9595482B2 (en) 2017-03-14

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