CN105990291B - 用于管芯探测的结构 - Google Patents

用于管芯探测的结构 Download PDF

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Publication number
CN105990291B
CN105990291B CN201510790632.7A CN201510790632A CN105990291B CN 105990291 B CN105990291 B CN 105990291B CN 201510790632 A CN201510790632 A CN 201510790632A CN 105990291 B CN105990291 B CN 105990291B
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metal column
top surface
solder areas
component pipe
pipe core
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CN105990291A (zh
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陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

封装件包括器件管芯，器件管芯包括位于器件管芯的顶面处的金属柱和位于金属柱的侧壁上的焊料区。模制材料环绕器件管芯，其中，模制材料的顶面与器件管芯的顶面基本齐平。介电层与模制材料和器件管芯重叠，其中介电层的底面与器件管芯的顶面和模制材料的顶面接触。再分布线(RDL)延伸至介电层内以电连接至金属柱。本发明的实施例还涉及用于管芯探测的结构。

Description

用于管芯探测的结构
技术领域
本发明的实施例涉及集成电路，更具体地，涉及用于管芯探测的结构。
背景技术
随着半导体技术的演化，半导体芯片/管芯正变得越来越小。同时，需要将更多的功能集成到半导体管芯内。因此，半导体管芯需要把越来越大量的I/O焊盘封装到较小的区域内，并且I/O焊盘的密度随着时间快速上升。结果，半导体管芯的封装变得更加困难，这不利地影响封装的产量。
传统的封装技术可以分为两类。在第一类中，在锯切晶圆上管芯之前封装晶圆上管芯。该封装技术具有一些有利特征，诸如较大的生产力和较低的成本。此外，需要较少的底部填充物或模塑料。然而，该封装技术也遭受缺点。由于管芯的尺寸正变得越来越小，并且相应的封装件仅可以是扇入型封装件，其中，每个管芯的I/O焊盘限制于直接位于相应的管芯的表面上方的区域。在管芯的有限区域的情况下，由于I/O焊盘的间距的限制而限制了I/O焊盘的数量。如果焊盘的间距减小，可能发生焊料桥接。此外，在固定的球尺寸需求下，焊球必须具有特定尺寸，这进而限制了可以封装在管芯的表面上的焊球的数量。
在另一类封装中，在封装管芯之前从晶圆锯切管芯。该封装技术的有利特征是形成扇出型封装件的可能性，这意味着管芯上的I/O焊盘可以分布至比管芯更大的区域，并且因此可以增大封装在管芯的表面上的I/O焊盘的数量。该封装技术的另一有利特征是，封装“已知良好管芯”，以及丢弃缺陷管芯，并且因此成本和精力不会浪费在缺陷管芯上。
发明内容
本发明的实施例提供了一种封装件，包括：器件管芯，包括：金属柱，位于所述器件管芯的顶面处；和焊料区，位于所述金属柱的侧壁上；模制材料，环绕所述器件管芯，其中，所述模制材料的顶面与所述器件管芯的顶面基本齐平；介电层，与所述模制材料和所述器件管芯重叠，其中，所述介电层的底面与所述器件管芯的顶面和所述模制材料的顶面接触；以及再分布线(RDL)，延伸至所述介电层内以电连接至所述金属柱。
本发明的另一实施例提供了一种封装件，包括：器件管芯，包括：衬底；金属柱，位于所述器件管芯的表面处；焊料区，具有位于所述金属柱的侧壁上的部分，并且所述焊料区电连接至所述金属柱；和聚合物层，环绕所述金属柱，其中，所述金属柱和所述焊料区中的至少一个的顶面与所述聚合物层的顶面基本齐平，并且所述聚合物层与所述衬底共末端；模制材料，环绕所述器件管芯，其中，所述模制材料的边缘与所述聚合物层的边缘接触；通孔，穿过所述模制材料；介电层，位于所述器件管芯和所述模制材料上方；多条第一再分布线，位于所述模制材料上面，其中，所述多条第一再分布线的第一条具有穿过所述介电层的通孔部分以与所述金属柱和所述焊料区中的至少一个的顶面接触；以及多条第二再分布线，位于所述模制材料下面，其中，所述多条第一再分布线的第二条通过所述通孔电连接至所述多条第二再分布线中的一条。
本发明的又一实施例提供了一种方法，包括：在器件管芯的金属柱的顶面和侧壁上形成焊料区；通过使探针与所述焊料区接触来探测所述器件管芯；在所述探测之后，将所述器件管芯模制在模制材料中；平坦化所述器件管芯和所述模制材料，其中，所述焊料区的顶面与所述模制材料的顶面齐平，并且去除所述焊料区的位于所述金属柱上方的至少部分；在所述器件管芯和所述模制材料上方形成与所述器件管芯和所述模制材料接触的介电层；以及形成再分布线，所述再分布线包括穿过所述介电层的通孔部分，其中，每个所述通孔部分均与所述焊料区和所述金属柱中的至少一个接触。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图3示出了根据一些实施例的在器件管芯的形成中的中间阶段的截面图；
图4至图18示出了根据一些实施例的在器件管芯的封装中的中间阶段的截面图和立体图；
图19至图21是根据一些实施例的封装件的截面图；以及
图22是图1至图18中示出的封装工艺的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
根据各个示例性实施例提供了封装件及其形成方法。示出了形成封装件的中间阶段。讨论了实施例的变化。贯穿各个视图和说明性实施例，相同的参考标号用于指代相同的元件。
图1至图18示出了根据一些实施例的在集成扇出型(InFO)结构的形成中的中间阶段的截面图。在如图22所示的工艺流程图300中也示意性地示出了图1至图18中示出的步骤。在随后的讨论中，参照图22中的工艺步骤讨论了图1至图18中示出的工艺步骤。
图1示出了根据示例性实施例的晶圆20的截面图。晶圆20包括位于晶圆20中的多个半导体芯片22。晶圆20还包括在半导体芯片22内延伸的半导体衬底30。半导体衬底30可以是块状硅衬底或绝缘体上硅衬底。可选地，半导体衬底30可以包括包含III族、IV族和V族元素的其他半导体材料。在半导体衬底30的表面30A处形成集成电路32。集成电路32可以包括位于其中的互补金属氧化物半导体(CMOS)晶体管。
器件管芯22还可以包括位于半导体衬底30上方的层间电介质(ILD)33和位于ILD33上方的互连结构34。互连结构34包括介电层38以及形成在介电层38中的金属线35和通孔36。根据本发明的一些实施例，介电层38由低k介电材料形成。例如，低k介电材料的介电常数(k值)可以小于约2.8，或小于约2.5。金属线35和通孔36可以由铜、铜合金或其他含金属导电材料形成。可以使用单镶嵌和/或双镶嵌工艺形成金属线35和通孔36。
金属焊盘40形成在互连结构34上方并且可以通过互连结构34中的金属线35和通孔36电连接至电路32。金属焊盘40可以是铝焊盘或铝-铜焊盘，或者可以包括其他金属。根据本发明的一些实施例，位于金属焊盘40下面并且接触金属焊盘40的金属部件是金属线。在可选实施例中，位于金属焊盘40下面并且接触金属焊盘40的金属部件是金属通孔。
形成钝化层42以覆盖金属焊盘40的边缘部分。通过钝化层42中的开口暴露每个金属焊盘40的中心部分。钝化层42可以由非多孔材料形成。根据本发明的一些实施例，钝化层42是复合层，该复合层包括氧化硅层(未示出)和位于氧化硅层上方的氮化硅层(未示出)。在可选实施例中，钝化层42包括未掺杂的硅酸盐玻璃(USG)、氮氧化硅等。虽然示出一个钝化层42，但是可以存在多于一个的钝化层。
聚合物层46形成在钝化层42上方并且覆盖钝化层42。聚合物层46可以包括诸如环氧化物、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等的聚合物。图案化聚合物层46以形成开口，通过该开口暴露金属焊盘40。
在金属焊盘40上方形成凸块下金属(UBM)48。UBM 48包括位于聚合物层46上方的第一部分以及延伸至聚合物层46和钝化层42中的开口内以电连接至金属焊盘40的第二部分。根据本发明的一些实施例，每个UBM 48均包括钛层和由铜或铜合金形成的晶种层。
根据一些实施例，金属柱50形成在相应的UBM 48上方并且与相应的UBM 48共末端。例如，每个金属柱50的边缘与相应的UBM 48的对应边缘对准。因此，金属柱50的横向尺寸也等于UBM 48的相应的横向尺寸。UBM 48可以与相应的上面的金属柱50物理接触。在一些示例性实施例中，金属柱50由在用于熔化焊料的回流工艺中不熔化的非焊料材料形成。例如，金属柱50可以由铜或铜合金形成。
在金属柱50的顶面上形成焊帽54，其中，焊帽54可以由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金等形成并且可以是无铅焊帽或含铅焊帽。相应的步骤示出为图22中示出的工艺流程图中的步骤302。在一些示例性实施例中，整个金属柱50由均匀的金属材料形成，其中焊帽54接触金属柱50。在可选实施例中，可以存在额外的金属层52，额外的金属层52形成为与金属柱50的顶面和侧壁表面接触的共形层。使用虚线标记金属层52以表明它们可以或可以不形成。每个金属层52均可以完全地环绕相应的金属柱50并且可以包括与相应的金属柱50重叠的顶部。金属层52可以由钛、镍、钯、金或它们的合金形成。金属层52用作扩散阻挡层。
在一些示例性实施例中，UBM 48和金属柱50的形成包括实施物理汽相沉积(PVD)工艺以形成毯状UBM层(未示出，其中，UBM 48是UBM层的剩余部分)，以及在毯状UBM层上方形成并且图案化掩模层(未示出)。掩模层可以是光刻胶涂层或干膜。然后在掩模层的开口中形成金属柱50和焊帽54，通过掩模层的开口暴露毯状UBM层。然后通过镀形成金属柱50和焊帽54。在形成金属柱50和焊帽54之后，去除掩模层。去除UBM层的由图案化的掩模层覆盖的部分，从而留下未去除的金属柱50和焊帽54。
可以实施回流，从而使得焊帽54具有圆形顶面。回流的焊帽54此后称为焊料区54。如图2所示，焊帽54中的焊料包括保持与金属柱50重叠的一些部分和向下流动以与金属柱50的侧壁接触的一些其他部分。焊料区54可以不覆盖金属柱50的底部和侧壁。
接下来，对焊料区54实施探测步骤以测试器件管芯22的电特性。相应的步骤示出为图22中示出的工艺流程图中的步骤304。通过使探针56与焊料区54接触来实施该探测。探针56是探针卡59的部分，探针卡59电连接至测试设备(未示出)。通过探测，找到缺陷器件管芯22，并且确定良好管芯。有利地，焊料区54比下面的金属柱50软。因此，探针56和焊料区54之间的接触比探针56和金属柱50之间的接触更好。因此，该探测比如果不形成焊料区54更加可靠。
如图3所示，在探测之后，形成聚合物层58以覆盖晶圆20的顶面。相应的步骤示出为图22中示出的工艺流程图中的步骤306。因此，金属柱50和焊料区54嵌入在聚合物层58中，其中，聚合物层58的顶面高于焊料区54的顶端。聚合物层58可以由选自聚合物层46的相同候选材料(诸如PBO)的材料形成。如图3所示，然后对晶圆20实施管芯锯切，并且半导体管芯22彼此分离。相应的步骤示出为图22中示出的工艺流程图中的步骤308。分离的半导体管芯22此后称为器件管芯22。
图4至图18示出了器件管芯22的封装以形成InFO结构，从而使得上面的电连接件(诸如焊料区)可以分布至大于器件管芯22的区域。图4示出了载体60和形成在载体60上的释放层62。载体60可以是玻璃载体、陶瓷载体等。载体60可以具有圆形顶视图形状和常用的硅晶圆的尺寸。例如，载体60可以具有8英寸的直径、12英寸的直径等。释放层62可以由聚合物基材料(诸如光热转换(LTHC)材料)形成，释放层62可以从在随后步骤中将形成的上面的结构与载体60一起去除。在一些实施例中，释放层62由环氧化物基热释放材料形成。在其他实施例中，释放层62由紫外(UV)胶形成。释放层62可以作为液体分配并且被固化。在可选实施例中，释放层62是层压膜并且层压在载体60上。释放层62的顶面是平坦的并且具有高度的共面性。
在释放层62上形成介电层64。在一些实施例中，介电层64由聚合物形成，该聚合物也可以是使用光刻工艺可以容易地图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。在可选实施例中，介电层64由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等形成。
参照图5，在介电层64上方形成再分布线(RDL)66。由于当完成封装时RDL 66位于器件管芯22的后侧上(图18)，因此RDL 66也称为后侧RDL。RDL 66的形成可以包括在介电层64上方形成晶种层(未示出)，在晶种层上方形成诸如光刻胶的图案化的掩模(未示出)，以及然后对暴露的晶种层实施金属镀。然后去除图案化的掩模和晶种层的由图案化的掩模覆盖的部分，从而留下如图5所示的RDL 66。根据一些实施例，晶种层包括钛层和位于钛层上方的铜层。例如，可以使用PVD形成晶种层。例如，可以使用化学镀实施该镀。
参照图6，在RDL 66上方形成介电层68。图4至图6中示出的步骤也示出为图22中示出的工艺流程图中的步骤310。介电层68的底面与RDL 66和介电层64的顶面接触。根据本发明的一些实施例，介电层68由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。在可选实施例中，介电层68由诸如氮化硅的氮化物、诸如氧化硅的氧化物、PSG、BSG、BPSG等形成。然后图案化介电层68以在介电层68中形成开口70。因此，通过介电层68中的开口70暴露RDL 66。
参照图7，形成金属柱72。贯穿说明书，由于金属柱72穿过随后形成的模制材料，所以金属柱72可选地称为通孔72。相应的步骤示出为图22中示出的工艺流程图中的步骤312。根据本发明的一些实施例，通过镀形成通孔72。镀通孔72可以包括在层68上方形成延伸至开口70(图6)内的毯状晶种层(未示出)，形成和图案化光刻胶(未示出)，以及在晶种层的通过光刻胶中的开口暴露的部分上镀通孔72。然后去除光刻胶和晶种层的由光刻胶覆盖的部分。通孔72的材料可以包括铜、铝等。通孔72具有杆的形状。通孔72的顶视图形状可以是圆形、矩形、正方形、六边形等。
图8示出了器件管芯22放置在图7中示出的结构上的立体图，其中，器件管芯22布置为行和列。相应的步骤示出为图22中示出的工艺流程图中的步骤314。放置在探测期间找到的良好管芯22，并且丢弃缺陷管芯22。虽然图8中未示出通孔72，但是它们也存在。
图9示出了图8中示出的结构的部分的截面图。在图9中，仅示出了单个器件管芯22和它周围的通孔72。然而，应该注意，图9至图17中示出的工艺步骤是在晶圆级上实施，并且对载体60上的所有器件管芯22均实施。参照图9，通过管芯附接膜(DAF)74将器件管芯22粘合至介电层68，DAF 74可以是粘合膜。
接下来，参照图10，将模制材料76模制在器件管芯22上。相应的步骤示出为图22中示出的工艺流程图中的步骤316。模制材料76填充相邻的通孔72之间的间隙以及通孔72和器件管芯22之间的间隙。模制材料76可以包括模塑料、模制底部填充物、环氧化物或树脂。模制材料76的顶面高于金属柱50和通孔72的顶端。
接下来，如图11所示，实施诸如化学机械抛光(CMP)步骤或研磨步骤的平坦化以减薄模制材料76，直到暴露通孔72和金属柱50。相应的步骤示出为图22中示出的工艺流程图中的步骤318。由于研磨，通孔72的顶端与金属柱50的顶面齐平(共面)，并且与模制材料76的顶面共面。在示出的示例性实施例中，实施平坦化，直到暴露金属柱50。因此，去除了焊料区54的与金属柱50重叠的部分。在平坦化之后，保留焊料区54的位于金属柱50的侧壁上的部分。在图11中示出的结构的顶视图中，剩余的焊料区54可以或可以不形成环绕相应的金属柱50的全环。
焊料区54的保留在金属柱50的侧壁上的部分的高度H1受到多种因素的影响，诸如回流持续时间、回流的温度、金属柱50的材料、焊料的量等。在一些示例性实施例中，比率H1/H2可以在约0.2和约0.5之间的范围内，其中，H2是金属柱50的高度。
图2至图17示出了前侧RDL和焊料区的形成。参照图12，形成介电层78。相应的步骤示出为图22中示出的工艺流程图中的步骤320。在一些实施例中，介电层78由诸如PBO、聚酰亚胺等的聚合物形成。在可选实施例中，介电层78由氮化硅、氧化硅等形成。在介电层78中形成开口79以暴露通孔72和金属柱50。可以通过光刻工艺实施开口79的形成。
接下来，参照图13，形成再分布线(RDL)80以连接至金属柱50和通孔72。RDL 80也可以互连金属柱50和通孔72。RDL 80包括位于介电层78上方的金属迹线(金属线)以及延伸至开口79(图12)内以电连接至通孔72和金属柱50的通孔。为了简化，未示出连接至最左和最右的金属柱50的金属线，然而也形成这些金属线。在一些实施例中，在镀工艺中形成RDL80，其中，每个RDL 80均包括晶种层(未示出)和位于晶种层上方的镀的金属材料。晶种层和镀的材料可以由相同材料或不同材料形成。RDL 80可以包括包含铝、铜、钨和它们的合金的金属或金属合金。RDL 80由非焊料材料形成。RDL 80的通孔部分可以与金属柱50的顶面物理接触。此外，RDL 80的通孔部分可以与焊料区54的顶面物理接触(例如，如果发生未对准)，或者与焊料区54物理分离(并且电连接至焊料区54)。
参照图14，在RDL 80和介电层78上方形成介电层82。可以使用聚合物形成介电层82，聚合物可以选自与介电层78的材料相同的候选材料。例如，介电层82可以包括PBO、聚酰亚胺、BCB等。可选地，介电层82可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅等的非有机介电材料。也在介电层82中形成开口84以暴露RDL 80。可以通过光刻工艺实施开口84的形成。
图15示出了RDL 86的形成，RDL 86电连接至RDL 80。RDL 86的形成可以采用与用于形成RDL 80的方法和材料类似的方法和材料。由于RDL 86和80位于器件管芯22的前侧上，所以RDL 86和80也称为前侧RDL。
如图16所示，形成额外的介电层88以覆盖RDL 86和介电层82，额外的介电层88可以是聚合物层。介电层88可以选自用于形成介电层78和82的相同的候选聚合物。然后在介电层88中形成开口90以暴露RDL 86的金属焊盘部分。
图17示出了根据一些示例性实施例的凸块下金属(UBM)92和电连接件94的形成。UBM 92的形成可以包括沉积和图案化。电连接件94的形成可以包括将焊球放置在UBM 92的暴露部分上以及然后回流焊球。在可选实施例中，电连接件94的形成包括实施镀步骤以在RDL 86上方形成焊料区以及然后回流焊料区。电连接件94也可以包括金属柱或者金属柱和焊帽，金属柱和焊帽也可以通过镀来形成。贯穿说明书，包括器件管芯22、通孔72、模制材料76和相应的RDL与介电层的组合结构将称为封装件100，封装件100可以是具有圆形顶视图形状的复合晶圆。
接下来，封装件100从载体60脱粘。相应的步骤示出为图22中示出的工艺流程图中的步骤322。也从封装件100清除释放层62。可以通过将诸如UV光或激光的光投射到释放层62上以分解释放层62来实施该脱粘。
在脱粘中，胶带(未示出)可以粘合至介电层88和电连接件94上。在随后的步骤中，从封装件100去除载体60和释放层62。实施管芯锯切步骤以将封装件100锯切成多个封装件，每个封装件均包括器件管芯22和通孔72。其中一个产生的封装件示出为图18中的封装件102。
图18示出了封装件102与另一封装件200的接合。相应的步骤示出为图22中示出的工艺流程图中的步骤324。根据本发明的一些实施例，通过焊料区98实施接合，焊料区98将RDL 66的金属焊盘部分连接至封装件200中的金属焊盘。在一些实施例中，封装件200包括器件管芯202，器件管芯202可以是诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。在一些示例性实施例中，存储器管芯也可以接合至封装衬底204。
图19至图21示出了根据本发明的可选实施例形成的封装件的截面图。除非另有说明，否则这些实施例中的组件的的材料和形成方法与相同组件基本上相同，在图1至图18中示出的实施例中，相同组件由相同的参考标号表示。因此，可以在图1至图18中示出的实施例的讨论中找到关于图19至图21中示出的组件的形成工艺和材料的细节。
除了焊料区54具有保持与金属柱50重叠的部分之外，图19中的封装件与图18中的封装件类似。这是由于在图11中的平坦化步骤中在完全去除焊料区54的与金属柱50重叠的部分之前停止平坦化而形成的。因此，在如图19所示的产生的结构中，焊料区54使RDL 80的通孔部分和下面的金属柱50彼此物理分离，并且将RDL 80电连接至相应的金属柱50。焊料区54的顶面也与通孔72、模制材料76和聚合物层58的顶面共面。
图20示出了根据可选实施例的封装件的截面图。除了RDL的通孔部分穿过焊料区54以接触至金属柱50的顶面之外，图20中示出的结构类似于图19中示出的结构。RDL 80的通孔部分可以由相应的焊料区54环绕。相应的形成工艺包括蚀刻步骤以当图案化介电层78时蚀刻穿过焊料区54。
图21示出了根据可选实施例的封装件的截面图。除了扩散阻挡层52形成在金属柱50的侧壁上并且使金属柱50与焊料区54分离之外，图21中示出的结构类似于图18中示出的结构。
本发明的实施例具有一些有利特征。通过在金属柱上形成焊料区，以及然后通过焊料区探测相应的器件管芯，提高了探测中的可靠性。
根据本发明的一些实施例，一种封装件包括器件管芯，器件管芯包括位于器件管芯的顶面处的金属柱和位于金属柱的侧壁上的焊料区。模制材料环绕器件管芯，其中，模制材料的顶面与器件管芯的顶面基本齐平。介电层与模制材料和器件管芯重叠，其中介电层的底面与器件管芯的顶面和模制材料的顶面接触。RDL延伸至介电层内以电连接至金属柱。
在上述封装件中，其中，所述封装件还包括：通孔，穿过所述模制材料，其中，所述通孔的顶面与所述器件管芯的顶面基本共面。
在上述封装件中，其中，所述RDL的底面与所述金属柱的顶面接触，并且所述焊料区的顶面与所述金属柱的顶面共面。
在上述封装件中，其中，所述RDL的底面与所述焊料区的顶面接触，并且所述焊料区包括与所述金属柱重叠的部分。
在上述封装件中，其中，所述RDL的通孔部分穿过所述焊料区的顶部以与所述金属柱的顶面接触。
在上述封装件中，其中，所述封装件还包括：扩散阻挡层，环绕所述金属柱，其中，所述扩散阻挡层与所述金属柱和所述焊料区物理接触，并且所述扩散阻挡层使所述金属柱和所述焊料区彼此分离。
在上述封装件中，其中，所述金属柱由非焊料金属材料形成。
在上述封装件中，其中，所述器件管芯还包括环绕所述金属柱的聚合物，其中，所述金属柱的侧壁的上部与所述焊料区物理接触，并且所述金属柱的侧壁的下部与所述聚合物物理接触。
根据本发明的可选实施例，一种封装件包括器件管芯，器件管芯包括衬底、位于器件管芯的表面处的金属柱、具有位于金属柱的侧壁上的部分并且电连接至金属柱的焊料区、以及环绕金属柱的聚合物层。金属柱和焊料区中的至少一个的顶面与聚合物层的顶面基本齐平，并且聚合物层与衬底共末端。封装件还包括环绕器件管芯的模制材料和穿过模制材料的通孔，其中模制材料的边缘与聚合物层的边缘接触。介电层位于器件管芯和模制材料上方。多条第一再分布线位于模制材料上面，其中，多条第一再分布线的第一条具有穿过介电层的通孔部分以与金属柱和焊料区中的至少一个的顶面接触。多条第二再分布线位于模制材料下面，其中，多条第一再分布线的第二条通过通孔电连接至多条第二再分布线中的一条。
在上述封装件中，其中，所述多条第一再分布线的所述第二条包括穿过所述介电层以与所述通孔接触的额外的通孔部分。
在上述封装件中，其中，所述多条第一再分布线的的所述第一条的所述通孔部分与所述金属柱的顶面物理接触。
在上述封装件中，其中，所述多条第一再分布线的的所述第一条的所述通孔部分与所述金属柱的顶面物理接触，其中，所述多条第一再分布线的的所述第一条的所述通孔部分与所述焊料区物理分离。
在上述封装件中，其中，所述多条第一再分布线的的所述第一条的所述通孔部分与所述焊料区的顶面物理接触，其中，所述焊料区的部分与所述金属柱重叠。
在上述封装件中，其中，所述多条第一再分布线的的所述第一条的所述通孔部分穿过所述焊料区以与所述金属柱物理接触，并且所述焊料区的顶面与所述聚合物层的顶面齐平。
根据本发明的又可选实施例，一种方法包括在器件管芯的金属柱的顶面和侧壁上形成焊料区，以及通过使探针与焊料区接触来探测器件管芯。在探测之后，将器件管芯模制在模制材料中。平坦化器件管芯和模制材料，其中，焊料区的顶面与模制材料的顶面齐平，并且去除焊料区的位于金属柱上方的至少部分。在器件管芯和模制材料上方形成与器件管芯和模制材料接触的介电层。形成再分布线，并且再分布线包括穿过介电层的通孔部分，其中，每个通孔部分均与焊料区和金属柱中的至少一个接触。
在上述方法中，其中，通过所述平坦化去除所述焊料区的位于所述金属柱的顶面上方的所有部分，并且所述再分布线的所述通孔部分与所述金属柱的顶面物理接触。
在上述方法中，其中，在所述平坦化之后，留下所述焊料区的与所述金属柱重叠的部分，并且所述再分布线的所述通孔部分与所述焊料区的剩余部分的顶面物理接触。
在上述方法中，其中，所述方法还包括：将通孔模制在所述模制材料中，其中，在所述平坦化之后，所述通孔的顶面与所述模制材料的顶面齐平，其中，其中一条所述再分布线包括穿过所述介电层的额外的通孔部分，并且所述额外的通孔部分与所述通孔的顶面接触。
在上述方法中，其中，所述方法还包括：在形成所述焊料区之后并且在所述探测之前，回流所述焊料区。
在上述方法中，其中，所述方法还包括：在所述探测之后，实施管芯锯切以将所述器件管芯与相应的晶圆的其他器件管芯分离。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体封装件，包括：
器件管芯，包括：
金属柱，位于所述器件管芯的顶面处；和
焊料区，位于所述金属柱的侧壁上；
模制材料，环绕所述器件管芯，其中，所述模制材料的顶面与所述器件管芯的顶面齐平；
介电层，与所述模制材料和所述器件管芯重叠，其中，所述介电层的底面与所述器件管芯的顶面和所述模制材料的顶面接触；以及
再分布线(RDL)，延伸至所述介电层内以电连接至所述金属柱。
2.根据权利要求1所述的半导体封装件，还包括：通孔，穿过所述模制材料，其中，所述通孔的顶面与所述器件管芯的顶面共面。
3.根据权利要求1所述的半导体封装件，其中，所述再分布线的底面与所述金属柱的顶面接触，并且所述焊料区的顶面与所述金属柱的顶面共面。
4.根据权利要求1所述的半导体封装件，其中，所述再分布线的底面与所述焊料区的顶面接触，并且所述焊料区包括与所述金属柱重叠的部分。
5.根据权利要求1所述的半导体封装件，其中，所述再分布线的通孔部分穿过所述焊料区的顶部以与所述金属柱的顶面接触。
6.根据权利要求1所述的半导体封装件，还包括：扩散阻挡层，环绕所述金属柱，其中，所述扩散阻挡层与所述金属柱和所述焊料区物理接触，并且所述扩散阻挡层使所述金属柱和所述焊料区彼此分离。
7.根据权利要求1所述的半导体封装件，其中，所述金属柱由非焊料金属材料形成。
8.根据权利要求1所述的半导体封装件，其中，所述器件管芯还包括环绕所述金属柱的聚合物，其中，所述金属柱的侧壁的上部与所述焊料区物理接触，并且所述金属柱的侧壁的下部与所述聚合物物理接触。
9.一种半导体封装件，包括：
器件管芯，包括：
衬底；
金属柱，位于所述器件管芯的表面处；
焊料区，具有位于所述金属柱的侧壁上的部分，并且所述焊料区电连接至所述金属柱；和
聚合物层，环绕所述金属柱，其中，所述金属柱和所述焊料区中的至少一个的顶面与所述聚合物层的顶面齐平，并且所述聚合物层与所述衬底共末端；
模制材料，环绕所述器件管芯，其中，所述模制材料的边缘与所述聚合物层的边缘接触；
通孔，穿过所述模制材料；
介电层，位于所述器件管芯和所述模制材料上方；
多条第一再分布线，位于所述模制材料上面，其中，所述多条第一再分布线的第一条具有穿过所述介电层的通孔部分以与所述金属柱和所述焊料区中的至少一个的顶面接触；以及
多条第二再分布线，位于所述模制材料下面，其中，所述多条第一再分布线的第二条通过所述通孔电连接至所述多条第二再分布线中的一条。
10.根据权利要求9所述的半导体封装件，其中，所述多条第一再分布线的所述第二条包括穿过所述介电层以与所述通孔接触的额外的通孔部分。
11.根据权利要求9所述的半导体封装件，其中，所述多条第一再分布线的所述第一条的所述通孔部分与所述金属柱的顶面物理接触。
12.根据权利要求11所述的半导体封装件，其中，所述多条第一再分布线的所述第一条的所述通孔部分与所述焊料区物理分离。
13.根据权利要求9所述的半导体封装件，其中，所述多条第一再分布线的所述第一条的所述通孔部分与所述焊料区的顶面物理接触，其中，所述焊料区的部分与所述金属柱重叠。
14.根据权利要求9所述的半导体封装件，其中，所述多条第一再分布线的所述第一条的所述通孔部分穿过所述焊料区以与所述金属柱物理接触，并且所述焊料区的顶面与所述聚合物层的顶面齐平。
15.一种用于形成半导体封装件的方法，包括：
在器件管芯的金属柱的顶面和侧壁上形成焊料区；
通过使探针与所述焊料区接触来探测所述器件管芯；
在所述探测之后，将所述器件管芯模制在模制材料中；
平坦化所述器件管芯和所述模制材料，其中，所述焊料区的顶面与所述模制材料的顶面齐平，并且去除所述焊料区的位于所述金属柱上方的至少部分；
在所述器件管芯和所述模制材料上方形成与所述器件管芯和所述模制材料接触的介电层；以及
形成再分布线，所述再分布线包括穿过所述介电层的通孔部分，其中，每个所述通孔部分均与所述焊料区和所述金属柱中的至少一个接触。
16.根据权利要求15所述的用于形成半导体封装件的方法，其中，通过所述平坦化去除所述焊料区的位于所述金属柱的顶面上方的所有部分，并且所述再分布线的所述通孔部分与所述金属柱的顶面物理接触。
17.根据权利要求15所述的用于形成半导体封装件的方法，其中，在所述平坦化之后，留下所述焊料区的与所述金属柱重叠的部分，并且所述再分布线的所述通孔部分与所述焊料区的剩余部分的顶面物理接触。
18.根据权利要求15所述的用于形成半导体封装件的方法，还包括：
将通孔模制在所述模制材料中，其中，在所述平坦化之后，所述通孔的顶面与所述模制材料的顶面齐平，其中，其中一条所述再分布线包括穿过所述介电层的额外的通孔部分，并且所述额外的通孔部分与所述通孔的顶面接触。
19.根据权利要求15所述的用于形成半导体封装件的方法，还包括：在形成所述焊料区之后并且在所述探测之前，回流所述焊料区。
20.根据权利要求15所述的用于形成半导体封装件的方法，还包括：
在所述探测之后，实施管芯锯切以将所述器件管芯与相应的晶圆的其他器件管芯分离。
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