CN110416095A - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN110416095A
CN110416095A CN201811592443.9A CN201811592443A CN110416095A CN 110416095 A CN110416095 A CN 110416095A CN 201811592443 A CN201811592443 A CN 201811592443A CN 110416095 A CN110416095 A CN 110416095A
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Prior art keywords
dielectric layer
top surface
redistribution lines
layer
seed layer
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CN201811592443.9A
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CN110416095B (zh
Inventor
王博汉
胡毓祥
郭宏瑞
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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Abstract

方法包括在载体上方形成缓冲介电层，以及在缓冲介电层上方形成第一介电层和第一再分布线。第一再分布线位于第一介电层中。该方法还包括对第一介电层实施平坦化以使第一介电层的顶面齐平，在第一再分布线上方形成电连接至第一再分布线的金属桩，并且将金属桩密封在密封材料中。密封材料接触第一介电层的平坦化顶面的顶面。本发明的实施例还涉及封装件及其形成方法。

Description

封装件及其形成方法
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
随着半导体技术的进步，半导体芯片/管芯变得越来越小。同时，更多功能需要集成在半导体管芯内。因此，半导体管芯需要将越来越多的I/O焊盘封装至更小的区域内，并且，I/O焊盘的密度随着时间迅速上升。因此，半导体管芯的封装变得更加困难，这对封装件的良率产生不利的影响。
传统的封装技术可以划分为两类。在第一类中，晶圆上的管芯在它们被锯切之前封装。这种封装技术具有一些有利的特征，诸如更大的生产量和更低的成本。此外，需要较少的底部填充物或模塑料。然而，这种封装技术还具有缺陷。由于管芯的尺寸变得越来越小，并且相应的封装件仅可以是扇入型封装件，其中，每个管芯的I/O焊盘限制于相应的管芯的表面正上方的区域。由于管芯的面积有限，I/O焊盘的数量由于I/O焊盘的间距的限制而受到限制。如果焊盘的间距减小，则可能发生焊料桥接。此外，在固定的焊球尺寸需求下，焊球必须具有特定的尺寸，这进而限制可以封装在管芯表面上的焊球的数量。
在另一类封装件中，在封装管芯之前从晶圆锯切管芯。该封装技术的有利特征是可能形成扇出封装件，这意味着管芯上的I/O焊盘可以分布至比管芯更大的区域，并且因此可以增加封装在管芯的表面上的I/O焊盘的数量。该封装技术的另一有利特征是封装“已知良好管芯”，以及丢弃缺陷管芯，并且因此不会在缺陷管芯上浪费成本和精力。
在扇出封装件中，将器件管芯密封在模塑料中，之后平坦化模塑料以暴露器件管芯。之后，形成再分布线以连接至器件管芯。扇出封装件也可以包括穿透模塑料的通孔。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：在载体上方形成缓冲介电层，在所述缓冲介电层上方形成第一介电层和第一再分布线，其中，所述第一再分布线位于所述第一介电层中；对所述第一介电层实施平坦化以使所述第一介电层的顶面齐平，从而形成所述第一介电层的平坦化顶面；在所述第一再分布线上方形成金属桩，其中，所述金属桩电连接至所述第一再分布线；以及将所述金属桩密封在密封材料中，其中，所述密封材料接触所述第一介电层的所述平坦化顶面。
本发明的另一实施例提供了一种形成封装件的方法，包括：在载体上方形成缓冲介电层；在所述载体上方形成第一介电层；在所述第一介电层中形成第一开口和第二开口；在所述第一开口和所述第二开口中分别形成第一再分布线和第二再分布线；平坦化所述第一介电层的顶面，从而形成所述第一介电层的平坦化顶面；通过粘合膜将器件管芯附接至所述第一介电层的顶面，其中，所述粘合膜与所述第一介电层的所述平坦化顶面和所述第一再分布线的顶面物理接触；以及将所述器件管芯密封在密封材料中。
本发明的又一实施例提供了一种封装件，包括：第一介电层；第一再分布线和第二再分布线，位于所述第一介电层中；粘合膜，位于所述第一介电层的顶面和所述第一再分布线的顶面上方并且接触所述第一介电层的顶面和所述第一再分布线的顶面；器件管芯，位于所述粘合膜上方并且粘合至所述粘合膜；以及密封材料，将所述器件管芯密封在所述密封材料中，其中，所述密封材料接触所述第一介电层的顶面。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图13A示出了根据一些实施例的在封装件的形成中的中间阶段的截面图。
图13B示出了根据一些实施例的封装件的截面图。
图14至图23示出了根据一些实施例的在封装件的形成中的中间阶段的截面图。
图24示出了根据一些实施例的用于形成封装件的工艺流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例，提供了扇出封装件和及其形成方法。根据一些实施例示出了形成封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。
图1至图13A示出了根据本发明的一些实施例的在封装件的形成中的中间阶段的截面图。在图1至图13A所示的步骤也在图24所示的工艺流程200中示意性地示出。
图1示出了载体20和形成在载体20上的释放膜22。载体20可以是玻璃载体、硅晶圆、有机载体等。载体20可以具有圆形俯视图形状并且可以具有普通硅晶圆的尺寸。例如，载体20可以具有8英寸的直径、12英寸的直径等。释放膜22可以由基于聚合物的材料(诸如光热转换(LTHC)材料)形成，释放膜22可以与载体20一起从将在随后步骤中形成的上面的结构去除。根据本发明的一些实施例，释放膜22由环氧树脂基热释放材料形成。可以将释放膜22涂覆到载体20上。释放膜22的顶面是平坦的并且具有高度共面性。
在释放膜22上形成缓冲介电层24。根据本发明的一些实施例，缓冲介电层24由聚合物形成，该聚合物也可以是可以通过曝光和显影来图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。例如，通过烘烤工艺固化缓冲介电层24。根据本发明的可选实施例，介电层24由诸如氧化硅、氮化硅、氮氧化硅、碳氮氧化硅等的无机材料形成。
下一步，在介电层24上方形成介电层26。根据本发明的一些实施例，介电层26由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。根据本发明的可选实施例，介电层26由诸如氧化硅、氮化硅、氮氧化硅、碳氮氧化硅等的无机材料形成。介电层26可以具有大于约3μm的厚度。该厚度可以在约3μm和约10μm之间的范围内。介电层24和26可以由相同的介电材料或不同的介电材料形成。此外，介电层24和26之间可能存在或可能不存在可区分的界面。
进一步参照图1，图案化介电层26以形成开口28。相应的工艺示出为图24所示的工艺流程中的工艺202。根据本发明的一些实施例，介电层26由光敏材料形成，并且图案化包括使用光刻掩模曝光介电层26，并且之后显影曝光的介电层26。应该理解，当介电层24和26由相同的光敏材料形成时，由于介电层24已经被充分地烘烤，因此曝光和显影将不会引起介电层24的图案化。根据本发明的可选实施例，介电层26的图案化包括光刻工艺，光刻工艺进一步包括在介电层26上方形成图案化的光刻胶，并且使用图案化的光刻胶作为蚀刻掩模来蚀刻介电层26。
参照图2，例如，通过物理汽相沉积(PVD)来形成金属晶种层30。相应的工艺示出为图24所示的工艺流程中的工艺204。沉积使得形成延伸至开口28内的毯式金属晶种层30。金属晶种层30形成为毯式层，其可以包括粘合层(也称为扩散阻挡层)和位于粘合层上方的含铜层。粘合层包括与铜不同的金属，并且可以包括钛、钽、氮化钛、氮化钽等。含铜层可以由纯或基本纯(例如，具有大于约95％的百分比)的铜或铜合金形成。根据本发明的可选实施例，金属晶种层30包括钛、钽、氮化钛、氮化钽等，并且不包括含铜层。
图3示出了金属材料32的沉积。相应的工艺示出为图24所示的工艺流程中的工艺206。根据一些实施例，通过诸如电化学镀(ECP)工艺或化学镀工艺的镀工艺、物理汽相沉积工艺或化学汽相沉积工艺来沉积金属材料32。金属材料32可以由纯或基本纯(例如，具有大于约95％的百分比)的铜或铜合金形成。
参照图4，实施诸如化学机械抛光(CMP)工艺或机械抛光工艺的平坦化工艺。因此去除晶种层30和金属材料32的位于介电层26的顶面上方的过量部分。相应的工艺示出为图24所示的工艺流程中的工艺208。晶种30和金属材料32的剩余部分称为再分布线(RDL)34。RDL 34可以包括金属迹线和金属焊盘，这取决于RDL 34的相应部分是用于电路由的目的还是接合/连接的目的。因此，晶种层30、金属材料32和介电层26的顶面和顶部边缘共面。
由于平坦化工艺，RDL 34和介电层26的顶面可以具有抛光标记，抛光标记是延伸至RDL 34和介电层26内的划痕(条形空隙)。抛光标记表示已经对RDL 34和介电层26实施了平坦化工艺。
图5和图6示出了金属桩42(图6)的形成。参照图5，例如，通过物理汽相沉积(PVD)形成金属晶种层36。相应的工艺示出为图24所示的工艺流程中的工艺210。金属晶种层36形成为毯式层和平面层。金属晶种层36也可以包括粘合层和位于粘合层上方的含铜层。粘合层包括与铜不同的金属，并且可以包括钛、钽、氮化钛、氮化钽等。含铜层可以由纯或基本纯的铜(例如，铜的百分比大于约95％)或铜合金形成。
在金属晶种层36上方形成图案化的光刻胶38。相应的工艺示出为图24所示的工艺流程中的工艺212。之后使用光刻掩模对光刻胶38实施曝光，以及随后进行显影步骤以形成开口41，金属晶种层36通过开口41暴露。
下一步，例如通过在开口41中镀金属材料来形成金属桩40。相应的工艺示出为图24所示的工艺流程中的工艺212。镀的金属材料可以是铜或铜合金。金属桩40的顶面低于光刻胶38的顶面，使得金属桩40的形状由开口41限制。金属桩40可以具有基本垂直并且直的边缘。可选地，金属桩40的截面图可以具有沙漏形状，其中，金属桩40的中间部分比相应的顶部分和底部分窄。
在随后的步骤中，去除图案化的光刻胶38，并且因此暴露下面的金属晶种层36的部分。之后，在例如各向异性蚀刻步骤或各向同性蚀刻步骤的蚀刻步骤中去除金属晶种层36的暴露部分。相应的工艺示出为图24所示的工艺流程中的工艺214。产生的结构如图6所示。因此，剩余的晶种层36的边缘可以与相应的上面的金属桩40的部分齐平或基本齐平，或可以从上面的金属桩40的部分的相应边缘横向凹进，因此具有底切。产生的金属桩40在图6中示出。金属桩40和下面的金属晶种层36的剩余部分统称为金属桩42。金属桩42的俯视形状包括但不限于圆形、矩形、六边形、八边形等。由于金属桩42将穿透最终封装件中的随后形成的密封材料(其可以是模塑料)，因此金属桩42可以可选地称为通孔或模制通孔。在金属桩42的形成之后，再次暴露顶部介电缓冲层26。
在金属晶种层36的蚀刻期间，可以形成凹槽44，凹槽44是RDL 34中的金属晶种层30中的粘合层的蚀刻的结果。例如，当金属晶种层30和金属晶种层36包括相同或类似的材料(诸如钛)时，包括过蚀刻以确保去除金属晶种层36的不期望部分的金属晶种层36的蚀刻也在金属晶种层30中的粘合层的顶部边缘部分产生凹槽。凹槽44可以具有大于约0.2μm的深度，并且该深度可以在约0.2μm和约0.5μm之间的范围内。当在金属晶种层36的蚀刻期间，金属晶种层30和金属晶种层36的材料不同并且具有高蚀刻选择性时，可以不形成凹槽。在金属晶种层30的暴露于蚀刻的部分上形成凹槽44，而未蚀刻金属晶种层30的由金属桩42保护的部分，并且没有形成凹槽。
图7示出了器件46(可选地称为封装组件)的放置/附接。相应的工艺示出为图24所示的工艺流程中的工艺216。器件46可以是器件管芯，并且因此在下文中称为器件管芯46，而器件46也可以是封装件、管芯堆叠件等。器件管芯46通过管芯附接膜(DAF)48附接至介电层26和RDL 34，该管芯附接膜是在将器件管芯46放置在介电层26上之前预先附接在器件管芯46上的粘合膜。DAF 48可以与从其锯切器件管芯46的晶圆一起锯切，并且因此DAF 48的边缘与器件管芯46的相应边缘齐平。器件管芯46可以包括半导体衬底，该半导体衬底具有与相应的下面的DAF 48物理接触的背面(面朝下的表面)。器件管芯46可以包括诸如有源器件的集成电路器件，集成电路器件包括位于半导体衬底的正面(面朝上的表面)处的晶体管。根据本发明的一些实施例，器件管芯46包括一个或多个逻辑管芯，其可以是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯、微控制单元(MCU)管芯、输入输出(IO)管芯、基带(BB)管芯或应用处理器(AP)管芯。因为载体20是晶圆级载体，所以虽然示出了一个器件管芯46，但是可以在管芯放置步骤中将多个器件管芯46放置在介电层26上方，并且可以将器件管芯分配为包括多行和多列的阵列。
根据一些示例性实施例，金属柱50(诸如铜柱)预形成为器件管芯46的一部分，并且金属柱50通过下面的金属焊盘51电连接至集成电路器件(诸如器件管芯46中的晶体管)，下面的金属焊盘51可以是例如铝铜焊盘。根据本发明的一些实施例，诸如聚合物层52的介电层填充相邻金属柱50之间的间隙以形成顶部介电层。顶部介电层52也可以包括覆盖和保护金属柱50的部分。根据本发明的一些实施例，聚合物层52可以由PBO或聚酰亚胺形成。
根据本发明的一些实施例，由于如图4所示的平坦化工艺，晶种层30、金属材料32和介电层26的顶面和顶部边缘共面，并且因此DAF 48粘合至平坦顶面。在DAF 48和下面的结构之间没有形成空隙(其可以是气隙)。这改进了产生的封装件的可靠性。作为比较，如果没有实施平坦化，则将DAF 48放置在诸如图17所示的非平坦顶面上，在DAF 48和下面的结构之间将形成空隙(气隙)，并且封装件的可靠性受损。
下一步，参照图8，将器件管芯46和金属桩42密封在密封材料54中。相应的工艺示出为图24所示的工艺流程中的工艺218。金属桩42穿透密封料54，并且在下文中称为通孔。密封材料54填充相邻通孔42之间的间隙以及通孔42和器件管芯46之间的间隙。密封材料54可以是模塑料、模制底部填充物、环氧树脂和/或树脂。在密封之后，密封材料54的顶面高于金属柱50和通孔42的顶端。密封材料54可以包括基材料54A(其可以是聚合物、树脂、环氧树脂等)和基材料54A中的填料颗粒54B。填料颗粒可以是诸如SiO2、Al2O3、硅石等的介电材料的颗粒，并且可以具有球形形状。同样，如根据一些实例示出的，球形填料颗粒54B可以具有相同或不同的直径。根据一些实施例，一些凹槽44(未示出)未由DAF 48覆盖。这些凹槽44可以由密封材料54填充，或可以部分地填充并且留下一些剩余的气隙。
在随后的步骤中，同样如图8所示，实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺，以减薄密封材料54和介电层52，直至通孔42和金属柱50全部暴露。也可以轻微抛光通孔42和金属柱50以确保通孔42和金属柱50的暴露。由于平坦化工艺，通孔42的顶端与金属柱50的顶面齐平(共面)或基本齐平，并且与密封材料54的顶面基本共面。由于平坦化工艺，部分抛光了模制密封材料54的顶部处的一些填料颗粒54B，使得一些填料颗粒的顶部被去除，并且底部保留，如图8中的54B-1所示。因此，产生的部分填料颗粒54B-1将具有平坦顶面，该平坦顶面与基材料54A、通孔42和金属柱50的顶面共面。
图9至图11示出了前侧RDL的形成。相应的工艺示出为图24所示的工艺流程中的工艺220。参照图9，形成介电层56。根据本发明的一些实施例，介电层56由诸如聚合物的有机介电材料形成，该聚合物可以是PBO、聚酰亚胺等。根据本发明的可选实施例，介电层56由诸如氮化硅、氧化硅等的无机介电材料形成。在介电层56中形成开口58以暴露通孔42和金属柱50。可以通过光刻工艺(利用光刻胶蚀刻以限定图案)，或曝光工艺以及随后的显影工艺来形成开口58。
下一步，参照图10，形成连接至金属柱50和通孔42的RDL 60。RDL 60也可以互连金属柱50和通孔42。RDL 60包括位于介电层56上方的金属迹线(金属线)以及延伸至开口58(图9)内以电连接至通孔42和金属柱50的通孔。根据本发明的一些实施例，在镀工艺中形成RDL 60，其中，每个RDL 60均包括晶种层和位于晶种层上方的镀金属材料。晶种层和镀材料可以由相同的材料或不同的材料形成。RDL 60可以包括金属或金属合金(包括铜、铝、钨以及它们的合金)。RDL 60由非焊料材料形成。
进一步参照图10，在RDL 60和介电层56上方形成介电层62。介电层62可以使用有机材料形成，该有机材料可以选自与介电层56的那些相同的候选材料。例如，介电层62可以包括PBO、聚酰亚胺、BCB等。可选地，介电层62可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅等的非有机介电材料。开口64也形成在介电层62中以暴露RDL 60。可以通过光刻工艺形成开口64。根据本发明的一些实施例，未平坦化介电层62，并且介电层62的顶面是非平坦的。例如，虚线62A示意性地示出了介电层62的顶面的拓扑结构。在随后的附图中，为了简单起见，介电层62的顶面示出为平坦的，而实际的顶面可以是非平坦的。
图11示出了电连接至RDL 60的RDL 66的形成。RDL 66的形成可以采用与用于形成RDL 60的那些类似的方法和材料。RDL 66和60也称为前侧RDL，因为它们位于器件管芯46的前侧上。
如图11所示，形成额外的介电层68以覆盖RDL 66和介电层62。介电层68可以由选自用于形成介电层62和56的相同的候选材料的材料形成。之后，在介电层68中形成开口70以暴露RDL 66的金属焊盘部分。根据一些实施例，由于没有器件管芯通过DAF粘合在介电层62和68上方，所以未平坦化介电层62和68，并且介电层62和68的顶面是非平坦的，其与图10中的介电层62的示意性示出的顶部非平坦顶面62A类似。
图12示出了根据一些示例性实施例的凸块下金属(UBM)72和电连接件74的形成。相应的工艺示出为图24所示的工艺流程中的工艺222。UBM 72的形成可以包括沉积工艺和图案化工艺。电连接件74的形成可以包括将焊球放置在UBM 72的暴露部分上，并且之后回流焊球。根据本发明的可选实施例，电连接件74的形成包括实施镀步骤以在UBM 72上方形成焊料区域，并且之后回流焊料区域。电连接件74也可以包括金属柱或金属柱和焊料帽的组合结构，电连接件74也可以通过镀形成。在整个描述中，包括器件管芯46、通孔42、模制材料54以及对应的RDL和介电层的组合结构称为封装件100，封装件100可以是具有圆形俯视图形状的复合晶圆。
下一步，将封装件100与载体20分离。将复合晶圆100放置在带上，使得复合晶圆100可以从载体20卸下，例如通过将光(诸如激光束)投射到释放膜22上，并且光穿透透明载体20。因此，分解释放膜22，并且复合晶圆100从载体20释放。
参照图13A，在介电缓冲层24中形成开口(由焊料区域84占据)，并且因此暴露RDL34的金属晶种层30。根据本发明的一些实施例，通过激光钻孔形成开口。根据本发明的可选实施例，通过光刻工艺中的蚀刻形成开口。之后蚀刻穿过金属晶种层30中的粘合层，露出金属材料32。
复合晶圆100包括多个彼此相同的封装件76，其中，每个封装件76均包括多个通孔42和一个或多个器件管芯46。图13A也示出了将封装件78接合在封装件76上，从而形成叠层封装(PoP)结构/封装件88。通过焊料区域74实施接合。根据本发明的一些实施例，封装件78包括封装衬底82和器件管芯80，器件管芯80可以是诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。底部填充物83也设置在封装件78和下面的封装件76之间的间隙中，并且被固化。实施分割(管芯锯切)工艺以将复合晶圆100和其上接合的封装件78分离成彼此相同的单独的封装件88。
图13A也示出了分割的封装件88通过焊料区域84接合至封装组件90。根据本发明的一些实施例，封装组件90是封装衬底，其可以是无芯衬底或具有芯(诸如玻璃纤维增强芯)的衬底。根据本发明的其它实施例，封装组件90是印刷电路板或封装件。下文将图13A中的封装件称为封装件92。
图13B示出了根据本发明的可选实施例的封装件92。这些实施例与图13A所示的实施例类似，除了通孔42可以比下面的RDL 34更窄之外。因此，金属晶种层30的顶部边缘与模制材料54接触。在一些实施例中，金属晶种层30的顶部边缘在图6所示的步骤中凹进。因此，凹槽44(如虚线所示)形成为延伸至粘合层的顶部内，并且凹槽44延伸至晶种层30的顶部内。
图13B示出了具有倒梯形轮廓的RDL 34的截面图。根据可选实施例，RDL 34的截面图可以具有如虚线96A示出的垂直边缘，虚线96A表示对应的RDL 34的侧壁。根据另外的可选实施例，RDL 34的截面图可以具有如虚线96B示出的梯形轮廓，虚线96B表示对应的RDL34的侧壁。
图14至图23示出了根据本发明的可选实施例形成的封装件的截面图。除非另有说明，否则这些实施例中的组件的材料和形成方法与图1至图13A和图13B所示的实施例中的由相同参考标号表示的相同组件基本相同。因此，可以在图1至图13A/图13B所示的实施例的讨论中找到关于图14至图23所示的组件的形成工艺和材料的细节。
参照图14，在载体20上形成释放膜22，并且在释放膜22上方形成介电层24。之后，在介电层24上形成金属晶种层110。金属晶种层110可以具有与金属晶种层30(图2)类似的结构和形成的材料。例如，金属晶种层110可以包括粘合层和位于粘合层上方的含铜层。
参照图15，在金属晶种层110上方形成图案化的光刻胶112，并且露出金属晶种层110的一些部分。之后，例如通过镀在光刻胶112的开口中形成RDL 114。RDL 114可以由铜、铝、铝铜等形成。在形成RDL 114之后，去除光刻胶112，并且蚀刻金属晶种层110的先前由光刻胶112覆盖的部分。产生的结构如图16所示。在整个描述中，RDL 114和下面的金属晶种层110的剩余部分的组合称为RDL 116。RDL 116可以具有大于约3μm的厚度。该厚度可以在约3μm和约10μm之间的范围内。
图17示出了介电层118的形成。根据本发明的一些实施例，介电层118由聚合物形成，该聚合物也可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。根据本发明的可选实施例，介电层118由诸如氧化硅、氮化硅、氮氧化硅、碳氮氧化硅等的无机材料形成。
由于RDL 116突出高于介电层24，因此介电层118的顶面是非平坦的。如果器件管芯通过DAF粘合至介电层118的非平坦顶面的顶面，则将在DAF和介电层118之间形成空隙，并且不利地影响了封装件的可靠性。根据本发明的一些实施例，如图18所示，实施诸如CMP或机械研磨工艺的平坦化工艺以平坦化介电层118的顶面。
参照图19，例如通过蚀刻工艺在介电层118中形成开口120。因此，暴露RDL 116的一些部分。下一步，如图20所示，形成金属晶种层122。形成方法和材料可以选自用于形成金属晶种层36(图5)的相同的候选方法和材料的组。之后形成图案化的光刻胶124以及随后在光刻胶124中的开口中镀金属材料40。
在随后的步骤中，去除光刻胶124，并且蚀刻金属晶种层122的先前由光刻胶124覆盖的部分，从而形成如图21所示的金属桩(通孔)42。金属桩42包括金属材料40(其可以由铜或铜合金形成)以及下面的金属晶种层122的剩余部分。还与金属桩42同时形成通孔126。通孔126位于介电层118中，并且将金属桩42电连接至RDL 116。
图22示出了通过DAF 48将器件管芯46附接至平坦化的介电层118。下一步，将器件管芯46和金属桩42密封在密封材料54中，随后是诸如CMP工艺或机械研磨工艺的平坦化工艺以使器件管芯46和金属桩42的顶面齐平。在下文中，金属桩42可选地称为通孔42。在随后的工艺中，实施与图9至图13A所示那些类似的剩余工艺以形成图23所示的上面的结构。上面的结构包括RDL 60和66、介电层56、62和68、UBM 72以及电连接件74。接合封装组件78，并且实施管芯锯切以形成与示出的PoP封装件88相同的多个PoP封装件。将PoP封装件88接合至封装组件90，形成图23所示的封装件92。
在上述示例性实施例中，根据本发明的一些实施例讨论了一些示例性工艺和部件。也可以包括其它部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘以允许使用探针和/或探针卡等测试3D封装件或3DIC。可以对中间结构以及最终结构实施验证测试。此外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合以增加良率并且降低成本。
本发明的实施例具有一些有利特征。通过对介电层和RDL实施平坦化工艺，形成用于将器件管芯和DAF附接在其上的平坦顶面，并且因此在DAF和下面的介电层之间没有形成空隙(气隙)。改进了封装件的可靠性。
根据本发明的一些实施例，方法包括：在载体上方形成缓冲介电层，以及在缓冲介电层上方形成第一介电层和第一再分布线。第一再分布线位于第一介电层中。该方法还包括对第一介电层实施平坦化以使第一介电层的顶面齐平，在第一再分布线上方形成电连接至第一再分布线的金属桩，并且将金属桩密封在密封材料中。密封材料接触第一介电层的平坦化顶面的顶面。在实施例中，该方法包括在密封材料和金属桩上方形成接触密封材料和金属桩的第二介电层；形成第二再分布线，第二再分布线包括延伸至第二介电层内以连接至金属桩的通孔部分；在第二介电层和第二再分布线上方形成第三介电层，其中，未平坦化第三介电层；以及在第三介电层的非平坦顶面上方形成接触第三介电层的非平坦顶面的第四介电层。在实施例中，形成第一再分布线包括：在第一介电层中形成开口；形成延伸至开口内的第一晶种层；在第一晶种层上方形成第一金属材料；以及平坦化第一金属材料、第一晶种层和第一介电层。在实施例中，形成金属桩包括：在第一介电层和第一再分布线上方形成接触第一介电层和第一再分布线的第二晶种层；在第二晶种层上方形成图案化的光刻胶；在第二晶种层上方以及图案化的光刻胶中的开口中镀第二金属材料；以及去除图案化的光刻胶以及第二晶种层的位于去除的图案化的光刻胶正下面的部分。在实施例中，形成第一再分布线包括在缓冲介电层上方形成接触缓冲介电层的第一晶种层；在第一晶种层上方形成图案化的光刻胶；在第一晶种层上方和图案化的光刻胶中的开口中镀金属材料；以及去除图案化的光刻胶以及第一晶种层的位于去除的图案化的光刻胶正下面的部分，其中，在去除图案化的光刻胶和第一晶种层的部分之后形成第一介电层。在实施例中，在平坦化之后，整个第一再分布线位于第一介电层的平坦化顶面的顶面之下。在实施例中，在用于形成第一再分布线的同一工艺中形成第三再分布线，并且该方法还包括通过粘合膜将器件管芯附接至第一介电层，其中，粘合膜物理接触第一介电层的顶面和第三再分布线的顶面。在实施例中，形成金属桩使得凹槽形成在第一再分布线的阻挡层的顶部边缘部分中。
根据本发明的一些实施例，方法包括：在载体上方形成缓冲介电层；在载体上方形成第一介电层；在第一介电层中形成第一开口和第二开口；在第一开口和第二开口中分别形成第一再分布线和第二再分布线；平坦化第一介电层的顶面；通过粘合膜将器件管芯附接至第一介电层的顶面，其中，粘合膜与第一介电层的平坦化顶面和第一再分布线的顶面物理接触；以及将器件管芯密封在密封材料中。在实施例中，方法还包括在第二再分布线上方形成接触第二再分布线的金属桩，形成金属桩包括：在第一介电层、第一再分布线和第二再分布线上方形成接触第一介电层、第一再分布线和第二再分布线的金属晶种层；在金属晶种层上镀金属材料；以及去除金属晶种层的不期望的部分，其中，去除接触第一再分布线的所有金属晶种层。在实施例中，金属桩与第二再分布线的第一部分重叠并且接触，并且密封材料与第二再分布线的第二部分重叠并且接触。在实施例中，形成金属桩使得凹槽形成在第一再分布线的阻挡层的顶部边缘部分中。在实施例中，密封材料接触第一再分布层的平坦化顶面的顶面。在实施例中，在平坦化中，平坦化第一介电层、第一再分布线和第二再分布线。
根据本发明的一些实施例，器件包括第一介电层；位于第一介电层中的第一再分布线和第二再分布线；位于第一介电层的顶面和第一再分布线的顶面上方并且接触第一介电层的顶面和第一再分布线的顶面的粘合膜；位于粘合膜上方并且粘合至粘合膜的器件管芯；以及将器件管芯密封在其中的密封材料，其中，密封材料接触第一介电层的顶面。在实施例中，器件还包括在第二再分布线的顶面上方并且接触第二再分布线的顶面的通孔，其中，通孔密封在密封材料中，其中，通孔包括扩散阻挡层和位于扩散阻挡层上方的金属材料，并且整个扩散阻挡层是平坦的。在实施例中，通孔比第二再分布线宽，并且扩散阻挡层在第一介电层的顶面上延伸。在实施例中，通孔比第二再分布线窄，并且密封材料接触第二再分布线的顶面。在实施例中，该器件还包括位于密封材料上方的第二介电层；第二再分布线，包括延伸至第二介电层内以连接至器件管芯的通孔部分；以及位于第二介电层和第二再分布线上方的第三介电层，其中，第三介电层具有非平坦顶面，该非平坦顶面的拓扑结构跟随下面的部件的拓扑结构。在实施例中，第一再分布线具有扩散阻挡层，并且扩散阻挡层的顶部边缘凹进低于第一介电层的顶面。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成封装件的方法，包括：
在载体上方形成缓冲介电层，
在所述缓冲介电层上方形成第一介电层和第一再分布线，其中，所述第一再分布线位于所述第一介电层中；
对所述第一介电层实施平坦化以使所述第一介电层的顶面齐平，从而形成所述第一介电层的平坦化顶面；
在所述第一再分布线上方形成金属桩，其中，所述金属桩电连接至所述第一再分布线；以及
将所述金属桩密封在密封材料中，其中，所述密封材料接触所述第一介电层的所述平坦化顶面。
2.根据权利要求1所述的方法，还包括：
在所述密封材料和所述金属桩上方形成接触所述密封材料和所述金属桩的第二介电层；
形成第二再分布线，所述第二再分布线包括延伸至所述第二介电层内以连接至所述金属桩的通孔部分；
在所述第二介电层和所述第二再分布线上方形成第三介电层，其中，所述第三介电层未被平坦化并且包括非平坦顶面；以及
在所述第三介电层的非平坦顶面上方形成接触所述第三介电层的非平坦顶面的第四介电层。
3.根据权利要求1所述的方法，其中，形成所述第一再分布线包括：
在所述第一介电层中形成开口；
形成延伸至所述开口内的第一晶种层；
在所述第一晶种层上方形成第一金属材料；以及
平坦化所述第一金属材料、所述第一晶种层和所述第一介电层。
4.根据权利要求3所述的方法，其中，形成所述金属桩包括：
在所述第一介电层和所述第一再分布线正上方形成第二晶种层；
在所述第二晶种层上方形成图案化的光刻胶；
在所述第二晶种层上方以及所述图案化的光刻胶中的开口中镀第二金属材料；以及
去除所述图案化的光刻胶以及所述第二晶种层的位于所述图案化的光刻胶正下面的部分。
5.根据权利要求3所述的方法，其中，形成所述金属桩使得凹槽形成在所述第一介电层中的所述开口中的所述第一晶种层的顶部边缘部分中。
6.根据权利要求1所述的方法，其中，形成所述第一再分布线包括：
在所述缓冲介电层上方形成接触所述缓冲介电层的第一晶种层；
在所述第一晶种层上方形成图案化的光刻胶；
在所述第一晶种层上方和所述图案化的光刻胶中的开口中镀金属材料；以及
去除所述图案化的光刻胶以及所述第一晶种层的位于所述图案化的光刻胶正下面的部分，其中，在去除所述图案化的光刻胶和所述第一晶种层的部分之后形成所述第一介电层。
7.根据权利要求6所述的方法，其中，在所述平坦化之后，整个所述第一再分布线位于所述第一介电层的所述平坦化顶面的顶面之下。
8.根据权利要求1所述的方法，其中，在用于形成所述第一再分布线的相同工艺中形成第三再分布线，并且所述方法还包括：
通过粘合膜将器件管芯附接至所述第一介电层，其中，所述粘合膜物理接触所述第一介电层的顶面和所述第三再分布线的顶面。
9.一种形成封装件的方法，包括：
在载体上方形成缓冲介电层；
在所述载体上方形成第一介电层；
在所述第一介电层中形成第一开口和第二开口；
在所述第一开口和所述第二开口中分别形成第一再分布线和第二再分布线；
平坦化所述第一介电层的顶面，从而形成所述第一介电层的平坦化顶面；
通过粘合膜将器件管芯附接至所述第一介电层的顶面，其中，所述粘合膜与所述第一介电层的所述平坦化顶面和所述第一再分布线的顶面物理接触；以及
将所述器件管芯密封在密封材料中。
10.一种封装件，包括：
第一介电层；
第一再分布线和第二再分布线，位于所述第一介电层中；
粘合膜，位于所述第一介电层的顶面和所述第一再分布线的顶面上方并且接触所述第一介电层的顶面和所述第一再分布线的顶面；
器件管芯，位于所述粘合膜上方并且粘合至所述粘合膜；以及
密封材料，将所述器件管芯密封在所述密封材料中，其中，所述密封材料接触所述第一介电层的顶面。
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CN113053757B (zh) * 2020-03-19 2024-05-24 台湾积体电路制造股份有限公司 封装件及其形成方法
CN113496899A (zh) * 2020-06-23 2021-10-12 台湾积体电路制造股份有限公司 封装件及其形成方法

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