TW201946232A - 封裝及其形成方法 - Google Patents

封裝及其形成方法 Download PDF

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Publication number
TW201946232A
TW201946232A TW107127209A TW107127209A TW201946232A TW 201946232 A TW201946232 A TW 201946232A TW 107127209 A TW107127209 A TW 107127209A TW 107127209 A TW107127209 A TW 107127209A TW 201946232 A TW201946232 A TW 201946232A
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Taiwan
Prior art keywords
dielectric layer
forming
top surface
layer
redistribution
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TW107127209A
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English (en)
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TWI674655B (zh
Inventor
王博漢
余振華
郭宏瑞
胡毓祥
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台灣積體電路製造股份有限公司
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Publication of TWI674655B publication Critical patent/TWI674655B/zh
Publication of TW201946232A publication Critical patent/TW201946232A/zh

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Abstract

一種封裝的形成方法，包括在載板上形成緩衝介電層，以及在緩衝介電層上形成第一介電層以及第一重佈線。第一重佈線位於第一介電層中。所述方法更包括對第一介電層執行平坦化以使第一介電層的頂表面變平，在第一重佈線上形成金屬支柱，金屬支柱電耦接至第一重佈線，以及將金屬支柱包封於包封材料中。包封材料與第一介電層的平坦化頂表面的頂表面接觸。

Description

封裝及其形成方法
隨著半導體技術的發展，半導體晶片/晶粒變得愈來愈小。同時，需要將更多的功能整合至半導體晶粒中。因此，半導體晶粒需要將愈來愈多的輸入/輸出（I/O）襯墊封裝於較小區域中，且I/O襯墊的密度隨著時間推移而快速增加。因此，半導體晶粒的封裝變得更加困難，而不利於封裝的良率。
習知封裝技術可劃分成兩個種類。在第一種類中，晶圓上的晶粒在被切割之前進行封裝。此封裝技術具有一些有利的特徵，例如，較大的產能（throughput）以及較低的成本。另外，所需要的底填充料或模製化合物較少。然而，此封裝技術也有缺點。由於晶粒的尺寸正變得愈來愈小，且相應封裝僅可為扇入型封裝，其中每一晶粒的I/O襯墊被限於相應晶粒的表面正上方的區域。由於晶粒的面積有限，I/O襯墊的數目由於I/O襯墊的間距限制而受到限制。若襯墊的間距減小，則可能會出現焊橋（solder bridge）。另外，在固定的球尺寸之要求下，焊球必須具有一特定尺寸，此又會限制可封裝於晶粒的表面上的焊球的數目。
在封裝的另一種類中，晶圓先被切割成晶粒，之後再對晶粒進行封裝。此封裝技術的有利特徵為形成扇出型封裝的可能性，此意味著可將晶粒上的I/O襯墊重新分配至比晶粒更大的區域，且因此可增加封裝於晶粒的表面上的I/O襯墊的數目。此封裝技術的另一有利特徵是封裝「良品晶粒（known-good-dies）」並捨棄有缺陷的晶粒，且因此不會在有缺陷的晶粒上浪費成本以及精力。
在扇出型封裝中，裝置晶粒包封於模製化合物中，所述模製化合物接著經平坦化以暴露出裝置晶粒。接著形成重佈線以連接至裝置晶粒。扇出型封裝亦可包括穿過模製化合物的穿孔（through-vias）。
以下揭露內容提供用於實施本揭露的不同特徵的許多不同實施例或實例。以下描述組件以及配置的具體實例以簡化本揭露。當然，這些僅為實例且並非用以限制。舉例而言，在以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵直接接觸地形成的實施例，且亦可包括在第一特徵與第二特徵之間可形成額外特徵使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複參考編號及/或字母。這種重複是出於簡單以及清晰起見，且並不表示所論述的各種實施例及/或配置之間的關係。
另外，為了易於描述附圖中所示的一個元件或特徵與另一元件或特徵的關係，本文中可使用例如「在…下」、「在…下方」、「下部」、「在…上」、「在…上方」、「上部」以及類似用語的空間相對用語。除附圖中所繪示的定向以外，所述空間相對用語意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向（旋轉80度或處於其他定向），且本文中所使用的空間相對用語可同樣相應地進行解釋。
根據各種例示性實施例提供一種扇出型封裝及其形成方法。根據一些實施例說明形成封裝的中間階段。實施例的一些變化亦將討論。在全文各視圖以及說明性實施例中，相似的參考標號用以表示相似元件。
圖1至圖13A是根據本揭露的一些實施例的形成封裝的中間階段的剖視圖。在圖24中繪示的製程流程200中亦示意性地反映圖1至圖13A中繪示的步驟。
圖1示出載板20以及形成於載板20上的離型薄膜（release film）22。載板20可為玻璃載板、矽晶圓、有機載板或類似物。載板20可具有圓形俯視圖形狀，且可具有普通矽晶圓的尺寸。舉例而言，載板20可具有8英吋直徑、12英吋直徑或類似尺寸。離型薄膜22可由基於聚合物的材料（例如，光熱轉換（Light-To-Heat-Conversion；LTHC）材料）形成，其可連同載板20一起從將在後續步驟中形成的上覆（overlying）結構移除。根據本揭露的一些實施例，離型薄膜22由環氧基熱釋放材料（epoxy-based thermal-release material）形成。離型薄膜22可被塗佈至載板20。離型薄膜22的頂表面平坦且具有高平坦度。
緩衝介電層（或稱為介電層）24形成於離型薄膜22上。根據本揭露的一些實施例，緩衝介電層24由聚合物形成，聚合物亦可為可藉由曝光以及顯影被圖案化的感光性材料，例如，聚苯並噁唑（polybenzoxazole, PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene, BCB）或其類似物。緩衝介電層24例如藉由烘烤製程被固化。根據本揭露的替代性實施例，介電層24由無機材料形成。無機材料例如是氧化矽、氮化矽、氮氧化矽、碳氮氧化矽或其類似物。
接下來，在介電層24上形成介電層26。根據本揭露的一些實施例，介電層26由聚合物形成，聚合物亦可為感光性材料，例如PBO、聚醯亞胺、BCB或其類似物。根據本揭露的替代性實施例，介電層26由無機材料形成，例如氧化矽、氮化矽、氮氧化矽、碳氮氧化矽或類似物。介電層26可具有大於約3 µm的厚度。所述厚度可在約3 µm至約10 µm的範圍中。介電層24以及介電層26可由相同或不同的介電材料形成。此外，在介電層24與介電層26之間可存在或可不存在可區分的界面。
進一步參看圖1，介電層26經圖案化以形成開口28。相應的製程在圖24所示的製程流程中被示為製程202。根據本揭露的一些實施例，介電層26由感光性材料形成，圖案化包括使用微影罩幕對介電層26曝光，且接著對被曝光的介電層26進行顯影。應理解，當介電層24與26由相同感光材料形成時，由於介電層24已經充分烘烤，因此曝光以及顯影將不會導致介電層24被圖案化。根據本揭露的替代性實施例，介電層26的圖案化包括微影製程，其更包括在介電層26上形成圖案化的光阻，以及將圖案化的光阻用作蝕刻罩幕來蝕刻介電層26。
參看圖2，例如藉由物理氣相沈積（Physical Vapor Deposition；PVD）形成金屬晶種層（或稱為晶種層）30。相應的製程在圖24所示的製程流程中被示為製程204。沈積形成毯覆式（blanket）金屬晶種層30，所述金屬晶種層延伸至開口28中。金屬晶種層30被形成為毯覆式層，其可包括黏著層（亦被稱作擴散阻障層或阻障層）以及位於黏著層上的含銅層。黏著層包括不同於銅的金屬，且可包括鈦、鉭、氮化鈦、氮化鉭或類似物。含銅層可由純銅或實質上純銅（例如，銅的百分比大於約95%）或銅合金形成。根據本揭露的替代性實施例，金屬晶種層30包括鈦、鉭、氮化鈦、氮化鉭或類似物，且不包括含銅層，且可被稱為黏著層。
圖3示出金屬材料32的沈積。相應的製程在圖24所示的製程流程中被示為製程206。根據一些實施例，金屬材料32藉由例如電化學鍍覆（electro-chemical plating；ECP）製程或無電鍍覆製程等鍍覆製程、物理氣相沈積製程或化學氣相沈積製程來沈積。金屬材料32可由純銅或實質上純銅（例如，銅的百分比大於約95%）或銅合金形成。
參看圖4，執行平坦化製程，例如化學機械研磨（Chemical Mechanical Polish；CMP）製程或機械研磨製程，以移除位於介電層26的頂表面上的晶種層30以及金屬材料32的多餘部分。相應的製程在圖24所示的製程流程中被示為製程208。晶種層30以及金屬材料32的剩餘部分被稱作重佈線（Redistribution Line；RDL）34。取決於將RDL 34的相應部分用於電佈線的目的或接合/著陸的目的，RDL 34可包括金屬跡線以及金屬襯墊。晶種層30、金屬材料32及介電層26的頂表面以及頂部邊緣因此共面。
作為平坦化製程的結果，RDL 34以及介電層26的頂表面可具有研磨標記，其為延伸至RDL 34以及介電層26中的刮痕（條形空隙）。研磨標記指示已對RDL 34以及介電層26執行平坦化製程。
圖5以及圖6示出金屬支柱42（圖6）的形成。參看圖5，例如藉由物理氣相沈積（PVD）形成金屬晶種層36（或稱為晶種層）。相應的製程在圖24所示的製程流程中被示為製程210。金屬晶種層36被形成為毯覆式且平坦的層。金屬晶種層36亦可包括黏著層以及位於黏著層上的含銅層。黏著層包括不同於銅的金屬，且可包括鈦、鉭、氮化鈦、氮化鉭或其類似物。含銅層可由純銅或實質上純銅（例如，銅百分比大於約95%）或銅合金形成。
在金屬晶種層36上形成圖案化的光阻38。相應的製程在圖24所示的製程流程中被示為製程212。接著使用光微影罩幕對光阻38執行曝光，接著進行顯影步驟以形成開口41，藉由開口41暴露出金屬晶種層36。
接下來，例如藉由在開口41中鍍覆金屬材料來形成金屬支柱40。相應的製程在圖24所示的製程流程被示為製程212。經鍍覆的金屬材料可為銅或銅合金。金屬支柱40的頂表面低於光阻38的頂表面，使得金屬支柱40的形狀被開口41限制。金屬支柱40可具有實質上垂直且直的邊緣。或者，金屬支柱40在剖視圖中可具有沙漏計時器（sand timer）形狀，其中金屬支柱40的中間部分比相應的頂部部分以及底部部分窄。
在後續步驟中，移除圖案化的光阻38，且因此暴露出金屬晶種層36的位於圖案化的光阻38下方的部分。接著在蝕刻步驟（例如，非等向性蝕刻或等向性蝕刻）中移除金屬晶種層36的被暴露的部分。相應的製程在圖24所示的製程流程中被示為製程214。所得結構如圖6所示。餘留的晶種層36的邊緣可因此與金屬支柱40的位於晶種層36上方的相應的部分齊平或實質上齊平，或者餘留的晶種層36可自位於其上方的金屬支柱40的相應邊緣橫向凹入，因此具有底切（undercut）。所得金屬支柱40如圖6所示。金屬支柱40與位於其下方的金屬晶種層36的剩餘部分共同地被稱作金屬支柱42。金屬支柱42的俯視圖形狀包括且不限於圓形形狀、矩形、六邊形（hexagon）、八邊形（octagon）以及類似形狀。金屬支柱42替代地被稱作穿孔或模製穿孔，這是因為其將穿過最終封裝中的後續形成的包封材料（其可為模製化合物）。在形成金屬支柱42之後，頂部介電層26再次暴露出來。
在金屬晶種層36的蝕刻期間，可形成凹陷44，其為蝕刻RDL 34中的金屬晶種層30中的黏著層的結果。舉例而言，當黏著層30與金屬晶種層36包括相同或類似材料（例如，鈦）時，金屬晶種層36的蝕刻（包括過度蝕刻以確保移除金屬晶種層36的不需要的部分）亦導致金屬晶種層30中的黏著層的頂部邊緣部分的凹陷。凹陷44可具有大於約0.2 µm的深度D1，且深度D1可在約0.2 µm至約0.5 µm的範圍中。當黏著層30與金屬晶種層36的材料不同且在金屬晶種層36的蝕刻期間具有高蝕刻選擇性時，可不形成凹陷。凹陷44形成於金屬晶種層30的暴露於蝕刻的部分上，而金屬晶種層30的被金屬支柱42保護的部分不會被蝕刻，且不形成凹陷。
圖7示出裝置46（替代地被稱作封裝組件）的放置/貼附。相應的製程在圖24所示的製程流程中被示為製程216。裝置46可為裝置晶粒，且因此在下文被稱作裝置晶粒46，同時裝置46亦可為封裝、晶粒堆疊（die stack）或類似物。裝置晶粒46藉由晶粒貼附膜（Die-Attach Film；DAF）48貼附至介電層26以及RDL 34。晶粒貼附膜48是在將裝置晶粒46放置於介電層26上之前預先貼附於裝置晶粒46上的黏著膜。DAF 48可與從中切割出裝置晶粒46的晶圓一起被切割，且因此DAF 48的邊緣與裝置晶粒46的相應邊緣齊平。裝置晶粒46可包括半導體基底，半導體基底具有與相應的其下方的DAF 48物理接觸（physical contact）的背表面（面朝下的表面）。裝置晶粒46可包括積體電路裝置，例如主動裝置，其包括在半導體基底的前表面（面朝上的表面）處的電晶體。根據本揭露的一些實施例，裝置晶粒46包括一個或多個邏輯晶粒，其可為中央處理單元（Central Processing Unit；CPU）晶粒、圖形處理單元（Graphic Processing Unit；GPU）晶粒、行動應用晶粒（mobile application die）、微型控制單元（Micro Control Unit；MCU）晶粒、輸入-輸出（input-output；IO）晶粒、基頻（BaseBand；BB）晶粒或應用程式處理器（Application processor；AP）晶粒。由於載板20為晶圓級（wafer-level）載板，因此雖然示出一個裝置晶粒46，但可在晶粒放置步驟中在介電層26上放置多個裝置晶粒46，且可將裝置晶粒排列成包括多個列以及多個行的陣列。
根據一些例示性實施例，金屬柱50（例如，銅柱）預形成為裝置晶粒46的一部分，且金屬柱50藉由其下方的金屬襯墊51（例如鋁銅襯墊）電耦接至裝置晶粒46中的積體電路裝置（例如電晶體）。根據本揭露的一些實施例，介電層，例如聚合物層52填充於相鄰金屬柱50之間的間隙，以形成頂部介電層。頂部介電層52亦可包括覆蓋且保護金屬柱50的一部分。根據本揭露的一些實施例，聚合物層52可由PBO或聚醯亞胺形成。
根據本揭露的一些實施例，由於圖4所示的平坦化製程，晶種層30、金屬材料32以及介電層26的頂表面以及頂部邊緣共面，且因此DAF 48被黏附至平坦的頂表面。沒有空隙（空隙可為氣隙）形成在DAF 48與其下方的結構之間。這可提高所得封裝的可靠性。作為比較，若未執行平坦化，則DAF 48將被放置於例如圖17中所繪示的非平坦頂表面上，空隙（氣隙）將會形成在DAF 48與其下方的結構之間，且封裝的可靠性會受到損害。
接下來，參看圖8，將裝置晶粒46及金屬支柱42包封於包封材料（或稱為模製材料）54中。相應製程在圖24所示的製程流程中被示為製程218。金屬支柱42穿過包封材料54，且在下文中被稱作穿孔。包封材料54填充相鄰穿孔42之間的間隙以及穿孔42與裝置晶粒46之間的間隙。包封材料54可為模製化合物、模製底填充料、環氧樹脂及/或樹脂。在包封之後，包封材料54的頂表面高於金屬柱50以及穿孔42的頂端。包封材料54可包括基礎材料（base material）54A（其可為聚合物、樹脂、環氧樹脂或類似物）以及基礎材料54A中的填料顆粒（filler particle）54B。填料顆粒可為介電材料（例如SiO2 、Al2 O3 、矽石（silica）或類似物）的顆粒，且可具有球形形狀（spherical shape）。又根據一些實例所示，球形填料顆粒54B可具有相同直徑或不同直徑。根據一些實施例，一些凹陷44（未繪示）未被DAF 48覆蓋。這些凹陷44可被包封材料54填充，或可被局部填充且餘留一些作為氣隙。
在後續步驟中，亦如圖8中所繪示，執行平坦化製程，例如化學機械研磨（Chemical Mechanical Polish；CMP）製程或機械研磨製程，以使包封材料54以及介電層52變薄，直到穿孔42以及金屬柱50全部暴露出來。穿孔42以及金屬柱50也可被輕微地研磨以確保穿孔42以及金屬柱50均暴露出來。因為平坦化製程，穿孔42的頂端與金屬柱50的頂表面齊平（共面）或實質上齊平，且與包封材料54的頂表面實質上共面。因為平坦化製程，在模製的包封材料54的頂部處的一些填料顆粒54B被部分研磨，從而使一些填料顆粒的頂部部分被移除，且底部部分余留下來，如圖8中所示的54B-1。因此使所得的部分填料顆粒54B-1的頂表面平坦，所述平坦頂表面與基礎材料54A、穿孔42以及金屬柱50的頂表面共面。
圖9至圖11示出前側RDL的形成。相應製程在圖24所示的製程流程中被示為製程220。參看圖9，形成介電層56。根據本揭露的一些實施例，介電層56是由例如聚合物（其可為PBO、聚醯亞胺或類似物）等有機介電材料形成。根據本揭露的替代性實施例，介電層56由例如氮化矽、氧化矽或類似物等無機介電材料形成。開口58形成於介電層56中，以暴露出穿孔42以及金屬柱50。開口58可藉由光微影製程（使用光阻進行蝕刻以定義圖案）或曝光製程以及後續顯影製程形成。
接下來，參看圖10，形成RDL 60，RDL 60連接至金屬柱50以及穿孔42。RDL 60亦可與金屬柱50及穿孔42互連。RDL 60包括在介電層56上的金屬跡線（金屬線），以及延伸至開口58（圖12）中以電連接至穿孔42以及金屬柱50的通孔。根據本揭露的一些實施例，RDL 60在鍍覆製程中形成，其中RDL 60中的每一者包括晶種層以及在晶種層上鍍覆的金屬材料。晶種層以及鍍覆材料可由相同材料或不同材料形成。RDL 60可包括金屬或金屬合金。金屬或金屬合金包括銅、鋁、鎢及其合金。RDL 60由非焊料材料形成。
進一步參看圖10，在RDL 60以及介電層56上形成介電層62。介電層62可使用有機材料形成，有機材料可選自與介電層56的候選材料相同的候選材料。舉例而言，介電層62可包括PBO、聚醯亞胺、BCB或類似物。替代地，介電層62可包括非有機介電材料，例如，氧化矽、氮化矽、碳化矽、氮氧化矽或類似物。開口64亦形成於介電層62中，以暴露出RDL 60。開口64可藉由光微影製程形成。根據本揭露的一些實施例，介電層62未被平坦化，且介電層62的頂表面不平坦。舉例而言，虛線62A示意性地示出介電層62的頂表面的形貌（topology）。在後續圖式中，為簡單起見，將介電層62的頂表面示出為平坦的，而實際的頂表面可能不平坦。
圖11示出電連接至RDL 60的RDL 66的形成。RDL 66的形成可採用與形成RDL 60的方法以及材料類似的方法以及材料。由於RDL 66及60位於裝置晶粒46的前側，因此RDL 66及60亦被稱作前側RDL。
如圖11中所示，形成額外的介電層68，以覆蓋RDL 66以及介電層62。介電層68可由選自用於形成介電層62及56的相同候選材料的材料形成。接著在介電層68中形成開口70，以暴露出RDL 66的金屬襯墊部分。根據一些實施例，由於沒有裝置晶粒藉由DAF黏附於介電層62及68上，因此介電層62及68未被平坦化，且介電層62與68的頂表面不平坦，此類似於圖10中示意性示出的介電層62的頂部不平坦頂表面62A。
圖12示出根據一些例示性實施例的凸塊下金屬（Under-Bump Metallurgy；UBM）72以及電連接件74的形成。相應的製程在圖24所示的製程流程中被示為製程222。UBM 72的形成可包括沈積製程以及圖案化製程。電連接件74的形成可包括將焊球放置於UBM 72的被暴露出的部分上，且接著回焊焊球。根據本揭露的替代性實施例，電連接件74的形成包括執行鍍覆步驟，以在UBM 72上形成焊料區域，且接著回焊焊料區域。電連接件74亦可包括可藉由鍍覆形成的金屬柱或金屬柱與焊蓋（solder cap）的組合結構。貫穿全文，包括裝置晶粒46、穿孔42、模製材料54以及對應的RDL與介電層的組合結構被稱作封裝100，其可為具有圓形俯視圖形狀的複合晶圓100。
接下來，將封裝100從載板20剝離。將複合晶圓100放置於膠帶上，使得複合晶圓100可從載板20拆卸下來，例如，藉由將光（例如，雷射光束）投射於離型薄膜22上，且光穿過透明載板20。離型薄膜22因此分解，且複合晶圓100從載板20脫離。
參看圖13A，在緩衝介電層24中形成開口（由焊料區域84佔據），且因此暴露出RDL 34的黏著層30。根據本揭露的一些實施例，開口藉由雷射鑽孔形成。根據本揭露的替代性實施例，開口藉由微影製程中的蝕刻形成。接著金屬晶種層30中的黏著層被蝕刻穿，以露出含銅區域（金屬材料）32。
複合晶圓100包括彼此等同的多個封裝76，其中每個封裝76包括多個穿孔42以及一個或多個裝置晶粒46。圖13A亦示出將封裝78接合至封裝76上，因此形成疊層封裝（Package-on-Package；PoP）結構/封裝88。所述接合藉由焊料區域（電連接件）74來執行。根據本揭露的一些實施例，封裝78包括封裝基底82以及裝置晶粒80。裝置晶粒80可為記憶體晶粒，例如靜態隨機存取記憶體（Static Random Access Memory；SRAM）晶粒、動態隨機存取記憶體（Dynamic Random Access Memory；DRAM）晶粒或類似物。底填充料83亦設置於封裝86與其下方的封裝76之間的間隙中，且被固化。執行單體化（singulation）（晶粒切割）製程，以將複合晶圓100及接合於其上的封裝78分離成彼此等同的單獨的封裝88。
圖13A亦示出將單體化的封裝88藉由焊料區域84接合至封裝組件90。根據本揭露的一些實施例，封裝組件90為封裝基底，其可為無核心基底（coreless substrate）或具有核心（core）（例如，玻璃纖維加強型核心（fiberglass-reinforced core））的基底。根據本揭露的其他實施例，封裝組件90是印刷電路板或封裝。圖13A中的封裝在下文被稱作封裝92。
圖13B示出根據本揭露的替代性實施例的封裝92。這些實施例類似於圖13A中所示的實施例，惟穿孔42可比其下方的RDL 34更窄除外。因此，黏著層30的頂部邊緣與模製材料54接觸。在一些實施例中，黏著層30的頂部邊緣在圖6所示的步驟中凹陷。因此，凹陷44（如由虛線表示）被形成為延伸至黏著層30的頂部部分中，且凹陷44延伸至晶種層30的頂部部分中。
圖13B示出RDL 34的剖視圖具有倒梯形輪廓。根據替代性實施例，RDL 34的剖視圖可具有垂直邊緣，如由虛線96A所示，虛線96A表示對應的RDL 34的側壁。根據另一替代性實施例，RDL 34的剖視圖可具有梯形輪廓，如由虛線96B所示，虛線96B表示對應的RDL 34的側壁。
圖14至圖23示出根據本揭露的替代性實施例所形成的封裝的剖視圖。除非另有指定，否則在這些實施例中的組件的材料以及形成方法與圖1至圖13A及圖13B中所示的實施例中的相似參考標號表示的相似組件實質上相同。關於圖14至圖23中所示的組件的形成製程以及材料的細節可因此參考圖1至圖13A/13B中所示的實施例的描述。
參看圖14，在載板20上形成離型薄膜22，且在離型薄膜22上形成介電層24。接著在介電層24上形成金屬晶種層110。金屬晶種層110可具有類似於金屬晶種層30（圖2）的結構且可由與金屬晶種層30（圖2）的材料類似的材料形成。舉例而言，金屬晶種層110可包括黏著層以及在黏著層上的含銅層。
參看圖15，在金屬晶種層110上形成圖案化的光阻112，且金屬晶種層110的一些部分被暴露出來。接著例如藉由鍍覆在光阻112中的開口中形成RDL 114。RDL 114可由銅、鋁、鋁銅或類似物形成。在形成RDL 114後，移除光阻112，並蝕刻金屬晶種層110的先前被光阻112覆蓋的部分。所得結構如圖16所示。貫穿全文，RDL 114及其下方的金屬晶種層110的餘留部分共同被稱作RDL 116。RDL 116可具有大於約3 µm的厚度。所述厚度可在約3 µm至約10 µm的範圍中。
圖17示出介電層118的形成。根據本揭露的一些實施例，介電層118由聚合物形成，聚合物亦可為感光性材料，例如PBO、聚醯亞胺、BCB或類似物。根據本揭露的替代性實施例，介電層118由無機材料形成，無機材料例如是氧化矽、氮化矽、氮氧化矽、碳氮氧化矽或類似物。
由於突出且高於介電層24的RDL 116，介電層118的頂表面不平坦。若裝置晶粒藉由DAF黏附至介電層118的不平坦頂表面的頂表面，則將會在DAF與介電層118之間形成空隙，且封裝的可靠性將受到不利影響。根據本揭露的一些實施例，如圖18中所示，執行平坦化製程，例如CMP或機械研磨製程，以使介電層118的頂表面平坦化。
參看圖19，例如藉由蝕刻製程在介電層118中形成開口120。因此暴露出RDL 116的一些部分。接下來，如圖20所示，形成金屬晶種層122。形成方法以及材料可選自用於形成金屬晶種層36（圖5）的候選方法以及材料的相同族群。接著形成圖案化的光阻124，隨後在光阻124的開口中鍍覆金屬材料40。
在後續步驟中，移除光阻124，並蝕刻金屬晶種層122先前被光阻124覆蓋的部分，從而形成如圖21所示的金屬支柱（穿孔）42。金屬支柱42包括金屬材料40（其可由銅或銅合金形成）以及其下方的金屬晶種層122的餘留部分。通孔126亦與金屬支柱42同時形成。通孔126位於介電層118中，且將金屬支柱42電連接至RDL 116。
圖22示出藉由DAF 48將裝置晶粒46貼附至平坦化的介電層118。接著，將裝置晶粒46以及金屬支柱42包封於包封材料54中，隨後執行平坦化製程，例如CMP製程或機械研磨製程，以使裝置晶粒46以及金屬支柱42的頂表面平坦化。下文中，金屬支柱42替代地被稱作穿孔42。在後續製程，執行類似於圖9至圖13A所示的其餘製程，以形成圖23中所示的上覆結構。上覆結構包括RDL 60以及66、介電層56、62以及68、UBM 72以及電連接件74。接合封裝組件78，且執行晶粒切割以形成與所示出的PoP封裝88等同的多個PoP封裝。將PoP封裝88接合至封裝組件90，從而形成如圖23所示的封裝92。
在以上說明的例示性實施例中，根據本揭露的一些實施例論述一些例示性製程以及特徵。亦可包括其他特徵以及製程。舉例而言，可包括測試結構以輔助對3D封裝或3DIC裝置的驗證測試。測試結構可包括，例如，形成於重佈層中或基底上的測試襯墊，其允許測試3D封裝或3DIC、探針及/或探針卡的使用以及類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構以及方法可結合併入對良品晶粒的中間驗證的測試方法使用，以增大良率以及降低成本。
本揭露的實施例具有一些有利特徵。藉由對介電層以及RDL執行平坦化製程形成平坦頂表面，以用於將裝置晶粒以及DAF貼附於其上，且因此沒有空隙（氣隙）形成於DAF與下方介電層之間。封裝的可靠性得以提高。
根據本揭露的一些實施例，一種封裝的形成方法包括在載板上形成緩衝介電層，以及在緩衝介電層上形成第一介電層以及第一重佈線。第一重佈線位於第一介電層中。所述方法更包括對第一介電層執行平坦化以使第一介電層的頂表面變平，形成在第一重佈線上且電耦接至第一重佈線的金屬支柱，以及包封金屬支柱於包封材料中。包封材料接觸第一介電層的平坦化頂表面的頂表面。在實施例中，所述方法包括形成在包封材料以及金屬支柱上且接觸包封材料以及金屬支柱的第二介電層；形成第二重佈線，其包括延伸至第二介電層中以連接至金屬支柱的通孔部分；在第二介電層以及第二重佈線上形成第三介電層，其中第三介電層未被平坦化；以及在第三介電層的不平坦頂表面上形成第四介電層，第四介電層接觸第三介電層的不平坦頂表面。在實施例中，形成第一重佈線包括：在第一介電層中形成開口；形成延伸至開口中的第一晶種層；在第一晶種層上形成第一金屬材料；以及平坦化第一金屬材料、第一晶種層以及第一介電層。在實施例中，形成金屬支柱包括：在第一介電層以及第一重佈線上形成第二晶種層，第二晶種層接觸第一介電層以及第一重佈線；在第二晶種層上形成圖案化的光阻；在第二晶種層上以及在圖案化的光阻中的開口中鍍覆第二金屬材料；以及移除圖案化的光阻以及位於被移除的圖案化的光阻正下方的部分的第二晶種層。在實施例中，形成第一重佈線包括在緩衝介電層上形成第一晶種層，且第一晶種層接觸緩衝介電層；在第一晶種層上形成圖案化的光阻；在第一晶種層上以及在圖案化的光阻中的開口中鍍覆金屬材料；以及移除圖案化的光阻以及位於被移除的圖案化的光阻正下方的部分的第一晶種層，其中在移除圖案化的光阻以及部分的第一晶種層後形成第一介電層。在實施例中，在平坦化後，整個第一重佈線位於第一介電層的平坦化頂表面的頂表面下方。在實施例中，在用於形成第一重佈線的同一製程中形成第三重佈線，且所述方法更包括藉由黏著膜將裝置晶粒貼附至第一介電層，其中黏著膜與第一介電層的頂表面以及第三重佈線的頂表面物理接觸。在實施例中，形成金屬支柱導致在第一重佈線的阻障層的頂部邊緣部分中形成凹陷。
根據本揭露的一些實施例，一種封裝的形成方法包括在載板上形成緩衝介電層；在載板上形成第一介電層；在第一介電層中形成第一開口以及第二開口；分別在第一開口以及第二開口中形成第一重佈線以及第二重佈線；平坦化第一介電層的頂表面；藉由黏著膜將裝置晶粒貼附至第一介電層的頂表面，其中黏著膜與第一介電層的平坦化頂表面以及第一重佈線的頂表面物理接觸；以及包封裝置晶粒於包封材料中。在實施例中，所述方法更包括在第二重佈線上形成金屬支柱，金屬支柱接觸第二重佈線，形成金屬支柱包括：在第一介電層、第一重佈線以及第二重佈線上形成金屬晶種層，金屬晶種層接觸第一介電層、第一重佈線以及第二重佈線；在金屬晶種層上鍍覆金屬材料；以及移除金屬晶種層的不需要的部分，其中與第一重佈線接觸的所有金屬晶種層被移除。在實施例中，金屬支柱交疊並接觸第二重佈線的第一部分，且包封材料交疊並接觸第二重佈線的第二部分。在實施例中，形成金屬支柱導致在第一重佈線的阻障層的頂部邊緣部分中形成凹陷。在實施例中，包封材料接觸第一介電層的平坦化頂表面的頂表面。在實施例中，在平坦化中，第一介電層、第一重佈線以及第二重佈線被平坦化。
根據本揭露的一些實施例，一種封裝包括：第一介電層；第一重佈線以及第二重佈線，位於第一介電層中；黏著膜，位於第一介電層的頂表面以及第一重佈線的頂表面兩者之上，且與第一介電層的頂表面以及第一重佈線的頂表面兩者接觸；裝置晶粒，在黏著膜上且黏附至黏著膜；以及包封材料，將裝置晶粒包封於其中，其中包封材料接觸第一介電層的頂表面。在實施例中，封裝更包括穿孔，位於第二重佈線的頂表面正上方且接觸第二重佈線的頂表面，其中穿孔被包封於包封材料中，其中穿孔包括擴散阻障層以及位於擴散阻障層上的金屬材料，且整個擴散阻障層是平坦的。在實施例中，穿孔比第二重佈線寬，且擴散阻障層在第一介電層的頂表面上延伸。在實施例中，穿孔比第二重佈線窄，且包封材料與第二重佈線的頂表面接觸。在實施例中，封裝更包括第二介電層，位於包封材料上；第二重佈線，包括延伸至第二介電層中以連接至裝置晶粒的通孔部分；以及第三介電層，位於第二介電層以及第二重佈線上，其中第三介電層具有不平坦頂表面，所述不平坦頂表面具有依循其下方特徵的形貌的形貌。在實施例中，第一重佈線具有擴散阻障層，且擴散阻障層的頂部邊緣凹陷，且低於第一介電層的頂表面。
以上概述了數個實施例的特徵，使本領域技術人員可更加瞭解本揭露的態樣。本領域技術人員應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實現本文所介紹的實施例的相同目的及/或達到相同優點。本領域技術人員還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域技術人員在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
20‧‧‧載板
22‧‧‧離型薄膜
24‧‧‧緩衝介電層/介電層
26、56、62、68、118‧‧‧介電層
28、41、58、64、70、120‧‧‧開口
30、36、110、122‧‧‧金屬晶種層/晶種層
32‧‧‧金屬材料
34、60、66、114、116‧‧‧重佈線（RDL）
38、124‧‧‧圖案化的光阻/光阻
40‧‧‧金屬支柱/金屬材料
42‧‧‧金屬支柱/穿孔
44‧‧‧凹陷
46、80‧‧‧裝置晶粒
48‧‧‧晶粒貼附膜（DAF）
50‧‧‧金屬柱
51‧‧‧金屬襯墊
52‧‧‧聚合物層/介電層
54‧‧‧包封材料/模製材料
54A‧‧‧基礎材料
54B‧‧‧填料顆粒
54B-1‧‧‧部分填料顆粒
62A‧‧‧頂部不平坦頂表面
72‧‧‧凸塊下金屬（UBM）
74‧‧‧電連接件
76、78、88、92、100‧‧‧封裝
82‧‧‧封裝基底
83‧‧‧底填充料
84‧‧‧焊料區域
90‧‧‧封裝組件
96A、96B‧‧‧虛線/RDL的側壁
112‧‧‧光阻
126‧‧‧通孔
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218、220、222‧‧‧製程
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的態樣。應注意，根據本行業中的標準慣例，各種特徵未按比例繪製。事實上，為使論述清楚起見，可任意地增大或減小各種特徵的尺寸。 圖1至圖13A是根據一些實施例的形成封裝的中間階段的剖視圖。 圖13B是根據一些實施例的封裝的剖視圖。 圖14至圖23是根據一些實施例的形成封裝的中間階段的剖視圖。 圖24是根據一些實施例的形成封裝的製程流程。

Claims (20)

  1. 一種封裝的形成方法，包括： 在載板上形成緩衝介電層； 在所述緩衝介電層上形成第一介電層以及第一重佈線，其中所述第一重佈線位於所述第一介電層中； 對所述第一介電層執行平坦化，以使所述第一介電層的頂表面變平，由此形成所述第一介電層的平坦化頂表面； 在所述第一重佈線上形成金屬支柱，其中所述金屬支柱電耦接至所述第一重佈線；以及 包封所述金屬支柱於包封材料中，其中所述包封材料與所述第一介電層的所述平坦化頂表面接觸。
  2. 如申請專利範圍第1項所述的封裝的形成方法，更包括： 在所述包封材料以及所述金屬支柱上形成第二介電層，且所述第二介電層與所述包封材料以及所述金屬支柱接觸； 形成第二重佈線，所述第二重佈線包括通孔部分，所述通孔部分延伸至所述第二介電層中以與所述金屬支柱連接； 在所述第二介電層以及所述第二重佈線上形成第三介電層，其中所述第三介電層未被平坦化且包括不平坦頂表面；以及 在所述第三介電層的所述不平坦頂表面上形成第四介電層，且所述第四介電層與所述第三介電層的所述不平坦頂表面接觸。
  3. 如申請專利範圍第1項所述的封裝的形成方法，其中所述形成所述第一重佈線包括： 在所述第一介電層中形成開口； 形成延伸至所述開口中的第一晶種層； 在所述第一晶種層上形成第一金屬材料；以及 平坦化所述第一金屬材料、所述第一晶種層以及所述第一介電層。
  4. 如申請專利範圍第3項所述的封裝的形成方法，其中所述形成所述金屬支柱包括： 在所述第一介電層以及所述第一重佈線的正上方形成第二晶種層； 在所述第二晶種層上形成圖案化的光阻； 在所述第二晶種層上及所述圖案化的光阻的開口中鍍覆第二金屬材料；以及 移除所述圖案化的光阻以及位於所述圖案化的光阻正下方的部分的所述第二晶種層。
  5. 如申請專利範圍第3項所述的封裝的形成方法，其中所述形成所述金屬支柱導致在所述第一介電層中的所述開口中的所述第一晶種層的頂部邊緣部分中形成凹陷。
  6. 如申請專利範圍第1項所述的封裝的形成方法，其中所述形成所述第一重佈線包括： 在所述緩衝介電層上形成第一晶種層，且所述第一晶種層與所述緩衝介電層接觸； 在所述第一晶種層上形成圖案化的光阻； 在所述第一晶種層上以及在所述圖案化的光阻中的開口中鍍覆金屬材料；以及 移除所述圖案化的光阻以及位於所述圖案化的光阻正下方的部分的所述第一晶種層，其中在所述移除所述圖案化的光阻以及所述部分的所述第一晶種層後形成所述第一介電層。
  7. 如申請專利範圍第6項所述的封裝的形成方法，其中在所述平坦化後，整個所述第一重佈線位於所述第一介電層的所述平坦化頂表面的頂表面下方。
  8. 如申請專利範圍第1項所述的封裝的形成方法，其中在用於形成所述第一重佈線的同一製程中形成第三重佈線，且所述方法更包括： 藉由黏著膜將裝置晶粒貼附至所述第一介電層，其中所述黏著膜與所述第一介電層的所述平坦化頂表面以及所述第三重佈線的頂表面物理接觸。
  9. 一種封裝的形成方法，包括： 在載板上形成緩衝介電層； 在所述載板上形成第一介電層； 在所述第一介電層中形成第一開口以及第二開口； 分別在所述第一開口以及所述第二開口中形成第一重佈線以及第二重佈線； 平坦化所述第一介電層的頂表面，由此形成所述第一介電層的平坦化頂表面； 藉由黏著膜將裝置晶粒貼附至所述第一介電層的所述平坦化頂表面，其中所述黏著膜與所述第一介電層的所述平坦化頂表面以及所述第一重佈線的頂表面物理接觸；以及 包封所述裝置晶粒於包封材料中。
  10. 如申請專利範圍第9項所述的封裝的形成方法，更包括： 在所述第二重佈線正上方形成金屬支柱，所述形成所述金屬支柱包括： 在所述第一介電層、所述第一重佈線以及所述第二重佈線上形成金屬晶種層； 在所述金屬晶種層上鍍覆金屬材料；以及 移除不在所述金屬材料下方的部分的所述金屬晶種層。
  11. 如申請專利範圍第10項所述的封裝的形成方法，其中所述金屬支柱交疊並接觸所述第二重佈線的第一部分，且所述包封材料交疊並接觸所述第二重佈線的第二部分。
  12. 如申請專利範圍第10項所述的封裝的形成方法，其中所述形成所述金屬支柱導致在所述第一重佈線的阻障層的頂部邊緣部分中形成凹陷。
  13. 如申請專利範圍第9項所述的封裝的形成方法，其中所述包封材料與所述第一介電層的所述平坦化頂表面的頂表面接觸。
  14. 如申請專利範圍第9項所述的封裝的形成方法，其中在所述平坦化中，所述第一介電層、所述第一重佈線以及所述第二重佈線被平坦化。
  15. 一種封裝，包括： 第一介電層； 第一重佈線以及第二重佈線，位於所述第一介電層中； 黏著膜，位於所述第一介電層的頂表面以及所述第一重佈線的頂表面兩者之上，且與所述第一介電層的所述頂表面以及所述第一重佈線的所述頂表面兩者接觸； 裝置晶粒，位於所述黏著膜上且黏附至所述黏著膜；以及 包封材料，將所述裝置晶粒包封於其中，其中所述包封材料與所述第一介電層的所述頂表面接觸。
  16. 如申請專利範圍第15項所述的封裝，更包括： 穿孔，位於所述第二重佈線的頂表面正上方，其中所述穿孔被包封於所述包封材料中，其中所述穿孔包括擴散阻障層以及位於所述擴散阻障層上的金屬材料，且整個所述擴散阻障層是平坦的。
  17. 如申請專利範圍第16項所述的封裝，其中所述穿孔比所述第二重佈線寬，且所述擴散阻障層在所述第一介電層的所述頂表面上延伸。
  18. 如申請專利範圍第16項所述的封裝，其中所述穿孔比所述第二重佈線窄，且所述包封材料與所述第二重佈線的所述頂表面接觸。
  19. 如申請專利範圍第15項所述的封裝，更包括： 第二介電層，位於所述包封材料上； 第二重佈線，包括延伸至所述第二介電層中以連接至所述裝置晶粒的通孔部分；以及 第三介電層，位於所述第二介電層以及所述第二重佈線上，其中所述第三介電層具有不平坦頂表面，所述不平坦頂表面具有依循其下方特徵的形貌的形貌。
  20. 如申請專利範圍第15項所述的封裝，其中所述第一重佈線具有擴散阻障層，且所述擴散阻障層的頂部邊緣凹陷，且低於所述第一介電層的所述頂表面。
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